Carry-propagate Adder Research Articles

An Exact Leading Non-Zero Detector for a Floating-Point Unit

Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.

Architecture and implementation of a vector/SIMD multiply-accumulate unit

This work presents 64-bit fixed-point vector multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 64/spl times/64, two 32/spl times/32, four 16/spl times/16, or eight 8/spl times/8 bit signed/unsigned multiply using essentially the same hardware as a scalar 64-bit MAC and with only a small increase in delay. The scalar MAC architecture is "vectorized" by inserting mode-dependent multiplexing into the partial product generation and by inserting mode-dependent kills in the carry chain of the reduction tree and the final carry-propagate adder. This is an example of "shared segmentation" in which the existing scalar structure is segmented and then shared between vector modes. The vector MAC is area efficient and can be fully pipelined, which makes it suitable for high-performance processors and, possibly, dynamically reconfigurable processors. The "shared segmentation" method is compared to an alternative method, referred to as the "shared subtree" method, by implementing vector MAC designs using two different technologies and three different vector widths.

Arithmetic binary to residue encoders for moduli (2n±2k+1)

A binary-to-residue encoder design that encodes the binary value into modulo (2n±2k+1) residue digits is introduced. Such encoders are important for the newly introduced moduli set: (2n,2n-1,2n+1,2n-2k+1,2n+2k+1), where k is a positive integer, and n=2k-1. The proposed design utilises n bit carry-save adders and carry-propagate adders. A VLSI layout implementation based on 0.5 μm CMOS technology is presented. The area and delay requirements of the new encoders are shown to be less than another reported encoder.

Fast converter for 3 moduli RNS using new property of CRT

This paper presents a new fast RNS converter for the 3 moduli set of the form {2/sup n/-1,2/sup n/,2/sup n/+1}. A new property of the Chinese remainder theorem (CRT) is also presented and this property is used to develop a fast converter for this 3 moduli set. The resulting implementation is based on carry-save adders and one carry-propagate adder stage, without the need for any look-up tables. The new design is faster and smaller than existing designs.

Hardware implementation of the Lehmer random number generator

Multiplicative linear congruential pseudorandom number generators are a popular choice for many software routines. The paper describes fast hardware implementation of the Lehmer generator which belongs to the above class. First, using the Sylvester resultant matrices it is shown that the algorithm to generate the next random number, which is based on multiplication modM, can be reduced to the problem of addition/subtraction of six appropriately rotated copies of the current random number. Secondly, addition/subtraction of six numbers modM can be performed by means of three carry-save adders, one carry-propagate subtracter, and one carry-propagate adder.

Parallel reduced area multipliers

As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction of the partial products. The reduction scheme can be applied to either unsigned (sign-magnitude) or two's complement numbers. Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead for Wallace, Dadda, and Reduced Area multipliers. Area estimates indicate that for non-pipelined multipliers, the reduction in area achieved with Reduced Area multipliers ranges from 3.7 to 6.6 percent relative to Dadda multipliers, and from 3.8 to 8.4 percent relative to Wallace multipliers. For fully pipelined multipliers, the reduction in area ranges from 15.1 to 33.6 percent relative to Dadda multipliers, and from 2.9 to 9.0 percent relative to Wallace multipliers.

On-the-fly rounding (computing arithmetic)

In implementations of operations based on digit-recurrence algorithms such as division, left-to-right multiplication and square root, the result is obtained in digit-serial form, from most significant digit to least significant. To reduce the complexity of the result-digit selection and allow the use of redundant addition, the result-digit has values from a signed-digit set. As a consequence, the result has to be converted to conventional representation, which can be done on-the-fly as the digits are produced, without the use of a carry-propagate adder. The authors describe three ways to modify this conversion process so that the result is rounded. The resulting operation is fast because no carry-propagate addition is needed. The schemes described apply also to online arithmetic operations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fast multiplication without carry-propagate addition

Conventional schemes for fast multiplication accumulate the partial products in redundant form (carry-save or signed-digit) and convert the result to conventional representation in the last step. This step requires a carry-propagate adder which is comparatively slow and occupies a significant area of the chip in a VLSI implementation. A report is presented on a multiplication scheme (left-to-right, carry-free, LRCF) that does not require this carry-propagate step. The LRCF scheme performs the multiplication most-significant bit first and produces a conventional sign-and-magnitude product (most significant n bits) by means of an on-the-fly conversion. The resulting implementation is fast and regular and is very well suited for VLSI. The LRCF scheme for general radix r and a radix-4 signed-digit implementation are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fast inner product processor based on equal alignments

Inner product computation is an important operation, invoked repeatedly in matrix multiplications. A high-speed inner product processor can be very useful (among many possible applications) in real-time signal processing. This paper presents the design of a fast inner product processor, with appreciably reduced latency and cost. The inner product processor is implemented with a tree of carry-propagate or carry-save adders; this structure is obtained with the incorporation of three innovations in the conventional multiply/add tree: (1) The leaf-multipliers are expanded into adder subtrees, thus achieving an O(log Nb) latency, where N denotes the number of elements in a vector and b the number of bits in each element. (2) The partial products, to be summed in producing an inner product, are reordered according to their “minimum alignments.” This reordering brings approximately a 20% saving in hardware—including adders and data paths. The reduction in adder widths also yields savings in carry propagation time for carry-propagate adders. (3) For trees implemented with carry-save adders, the partial product reordering also serves to truncate the carry propagation chain in the final propagation stage by 2 log b − 1 positions, thus significantly reducing the latency further. A form of the Baugh and Wooley algorithm is adopted to implement two's complement notation with changes only in peripheral hardware.