Carry Lookahead Adder Research Articles

Outperforming Sequential Full-Word Long Addition With Parallelization and Vectorization

The article presents algorithms for parallel and vectorized full-word addition of big unsigned integers with carry propagation. Because of the propagation, software parallelization and vectorization of non-polynomial addition of big integers have long been considered impractical due to data dependencies between digits of the operands. The presented algorithms are based upon parallel and vectorized detection of carry origins within elements of vector operands, masking bits which correspond to those elements and subsequent scalar addition of the resulting integers. The acquired bits can consequently be taken into account to adjust the sum using the proposed generalization of the Kogge-Stone method. Essentially, the article formalizes and experimentally verifies parallel and vectorized implementation of carry-lookahead adders applied at arbitrary granularity of data. This approach is noticeably beneficial for manycore, CUDA and vectorized implementation using AVX-512 with masked instructions. Experiments show that the parallel and vectorized implementations of the proposed algorithms can be multiple times faster compared to a sequential ripple-carry adder or adders based on redundant number systems such as one used in the GNU Multiple Precision library.

Design Optimization of the 64-Bit Carry Look-Ahead Adder Based on FPGA and Verilog HDL

Design Optimization of the 64-Bit Carry Look-Ahead Adder Based on FPGA and Verilog HDL

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Multiplication is one of the most basic processes, in digital signal processing applications. To process the instructions, most processors require multiplication. Because multipliers are employed in almost all arithmetic operations, they consume the majority of time and power. As a nutshell, the multiplier's efficiency is critical in terms of enhancing processor performance. The array multiplier is one of the most efficient multipliers since it is both quick and simple. However, power consumption is high. The basic components of an array multiplier are adders. The multiplier's efficiency will improve if the adders are much more efficient. The prior study used Complementary Metal Oxide Semiconductor (CMOS) to construct a Quaternary Carry-Lookahead Adder (CLA) that substitutes the adder circuit in the array multiplier. Quaternary number system circuits are quicker than binary number system circuits and can execute arithmetic operations without carry. However, Quaternary circuits take up more space. As a solution, the Quaternary Carry Increment Adder (CIA) is proposed. The proposed adder consumes less power and occupies less area than the existing Quaternary CLA. In the array multiplier, the Quaternary CIA substitutes the Quaternary CLA. This helps to lower the multiplier's power and area consumption. Tanner EDA tool is used to designing the circuits and were simulated with 180 nm technology. Various parameters such as delay, power and power-delay product of the existing and the proposed are measured and compared.

High-Speed and Energy-Efficient Carry Look-Ahead Adder

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

A Novel Design of High-Performance Hybrid Multiplier

In this brief, a novel design of hybrid multiplier is proposed. The hybrid multiplier is a combination of two different types of multipliers. The latest computing systems require low-power, area, and delay multipliers. In this work, we extend a new idea of high-performance hybrid multiplier by using Wallace–Dadda and Vedic multipliers. The addition of partial products is done by dividing them into smaller groups to obtain faster results. The proposed method is illustrated by designing an 8-bit hybrid multiplier in which the partial products are divided into four subgroups. In this analysis, two different multipliers are applied to alternative groups. Finally, the carry look ahead adder (CLA) is used to reduce carry propagation delay in the proposed hybrid multiplier. The proposed hybrid multiplier has been synthesized using the Cadence virtuoso tool using a 45-nm CMOS technology. This hybrid multiplier is faster, consumes less power, and occupies less area as compared to the conventional hybrid multipliers.

Comparative Analysis of Optimization Schemes of Carry Look-ahead Adder

Conventional CLA adder has has a large number of transistors and high input impedance, which affects various performance aspects, resulting in high delay and power consumption. Therefore, to increase the performance and reduce delay, several optimized structures of CLA are proposed. From the perspective of structure and power, this paper selects four different design schemes and uses Cadence Virtuoso 90nm technology to compare and analyze the optimization results in aspects of circuit area, delay and power consumption. The analysis results show that the conventional 4-bit adder structure can be improved by designing the carry term Field Effect Transistor (FET) network and replacing the existing gate circuit with a hybrid Gate diffusion technology (GDI) gate, which can reduce the number of transistors and the design circuit area. They also contribute to improving the power consumption, delay, power delay product (PDP) and other performance parameters. Pipeline technology and multi-layer CLA block technology are suitable for carry look-ahead adder with more bits and longer carry chain, which can shorten carry propagation time, further optimize processor performance and improve CPU computing efficiency.

Performance Comparison for FinFET Nanoscale Static and Domino Logic Circuits

The future prospects of complementary metal oxide semiconductor (CMOS) technology are estimated to be replaced by fin-shaped field effect transistor (FinFET) owing to its strong channel control, high driving capability and ease of fabrication. This paper envisages the effects of voltage, temperature and fin variation on power dissipation and delay for static and domino logic circuits. Circuit behavior becomes unpredictable due to process, voltage and temperature (PVT) variations such as irregular power consumption and performance deviation. It also accelerates circuit deterioration and makes them ineffective. The important circuit level leakage power reduction techniques like LCNT, LECTOR and INDEP have been applied to basic gates, 3-bit carry look ahead adder (CLA) and domino logic circuits at 16 nm FinFET technology. It is found that power delay product (PDP) in CLA using INDEP technique exhibits 61.48% less than conventional CLA. Leakage power reduction techniques have also been verified for the footer domino logic (FDL) circuit and performed Monte Carlo simulations for 10000 samples for reliability analysis. INDEP circuits are robust to PVT variations. The simulations have been completed using Cadence Virtuoso tool.

A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology

In this paper, a new hybrid low-power and area efficient Carry Look-Ahead Adder in CNFET technology based on the full-swing Gate Diffusion Input (GDI) technique is proposed. The proposed CLA design in GDI logic style, not only decreases the circuit area effectively but also decreases the power consumption and delay parameters as well. The proposed design is simulated in HSPICE using the CNFET model parameters. Finally, the simulation results justify a good improvement in the circuit performance parameters such as power consumption, delay, chip size area and power-delay product (PDP) for the proposed CLA circuit.

Implementation of three efficient 4-digit fault-tolerant quantum carry lookahead adders

Adders are one of the most interesting circuits in quantum computing due to their use in major algorithms that benefit from the special characteristics of this type of computation. Among these algorithms, Shor’s algorithm stands out, which allows decomposing numbers in a time exponentially lower than the time needed to do it with classical computation. In this work, we propose three fault-tolerant carry lookahead adders that improve the cost in terms of quantum gates and qubits with respect to the rest of quantum circuits available in the literature. Their optimal implementation in a real quantum computer is also presented. Finally, the work ends with a rigorous comparison where the advantages and disadvantages of the proposed circuits against the rest of the circuits of the state of the art are exposed. Moreover, the information obtained from such a comparison is summarized in tables that allow a quick consultation to interested researchers.

High-Performance 10-Transistor Adder Cell for Low-Power Applications

Addition is one of the most fundamental arithmetic operations. Any adder in a digital circuit and system can improve the digital system's performance. Adders, for example, are commonly found in the critical path of many ALUs, processors, and digital signal processing chips. As a result, each of these blocks should execute efficiently and precisely on their own, enhancing the overall performance of the system. Optimizing an adder may lead to overall system optimization. A desirable adder meets all the criteria, such as high speed, low-power dissipation, low leakage power, and small footprint. However, because there is a trade-off between the area, power and, speed.Obtaining the finest adder in terms of speed, power dissipation, leakage power, and area consumed would assist the designer in selecting an adder for the given application. Transmission function adder (TFA), 17-transistor adder (17-TA), 14-transistor adder (14-TA), ripple carry adder (RCA), carry lookahead adder (CLA), and carry-select adder are among the new 2-bit adders suggested and compared (CSL). This research presents a comparative analysis and performance evaluation of adders based on latency, power dissipation, PDP, leakage power, area, and EDP. Simulations are being done using HSPICE software at 28-nm technology with a supply voltage range of 0.7–1.1 V. The suggested adder has a minimum delay and is 8.6% faster than CLA, according to simulation results. When compared to the other adders, it uses the minimum area and has the lowest leakage power. The proposed adder has minimum power delay product.

A novel pipelined carry adder design based on half adder

<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and simulated on the Cyclone IV FPGA kit platform. Results show that the circuit needs a 7.69 ƞ Sec delay time to provide the output values. The suggested PCA circuit is more attractive than the conventional ripple carry adder for future electronic applications. </span>

Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration

In this paper, a self-checking and -repairing carry-lookahead adder (CLA) is proposed with distributed fault detection ability. The presented design with self-checking and fault localization ability requires an area overhead of 69.6% as compared to the conventional CLA. It can handle multiple faults simultaneously without affecting the delay of conventional CLA, with the condition that each module has a single fault at a time. The repairing operation utilizes the hot-standby approach with partial reconfiguration in which the faulty module would be replaced by an accurately functioning module at run-time. The proposed self-repairing adder with high fault coverage requires 161.5% area overhead as compared to conventional CLA design which is 35.3% less as compared to the state-of-the-art partial self-repairing CLA. Moreover, the delay of the proposed 64-bit self-repairing CLA is 40.7% more efficient as compared to conventional ripple carry adder.

Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications

Low Power circuits play a significant role in designing large-scale devices with high energy and power consumption. Adiabatic circuits are one such energy-saving circuits that utilize reversible power. Several methodologies used previously infer the use of CMOS circuits for reducing power dissipation in logic circuits. However, CMOS devices hardly manage in maintaining their performance when it comes to fast switching networks. Adiabatic technology is employed to overcome these difficulties, which can further scale down the dissipation of power by charging and discharging. An Efficient Charge Recovery Logic (ECRL) based adiabatic technology is used here to evaluate arithmetic operations in circuits like inverter, full adder, Carry Look-Ahead adder etc. A better chance at reducing delay in digital circuits is illustrated by developing a Kogge-stone Adder, built using the ECRL technology. The developed circuitry is further integrated into a Fast Fourier Transform (FFT), which demonstrates the circuit’s enhancement into DSP applications. Not only does this design reduce delay in VLSI switching circuits, but also narrows the power dissipation down to a minimum. This technique proved superior to the existing PFAL technique by demonstrating almost 10% less power dissipation with minimal propagation delay. All the circuits have been simulated at 45 nm technology using the Tanner EDA tool.

Efficient Construction of a Control Modular Adder on a Carry-Lookahead Adder Using Relative-Phase Toffoli Gates

Control modular addition is a core arithmetic function, and we must consider the computational cost for actual quantum computers to realize efficient implementation. To achieve a low computational cost in a control modular adder, we focus on minimizing KQ, defined by the product of the number of qubits and the depth of the circuit. In this paper, we construct an efficient control modular adder with small KQ by using relative-phase Toffoli gates in two major types of quantum computers: Fault-Tolerant Quantum Computers (FTQ) on the Logical layer and Noisy Intermediate-Scale Quantum Computers (NISQ). We give a more efficient construction compared to Van Meter and Itoh's, based on a carry-lookahead adder. In FTQ, $T$ gates incur heavy cost due to distillation, which fabricates ancilla for running $T$ gates with high accuracy but consumes a lot of specially prepared ancilla qubits and a lot of time. Thus, we must reduce the number of $T$ gates. We propose a new control modular adder that uses only 20% of the number of $T$ gates of the original. Moreover, when we take distillation into consideration, we find that we minimize $\text{KQ}_{T}$ (the product of the number of qubits and $T$-depth) by running $\Theta\left(n / \sqrt{\log n} \right)$ $T$ gates simultaneously. In NISQ, CNOT gates are the major error source. We propose a new control modular adder that uses only 35% of the number of CNOT gates of the original. Moreover, we show that the $\text{KQ}_{\text{CX}}$ (the product of the number of qubits and CNOT-depth) of our circuit is 38% of the original. Thus, we realize an efficient control modular adder, improving prospects for the efficient execution of arithmetic in quantum computers.

Low power and area efficient design of fir filter using enhanced clock gating technique

The main aim of this approach is to improve the design model of filters for optimal circuit design. The objective of this proposed method is to improve the performance of VLSI circuit like area, power, and delay. In recent days, the filters are most applicable designs in DSP, medical diagnosis and arithmetic computations. In Digital Signal Processing and communication applications, the FIR filter plays an important role. The Finite Impulse Response is designed with number of adders, multipliers, subtraction units, transfer functions and delay elements. The VLSI circuits are applied in various applications, but the number adders and multipliers occupy the design space since it increases the area and delay factors. The main aim is to reduce the number of adders and multiplier by various computational algorithms. The existing research work uses carry save accumulator with ripple carry adder and binary multiplier. In proposed method, the enhanced Vedic multiplication logic and improved carry lookahead adder logic improves the result. In Vedic multiplication algorithm, the number of adder logic is minimized by adding speculative Brent-kung adder logic in it. The fastest adder in VLSI circuit is CLA (Carry look ahead adder logic), which is improved by utilizing the result of reduced power consumption and delay. In this proposed research work, the power optimization is done by using enhanced clock gating technique. Here, area, power, and delay factors are measured and it is compared with conventional FIR filter design. The proposed method improves the result in the way of area, power, and delay. The whole FIR filter structure is designed and power optimized by connecting with an enhanced clock gating technique. This proposed design and simulate by using Xilinx ISE 14.5 and it is synthesize by ModelSim.

Recurrent neural network from adder’s perspective: Carry-lookahead RNN

The recurrent network architecture is a widely used model in sequence modeling, but its serial dependency hinders the computation parallelization, which makes the operation inefficient. The same problem was encountered in serial adder at the early stage of digital electronics. In this paper, we discuss the similarities between recurrent neural network (RNN) and serial adder. Inspired by carry-lookahead adder, we introduce carry-lookahead module to RNN, which makes it possible for RNN to run in parallel. Then, we design the method of parallel RNN computation, and finally Carry-lookahead RNN (CL-RNN) is proposed. CL-RNN takes advantages in parallelism and flexible receptive field. Through a comprehensive set of tests, we verify that CL-RNN can perform better than existing typical RNNs in sequence modeling tasks which are specially designed for RNNs. Code and models are available at: https://github.com/WinnieJiangHW/Carry-lookahead_RNN.

LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION

Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

Performance of Adder Architectures on Encrypted Integers

The fully Homomorphic encryption scheme is corner stone of privacy in an increasingly connected world. It allows to perform all kinds of computations on encrypted data. Although, time of computations is bottleneck of numerous applications of real life. In this paper, a brief description is made on the homomorphic encryption scheme TFHE of Illaria Chillota and the others. TFHE, implemented in c language in a library, improves the bootstrapping execution time of the FHEW scheme to 13 milliseconds. TFHE performs homomorphic processing on a multitude of logic gates. This variety made it possible to construct, implement five adder architectures and compare them in terms of the execution time of the bootstrapping per logic gate. In a singleprocessor computing environment, the Carry Look-ahead Adder completed a two-integer addition in 90 seconds, whereas the Ripple carry Adder did the same processing in 109 seconds. An improvement in processing time of 15% is observed. And, the same ratio of about 15% was obtained on four integers, respectively for 279 seconds for the first adder and 320 seconds for Wallace's dedicated adder. While in the dual-processor environment, a 50% improvement was seen on all adders in the same processing on integers. The Carry Look-ahead Adder saw his handling improved by the sum of two numbers from 90 seconds to 46 seconds and four numbers from 279 seconds to 139 seconds, respectively.

A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization

Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design.

A REVIEW OF LOW VOLTAGE AND LOW POWER CMOS ADDERS USING VLSI DESIGN IN VERILOG/VHDL

The dominant portion of power dissipation in CMOS adder circuits, due to logic transitions, varies as the square of the supply, significant savings in power dissipation may be exacted by operating with reduced supply voltage. If the supply voltage is reduced while threshold voltage stays same, the noise margins will reduce. Addition is a crucial process because it usually involve carry ripple steps which must propagate a carry signal from each bit to it’s higher bit position. This results in a substantial circuit delay. The adder which lies in the crucial delay path will effectively determine the system overall speed. To improve noise margins, the threshold voltages must also be made smaller. However subthreshold leakage current increases exponentially when threshold voltage is reduced. The higher static dissipation may then offset the reduction in transitions portion of the dissipation. Hence the devices needed to have threshold voltages that maximizes the net reduction in the dissipation. Addition is an obligatory operation that is crucial to processing the fundamental arithmetic operations. Due to the potential versatility of adders in this contemporary research field, the existing adders and adder designs currently intended for future low voltage and low power environments. This can be achieved by the CMOS adders namely Parallel Adder, Ripple Carry Adder(RCA), Carry Look Ahead Adder(CLA), Carry Select Adder(CSL), Carry Save Adder(CSA), Carry Skip Adder(CSK), Conditional Sum Adder(COS).