Inversion Layer Carrier Research Articles

Carrier Mobility Enhancement in Ultrathin-Body InGaAs-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Based on Dual-Gate Modulation

As a promising candidate for More Moore technology, InGaAs-based n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) have attracted growing research interest, especially with InGaAs-on-insulator (InGaAs-OI) configurations aimed at alleviating the short channel effects. Correspondingly, the fabrication of an ultrathin InGaAs body becomes necessary for the full depletion of the channel, while the deteriorated semiconductor–insulator interface-related scattering could severely limit carrier mobility. This work focuses on the exploration of carrier mobility enhancement strategies for 8 nm body-based InGaAs-OI nMOSFETs. With the introduction of a bottom gate bias on the substrate side, the conduction band structure in the channel was modified, relocating the carrier wave function from the InGaAs/Al2O3 interface into the body. Resultantly, the channel mobility with an inversion layer carrier concentration of 1 × 1013 cm−2 was increased by 62%, which benefits InGaAs-OI device application in monolithic 3D integration. The influence of the dual-gate bias from front gate and bottom gate on gate stability was also investigated, where it has been unveiled that the introduction of the positive bottom gate bias is also beneficial for gate stability with an alleviated orthogonal electric field.

Surface inversion layer effective minority carrier mobility as one of the measures of surface quality of the p-aSi:H/i-aSi:H/cSi heterojunction solar cell

The lateral transport of minority carriers in the surface inversion layer of a crystalline silicon (cSi) surface for a p-aSi:H/i-aSi:H/cSi heterojunction (SHJ) solar cell was experimentally analyzed to study defects/traps at the aSi:H/cSi interface and/or on the cSi surface. To extract the lateral surface inversion layer current, a field-effect transistor type test element group device was designed and fabricated on a cSi wafer where SHJ cells were co-integrated. By analyzing the lateral surface inversion layer current, the effective surface minority carrier mobility was calculated. The extracted mobility was one order of magnitude smaller than that of a reference MoOx/i-aSi:H/cSi structure but it increased by low-temperature post-deposition annealing with respect to the reference. This method is highly sensitive to the quality of the aSi:H/cSi interface and/or the cSi surface. The density of trap sites was estimated to be of the order of 1011 cm−2 at the aSi:H/cSi interface and/or on the cSi surface.

Impact of Interface Trap Density of SiC-MOSFET in High-Temperature Environment

We report the physical and electrical characterization of the inversion layer carrier and the shallow interface trap sites with n-and p-channel SiC-MOSFET in terms of high temperature electronics. This work proposes a physical model that explains the difference between Id-Vg measurement result and calculation result supposing the ideal condition with Pao and Sah double ideal in room temperature. The measurement at 500°C confirmed our model so that inversion carrier were thermally excided, they could not be easily trapped by shallow trap sites, and Id-Vg measurement result approached the ideal condition.

Stoner magnetism in an inversion layer

Motivated by recent experimental work on magnetic properties of Si-MOSFETs, we report a calculation of magnetisation and susceptibility of electrons in an inversion layer, taking into account the co-ordinate dependence of electron wave function in the direction perpendicular to the plane. It is assumed that the inversion-layer carriers interact via a contact repulsive potential, which is treated at a mean-field level, resulting in a self-consistent change of profile of the wave functions. We find that the results differ significantly from those obtained in the pure 2DEG case (where no provision is made for a quantum motion in the transverse direction). Specifically, the critical value of interaction needed to attain the ferromagnetic (Stoner) instability is decreased and the Stoner criterion is therefore relaxed. This leads to an increased susceptibility and ultimately to a ferromagnetic transition deep in the high-density metallic regime. In the opposite limit of low carrier densities, a phenomenological treatment of the in-plane correlation effects suggests a ferromagnetic instability above the metal–insulator transition. Results are discussed in the context of the available experimental data.

Temperature Dependence of Inversion Layer Carrier Concentration and Hall Mobility in 4H-SiC MOSFETs

Hall measurements on NO annealed 4H-SiC MOS gated Hall bars are reported in the temperature range 77 K- 423 K. The results indicate higher carrier concentration and lower trapping at increased temperatures, with a clear strong inversion regime at all temperatures. In stark contrast to Si, the Hall mobility increases with temperature for 77 K-373K, above which the mobility decreases slightly. The maximum experimental mobility was found to be ~50 cm2 V-1 s-1 which is only about 10% of the 4H-SiC bulk mobility indicating that while NO annealing drastically improves trapping, it does not improve the mobility significantly. Supporting modeling results strongly suggest the presence of a disordered SiC channel region.

Improvement in off-State Leakage Current of n-Channel SOS MOSFETs by Hydrogen Annealing of the SOS Film

The off-state source-to-drain leakage current and punchthrough voltage are the quantities that frequently limit the performance of short-channel floating-body silicon-on-sapphire (SOS) n-channel MOSFETs. In this paper, we demonstrate that the high-temperature hydrogen annealing of the SOS film prior to the device fabrication leads to marked improvement in these two parameters. The effect is attributed to the impact of hydrogen on the out-diffused thin alumina layer formed at the silicon-sapphire interface during the anneal. The thin alumina layer acting as a p-type dopant source at the back interface eliminates the back surface depletion of SOS n-MOSFETs. It also acts as a recombination center to eliminate the floating-body effect of floating-body n-MOSFETs. This technique provides a practical and reliable process to build short-channel floating-body SOS n-MOSFETs with off-state leakage as low as the junction leakage and punchthrough voltage as high as 6 V or higher at the gate length of 0.5 μm without any degradation on the inversion layer carrier mobility or increase in the junction leakage current.

Gate Capacitance Reduction Due to the Inversion Layer in High- $k$/Metal Gate Stacks Within a Subnanometer EOT Regime

We investigate the determining mechanisms of the inversion-layer capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> in the high-k/metal gate stacks, focusing on the two perturbative effects related with the dielectric properties. Those effects are the penetration of inversion-layer carriers into the dielectrics with a finite potential barrier and the image potential acting on the carriers adjacent to the dielectrics with permittivity different from that of the silicon substrate. The experimental and the theoretical analyses of the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> dependency on the crystal orientation of silicon substrates enable us to separate the two effects and to prove that the observed C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> modulation in the high- k/metal gate stacks is attributable not to the image potential effect, but to the penetration effect. Moreover, we investigate the reduction of the total gate capacitance due to the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> in the advanced gate stacks scaled down to 0.66-nm equivalent oxide thickness. The influence of the elementary composition, the physical thickness, and the interface layer on a scaling loss due to the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> is experimentally evaluated.

Inversion layer carrier concentration and mobility in 4H–SiC metal-oxide-semiconductor field-effect transistors

Free electron concentration and carrier mobility measurements on 4H–SiC metal-oxide-semiconductor inversion layers are reported in this article. The key finding is that in state-of-the-art nitrided gate oxides, loss of carriers by trapping no longer plays a significant role in the current degradation under heavy inversion conditions. Rather, it is the low carrier mobility (maximum∼60 cm2 V−1 s−1) that limits the channel current. The measured free carrier concentration is modeled using the charge-sheet model and the mobility is modeled by existing mobility models. Possible mobility mechanisms have been discussed based on the modeling results.

Carriers from impurities in semiconductors and carriers in inversion-layer of MOS structures

Carriers from impurities in semiconductors and carriers in inversion-layer of MOS structures

Attofarad resolution capacitance–voltage measurement of nanometer scale field effecttransistors utilizing ambient noise

A high resolution capacitance–voltage (C–V) characterization technique, enabling direct measurement of electronic properties at thenanoscale in devices such as nanowire field effect transistors (FETs) through the use ofrandom fluctuations, is described. The minimum noise level required for achieving sub-aF (10−18 F) resolution, the leveraging of stochastic resonance, and the effect ofhigher levels of noise are illustrated through simulations. The non-linearΔCgate−source/drain–Vgate response of FETs is utilized to determine the inversion layer capacitance (Cinv) and carrier mobility. The technique is demonstrated by extracting the carrierconcentration and effective electron mobility in a nanoscale Si FET withCinv = 60 aF.

A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO2/HfO2 dielectrics (effective oxide thickness is less than 1nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.

First-principles study on inversion layer properties of double-gate atomically thin silicon channels

The inversion layer properties of double-gate atomically thin silicon channels are studied based on the first-principles enforced Fermi energy difference method. The calculated results indicate that the atomic-scale thickness of the channel significantly affects the inversion layer capacitance as well as the inversion layer carrier properties. They also indicate that the first-principles approach is essential and practical for studying the device physics of the field effect transistors with nanometer-scale channels.

Simultaneous and Independent Measurement of Stress and Temperature Using a Single Field-Effect Transistor Structure

This paper reports on the simultaneous and independent measurement of mechanical stress and temperature using p- and n-channel field-effect transistor structures with multiple drain/source contacts fabricated in a commercial complementary metal-oxide-semiconductor technology. The respective average stress sensitivities of of three p-channel devices and 66 of two n-channel devices at room temperature originate from the shear piezoresistance effect, also termed pseudo-Hall effect, of the inversion layer carriers. The stress sensitivities show very small average temperature coefficients (TCs) of 1127 and 431 ppm/K for the p- and n-channel devices, respectively. Temperature values were obtained from the temperature-dependent threshold voltage . Robust values were extracted from the second-order transconductance smoothed using a new variant of Tikhonov's regularization method. With both types of devices, the obtained by this procedure was found to be stress insensitive in the range of stresses from 0 to 20.4 MPa. Between 25 and 150 , depends linearly on temperature, with average slopes of 1.67 and for p- and n-channel devices, respectively. Device-to-device variations of the temperature sensitivity and its slope suggest the use of a two-point calibration. With only a one-point calibration, a temperature uncertainty of less than 3 over a temperature range of 100 is achieved.

Empirical Quantitative Modeling of Threshold Voltage of Sub-50-nm Double-Gate Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor

We simulated the threhold voltage characteristics of an ultrathin double-gate (DG) silicon-on-insulator metal–oxide–semiconductor field-effect transistor (SOI MOSFET) using the hydrodynamic transport model. It has been shown that threshold voltage increases as SOI layer thickness is reduced in many cases, which is not due to a distinct quantum effect. This stems from an increase in surface potential at the threshold; this increase in surface potential is a physically inevitable result because a reduction in SOI layer thickness decreases inversion layer carrier density per unit area. We proposed models of threshold voltage and surface potential at the threshold, and their availabilities were confirmed by comparing what with the detailed simulation results. We also addressed the short-channel effect on surface potential and proposed a model of drain-induced barrier lowering.

Tunneling 1/ fγ noise in 5 nm HfO 2/2.1 nm SiO 2 gate stack n-MOSFETs

Evidence is provided for excess tunneling 1/ f γ noise into trap states in a 5 nm HfO 2 layer deposited on 2.1 nm thermal SiO 2. As such, it is a nice illustration of the McWhorter type of flicker noise. The interaction of the HfO 2 traps with inversion layer carriers gives rise to an excess 1/ f γ component below 100 Hz typically, corresponding to a γ > 1. In contrast, the background 1 / f γ ′ noise of the SiO 2 layer is characterized by a γ′ < 1 and dominates the high-frequency part of the spectra. The excess fluctuations cause several peaks in the noise spectral density as a function of the gate bias or drain current. The fact that more than one “resonance” peak is found suggests tunneling to or from different discrete defect states or bands of energy levels.

Impact of the high vertical electric field on low-frequency noise in thin-gate oxide MOSFETs

In this paper, quantum effects induced by the high vertical electric field, i.e., inversion layer quantization and gate current tunneling, are taken into account to model the low-frequency noise behavior of 0.13 /spl mu/m technology node thin gate oxide MOSFETs. First, we show that the modifications induced by inversion layer quantization in the band structure and spatial distribution of the inversion layer carriers must be taken into account when extracting an effective density of traps from 1/f noise measurements. The ultrathin gate oxide and the high substrate doping of scaled MOSFETs create a strong electrical field in the inversion layer, which causes the surface conduction (n-) or valence (p-MOSFET) band to split into discrete energy levels. The first allowed state resides then above (below) the conduction (valence) band level in the bulk, giving rise to a band gap widening and in addition the spatially localized charge centroid is at a finite distance from the SiO/sub 2//Si interface. The impact on both dc and noise parameters of these quantum effects have been numerically calculated and compared to experimental results. The main conclusions coming out of this study is that if the inversion layer quantization is neglected, inaccurate oxide trap densities will be derived from the input-referred voltage noise spectral density S/sub VC/:. A similar conclusion will hold for the extraction of the scattering coefficient derived in the frame of a correlated number fluctuations model or for the effective Hooge parameter, derived from the normalized drain current spectral density S/sub ID//I/sub D//sup 2/. Finally, a particular gate tunneling mechanism namely Electron Valence Band (EVB) tunneling is shown to modify the noise behavior of thin gate oxide devices in terms of a self-biasing body effect.

Study of the effect of interface state charges on field-effect mobility of n-channel 6H-SiC MOSFET

The effect of interface state charges on the field-effect mobility of n-channel 6H-SiC MOSFET is analyzed based on the nonuniform distribution of interface state density in the energy gap. The results of the analysis show that interface state charges have the influence of lowering the field-effect mobility in n-channel SiC MOSFET. A relationship has been established between the ratio of the experimentally determined field-effect mobility to the inversion-layer carrier mobility and interface states.

Modeling inversion-layer carrier mobilities in all regions of MOSFET operation

Channel electron and hole mobilities in MOSFETs have been extracted in terms of the effective vertical field for several substrate biases. After ascertaining that the 2-D drift–diffusion numerical device simulator is reproducing the substrate charge variation in the MOSFET with respect to the gate voltage, obtained from C– V data, the mobility versus effective field behavior is extracted by comparing the simulated and measured I d– V gs characteristics. A simple model has been constructed to fit the extracted mobility data in weak and strong inversion, for inversion-layer electrons and holes in n-MOSFET and p-MOSFET, respectively.

Development of high dielectric constant epitaxial oxides on silicon by molecular beam epitaxy

Thin films of perovskite-type oxide SrTiO 3 have been grown epitaxially on Si(001) substrates using molecular beam epitaxy. Using reflection high energy electron diffraction (RHEED) we have determined the optimum growth conditions for these type of oxides directly on silicon. Also, observations of RHEED during growth and X-ray diffraction (XRD) analysis indicate that high quality heteroepitaxy on Si takes place with SrTiO 3(001)//Si(001) and SrTiO 3[010]//Si[110]. Thin SrTiO 3 layers grown directly on Si were used as the gate dielectric for the fabrication of MOSFET devices. An effective oxide thickness <10 Å has been obtained for a 110 Å thick SrTiO 3 dielectric film with interface state density around 6.4×10 10 cm −2 eV −1, and the inversion layer carrier mobilities of 220 and 62 cm 2 V −1 s −1 for NMOS and PMOS devices, respectively.

Epitaxial oxides on silicon grown by molecular beam epitaxy

Using molecular beam epitaxy, thin films of perovskite-type oxide Sr x Ba 1− x TiO 3 (0⩽ x⩽1) have been grown epitaxially on Si(0 0 1) substrates. Growth parameters were determined using reflection high energy electron diffraction (RHEED). Observation of RHEED during growth and X-ray diffraction analysis indicates that high quality heteroepitaxy on Si takes place with Sr x Ba 1− x TiO 3(0 0 1)//Si(0 0 1) and Sr x Ba 1− x TiO 3[0 1 0]//Si[1 1 0]. Extensive atomic simulations have also been carried out to understand the interface structure and give some insights into the initial growth mechanism of the oxide layers on silicon. SrTiO 3 layers grown directly on Si were used as the gate dielectric for the fabrication of MOSFET devices. An effective oxide thickness <10 Å has been obtained for a 110 Å thick SrTiO 3 dielectric film with interface state density around 6.4×10 10/cm 2/eV, and the inversion layer carrier mobilities of 220 and 62 cm 2/V/s for NMOS and PMOS devices, respectively.