The lateral transport of minority carriers in the surface inversion layer of a crystalline silicon (cSi) surface for a p-aSi:H/i-aSi:H/cSi heterojunction (SHJ) solar cell was experimentally analyzed to study defects/traps at the aSi:H/cSi interface and/or on the cSi surface. To extract the lateral surface inversion layer current, a field-effect transistor type test element group device was designed and fabricated on a cSi wafer where SHJ cells were co-integrated. By analyzing the lateral surface inversion layer current, the effective surface minority carrier mobility was calculated. The extracted mobility was one order of magnitude smaller than that of a reference MoOx/i-aSi:H/cSi structure but it increased by low-temperature post-deposition annealing with respect to the reference. This method is highly sensitive to the quality of the aSi:H/cSi interface and/or the cSi surface. The density of trap sites was estimated to be of the order of 1011 cm−2 at the aSi:H/cSi interface and/or on the cSi surface.