The surface passivation of a CMOS image sensor (CIS) is highly beneficial for the overall improvement of a device performance. We employed the thermal atomic layer deposition (T-ALD) and plasma enhanced (PE-ALD) techniques for the deposition of 20 nm HfO<sub>2</sub> as well as stacked with 3 and 5 nm Al<sub>2</sub>O<sub>3</sub> thin films. The HfO<sub>2</sub>/Si and Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>/Si metal-oxide-semiconductor structures were used to analyze the fixed charge density (Q<sub>f</sub>) and interface trap density (D<sub>it</sub>). The as-synthesized samples show high D<sub>it</sub> and Q<sub>f</sub> values (10<sup>12</sup> cm<sup>-2</sup>eV<sup>-1</sup>) and a minority carrier lifetime of 15-300 μs. The finite-difference time-domain simulation of high-k dielectrics confirmed that the Al<sub>2</sub>O<sub>3</sub> (top)/HfO<sub>2</sub> stacked structures expected higher quantum efficiency for CIS application. The effect of vacuum annealing (VA) and forming gas annealing (FGA) treatments succeeded with the decomposition of the D<sub>it</sub> and increase in carrier lifetime. The H<sub>2</sub> ambient FGA samples showed a remarkable decrease in the D<sub>it</sub> values. To improve the overall performance of the device after passivation, we employed an Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub> bilayer structure, which showed a low D<sub>it</sub> of 10<sup>11</sup> cm<sup>-2</sup>eV<sup>-1</sup> and a minority carrier lifetime of ~3,700 μs after 400 °C and 30 min FGA. We believe that this surface passivation strategy will pave way for future CIS technology regarding the development of lower defective surface and superior performance.