Serious reliability concerns of Static Random Access Memories (SRAMs) in nanometer technologies are the increased process variations as well as the various aging mechanisms. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena are the main factors related to the aging reliability reduction. This degradation affects speed, operating voltages, memory cell noise margins and sense amplifier input offset voltage. Thus, it is imperative to develop design techniques for aging tolerance that will provide the ability to sense aging levels, predict upcoming failures in the memory and early react to retain the reliable operation. In this work, a circuit for the periodic aging monitoring in SRAM sense amplifiers and memory cells is presented.