Carrier Based PWM Technique Research Articles

FPGA implementation of carrier-based PWM techniques for single-phase matrix converters

Field programmable gate arrays (FPGAs) stand out as a highly efficient and reliable digital solution to control power electronics converters. Direct single-to-single-phase matrix converters (SSMCs) are widely used in industrial and power system-related applications and are usually controlled using carrier-based PWM techniques. Existing literature studies on FPGA implementation of carrier-based PWM techniques for SSMC lack providing architectural design details and programming algorithms. Further, resource utilization/power consumption optimizations and analyses are not performed. To fill these research gaps, we propose a new FPGA-based design that is capable of employing the desired carrier-based PWM technique and synthesizing any output frequency. It also optimizes the FPGA resource utilization and power consumption and utilizes a novel approach to synchronize the generated triggering pulses with the source. A laboratory setup is built to experimentally test the proposed FPGA-based design, where results demonstrate the efficiency and reliability of the design.

Segment Reduction-Based Space Vector Pulse Width Modulation for a Three-Phase F-Type Multilevel Inverter with Reduced Harmonics and Switching States

An improved segment reduction-based space vector pulse width modulation (SVPWM) for an F-type three-level inverter (FT2LI) is presented in this article. The proposed SVPWM algorithm decreases the additional switching state transition of each triangle with the application of an improved nine- and three-segment reduction switching strategy. The main feature of the segment reduction technique is that it eliminates second-order harmonics in the inverter output side with good total harmonic distortion (THD), low switching losses, and minimum filter requirements when compared with carrier-based PWM (CBPWM) techniques such as multi-carrier sine PWM (MC-SPWM), sixty-degree PWM (60° PWM), and switching frequency optimal PWM (SFO PWM). The proposed modulation algorithm for FT2LI is implemented on the MATLAB/Simulink platform. The performance of the proposed segment reduction-based SVPWM algorithm is tested experimentally on an FT2LI at various amplitude and frequency modulation indices, and the experimental results are verified with the simulation results. Additionally, a comparative analysis carried out to study the relationship between the segment reduction-based SVPWM and CBPWM techniques inferred that the suggested segment reduction-based SVPWM algorithms can optimize high-order harmonic distributions and have a minimum computational burden.

Implementation of a modified carrier-based PWM technique for a cascaded MLI using DSP microcontroller

<p><span lang="EN-US">A multi-level converter is a power electronic device desired to generate a desired AC voltage level using several introduced DC voltages, the output voltage of the converter is characterized by a low harmonic content (THD) compared to conventional inverters. The adopted innovative design permits the independent control of PV modules, enabling, in this way, to operate independently and won’t be very affected by intermittence. Additionally in this paper, a new control strategy based on sinusoidal pulse width modulation (SPWM) technique is analyzed for cascaded H-Bridge inverter. In this new technique, separate modified carriers are used for each H-Bridge (HB). Multiple-carrier SPWM is used with the new control SPWM technique. Those carriers are being implemented with diverse sinusoidal dispositions phase disposition (PD), phase opposition and disposition (POD), alternative opposition and disposition (APOD), and with altered frequencies. Experimental results are obtained while using different operating conditions.</span></p>

Carrier-Based Variable Frequency PWM Technique for PMSM Drives to Achieve Dispersed Spectrum and Extended Low-Speed Operation Capability

Carrier-Based Variable Frequency PWM Technique for PMSM Drives to Achieve Dispersed Spectrum and Extended Low-Speed Operation Capability

A performance assessment of nine-stage ternary DC source mli through various PWM topologies

ABSTRACT In modern days, MLIs comprise a lot of concentrations in academia and industry. As they are altering interest in a feasible technology in supporting frequent applications of renewable energy conversion systems and drives, these huge power and medium/higher voltage applications and MLIs are extensively used as one of the sophisticated powers converter topography. The MLIs are divided into two types such as asymmetric and symmetric. MLIs of the asymmetric kind have more amount of output AC voltage stage with fewer DC input source voltage and switching components. In this research paper, asymmetric single-phase cascade full-bridge MLI is developed with carrier-based unipolar PWM techniques. This MLI can generate nine-stage of output AC voltage through eight switches and two input DC sources. It is tested through a variety of multicarrier unipolar PWM control combinations. The Phase Disposition (PD), Alternating Phase Opposition Disposition (APOD), Carrier Overlapping (COP) and Variable Frequency (VF) are all PWM control which included in support of preference of single-phase nine-stage ternary cascade multilevel inverters. With various modulation indices (ma), the harmonic substance of output AC voltage for each approach is observed and tabulated. The proposed design for generating nine-stage output AC voltage is demonstrated using MATLAB-SIMULINK and confirmed using a laboratory-based prototype model. The results show that the unipolar Alternating Phase Opposition Disposition PWM technique that provides a high-quality output voltage with less harmonic distortion. Besides, the performance of Carrier Overlapping PWM techniques is greater since it produces a superior fundamental RMS output AC voltage.

DSP-FPGA based real time implementation of carrier based PWM technique for an indirect matrix converter

ABSTRACT The main focus of the presented work is to provide an easy, efficient and rapid method of implementing the carrier-based PWM (CPWM) technique for the three-to-three phase indirect matrix converter (IMC). The control platforms DSP (TMS320F28335) and the FPGA (Spartan-6) are used for realising the CPWM scheme for the IMC. In the presented work, the auto code generation facility provided by the simcoder module of the PSIM software is utilised to develop the C-code for the TI F28335 hardware target. The FPGA is used to perform the logical operations on the switching pulses produced by the DSP. The complete procedure of implementing the CPWM scheme in DSP using simcoder module of PSIM and FPGA is demonstrated in this work. The simulation and the experimental results are included to verify the effective implementation of the CPWM scheme for the IMC.

Study of power generation control strategy for five-phase open-winding PMSG based on dual-space closed-loop vector control using carrier-based PWM technique

Study of power generation control strategy for five-phase open-winding PMSG based on dual-space closed-loop vector control using carrier-based PWM technique

Design and Simulation of Modular Multilevel Inverter Using PWM

Modular Inverter is a kind of new multilevel inverter topology used in HVDC system and medium voltage applications like induction motor drive. Modular Multilevel inverter can operate at high voltages and current with fewer harmonic and simple filters, and without increasing the number of switches. This paper mainly focuses on simple topology for modular multilevel inverter in order to reduce the drawbacks of conventional M- level inverters such as capacitor voltage balancing during medium voltage applications. This paper addresses the basic modes of working, carrier-based sine PWM technique and voltage balancing at each capacitor for a three-level inverter are discussed. The simulation and design was carried out using MATLAB/SIMULINK software.

Implementation of a drive system for dual single-phase induction motor using a five-leg inverter with carrier-based space vector PWM technique

Implementation of a drive system for dual single-phase induction motor using a five-leg inverter with carrier-based space vector PWM technique

Performance Evaluation of Cascaded and Reduced Switch Multilevel Inverter Using Modified Carrier Based PWM Technique

This paper proposes an improved harmonic distorted modified triangular carrier-based multicarrier pulse width modulation for generating the switching pulses of a multilevel inverter. This modified triangular wave consists of a triangular wave bearing a close resemblance to an ‘M’ shaped wave. The design of this carrier signal has been optimized to maintain a low level of total harmonic distortion (THD), while increasing the fundamental o/p voltage to ensure the effective DC voltage utilization. Moreover, this optimization reduces the switching losses and improve the efficiency of the power inverter. With the help of this carrier signal, High-frequency alternative phase opposition disposition pulse width modulation (APODPWM) is generated. This new control scheme has been applied to seven levels of conventional cascaded H-bridge with reduced switch multilevel inverter. The output is compared with conventional carrier-based APODPWM. The comparison is made in terms of THD, fundamental output voltages and inverter losses. To ensure quality performance, conventional carrier and modified carrier-based multicarrier PWM topologies are used for the Cascaded seven-level inverter with reduced switch seven-level inverter having a carrier frequency of 2 kHz and modulation index of 0.8-1.30. According to the simulation results, by using the proposed modulation scheme the THD and the switching loss were reduced by 9.64[%] and 4.2[%] respectively. Besides, the proposed modulation technique increases the fundamental output voltages. The total simulation process is done in MATLAB Simulink environment.
 GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 6(1), Dec 2019 P 12-19

A modified carrier-based PWM technique for minimization of leakage current in transformer less single-phase grid-tied PV system

This paper discusses the impact of leakage current and its dependency on common mode voltage in transformer less single-phase grid connected photovoltaic (PV) system. Further a new carrier-based PWM method is derived for H bridge single-phase grid-tied PV inverter to minimize leakage current. The proposed modulation strategy is compared with conventional techniques through simulation in MATLAB R2018a. The superiority of the proposed technique is validated in laboratory prototype of a 500 W single-phase grid-tied PV system. The hardware results validate the theoretical findings in appropriate.

Optimum pulse-width modulation strategy for a symmetric cascaded multilevel inverter

This paper investigates for the most suitable PWM strategy for a symmetric cascaded multilevel inverter. The objective is to determine a PWM switching strategy which optimises inverter performance by ensuring higher DC link utilisation and minimum total harmonic distortion (THD) at low switching frequency to minimise switching power losses. Simulations carried out in MATLAB-Simulink environment has given an insight of inverter performance when carrier-based PWM techniques are applied. In this parametric evaluation, both odd and even multiples of 50 Hz modulating signal were applied for obtaining switching frequency for various multicarrier-based PWM strategies.

Optimisation of total harmonic distortion using carrier-based PWM techniques for nested multilevel inverter topologies

This paper presents the design and simulation of multilevel inverter topologies configuring nested arrangement. It has the remarkable feature of reduced number of diodes and concomitantly higher efficiency compared to the neutral-point clamped (NPC) inverter topology. The simulation of nested multilevel topology is fulfilled for four, five, six, seven, eight and nine output voltage levels having connected with a three phase star connected RL load. The performance comparison for different output voltage levels is accomplished in terms of total harmonic distortion (THD). The carrier-based sinusoidal PWM techniques, namely, phase disposition (PD), phase opposition disposition (POD) and alternative phase opposition disposition (APOD) are adopted here in order to reduce harmonic distortion in the output voltage as well as load current. The harmonic analysis is carried out through FFT analysis. The simulation is performed using MATLAB/Simulink software version R2012b.

Optimum pulse-width modulation strategy for a symmetric cascaded multilevel inverter

This paper investigates for the most suitable PWM strategy for a symmetric cascaded multilevel inverter. The objective is to determine a PWM switching strategy which optimises inverter performance by ensuring higher DC link utilisation and minimum total harmonic distortion (THD) at low switching frequency to minimise switching power losses. Simulations carried out in MATLAB-Simulink environment has given an insight of inverter performance when carrier-based PWM techniques are applied. In this parametric evaluation, both odd and even multiples of 50 Hz modulating signal were applied for obtaining switching frequency for various multicarrier-based PWM strategies.

Carrier-Based Digital PWM and Multirate Technique of a Cascaded H-Bridge Converter for Power Electronic Traction Transformers

In the existing technique for power electronic converters with low switching frequency and multiple cells, the sampling frequency is always set at the same value as the control frequency, and the modulating wave in each cell updates itself when its corresponding carrier reaches its peak and valley. In this paper, this implementation scheme is denoted by asymmetrically sampled-pulsewidth modulation (AS-PWM). It is proven that AS-PWM suffers from three defects: further increase of switching frequency is restricted by the available control period and the total cell number; long modulator delay exists and may bring the control system into instability if high crossover frequency is chosen; and spectrum aliasing toward the digital modulating waves may occur and makes the ac input current distorted. Therefore, another implementation scheme of carrier-based digital PWM is recommended in this paper, which is denoted by multisampled PWM (MS-PWM). In MS-PWM, all of the modulating waves update themselves at the same time. The research presented in this paper is based on a power-electronic traction transformer (PETT), which is made up of a cascaded H-bridge converter and several dc/dc converters. For the consideration of scalability, control, and reliability, a star-connected distributed control system is adopted for the PETT equipment. In order to make full use of this distributed hardware, and to improve the control performance with relatively low requirement toward the digital chips, a universal-type multirate structure is proposed in this paper, which is based on the MS-PWM technique. In the proposed structure, the sampling frequency, control frequency, and modulating-wave updating frequency can be separated from the switching frequency, and each of them can be chosen independently according to the practical control demand and the hardware condition. There is no mutual effect between their selections. The influence of the variation of these three frequencies on the control performance is analyzed as well. At last, experimental results based on a five-cell PETT laboratory prototype with a rated power of 30 kW are provided, and all of them verify the effectiveness and correctness of the proposed algorithms.

Novel Carrier based PWM Techniques Reduce Common Mode Voltage for Six Phase Induction Motor Drives

This paper proposes a novel pulse width modulation (CBPWM) technique for reducing the common mode voltage for a six-phase induction motor (SPIM) drive. This proposed CBPWM technique relies on setting up offset functions and the phase shift of carrier wares. Common mode voltage occurs under the effect of DC power Vd always in Vd/6 limits. Some ways of designing the offset function are proposed; these proposed strategies permit to reduce either the mean value or the instantaneous value of the common mode voltage. Features of proposal CBPWM solutions have been compared. Simulation and experimental results demonstrate the feasibility of the proposed solution.

MATLAB/simulink study of multi-level inverter topologies using minimized quantity of switches

Multilevel Inverters (MLI) have very good features when compared to Inverters. But using more switches in the conventional configuration will reduce its application in a wider range. For that reason a modified 7-level MLI Topology is presented. This new topology consists of less number of switches that can be reduced to the maximum extent and a separate gate trigger circuit. This will reduce the switching losses, reduce the size of the multilevel inverter, and cost of installation. This new topology can be used in Electrical drives and renewable energy applications. Performance of the new MLI is tested via. Total harmonic distortion. This construction structure of this multilevel inverter topology can also be increased for 9-level, 11-level and so on and simulated by the use of MATLAB/SIMULINK. A separate Carrier Based PWM Technique is used for the pulse generation in this configuration.

Performance Evaluation of Carrier Based PWM Techniques for Hybrid Multilevel Inverters with Reduced Number of Components

This paper presents an implementation of hybrid multilevel inverter employing fewer components and less carrier signals when compared to conventional multilevel inverters. In the hybrid topology, to increase the performance of multilevel inverter, first positive levels are generated by using switches having high frequency and then reverse the voltage component using low frequency switches. Due to this, the complexity and overall cost for higher output voltage levels are greatly reduced. Simulation of single phase 7-level, 9-level and 11-level hybrid inverter has been performed using sinusoidal pulse width modulation (SPWM) techniques i.e., APOD and CO. Also the two techniques are compared in terms of total harmonic distortion (THD) for various modulation indices and observed to be greatly improved when compared to conventional topologies. The performance of single phase eleven level hybrid inverter is analyzed for induction motor (IM) load. Simulation is performed using MATLAB/ SIMULINK.

A New Improved Variable Frequency Triangular Carrier-PWM with MOPSO Algorithm for Carrier Based PWM Techniques in Inverters

This paper investigates multi-carrier PWM methods in multi-level inverters. Two new MCPWM methods are introduced. This study proposes a new optimized MCPWM method to improve the output voltage characteristics like THD and LOH. The proposed method is based on variable frequency with a specific range. It means each carrier wave has a determined frequency. It is calling Variable Frequency Triangular Carrier-PWM. MOPSO algorithm is used to optimize the answers. This work considers some different levels of inverters like five, seven and nine levels. The results are compared with SPWM method.

An Equivalent Carrier-based Implementation of a Modified 24-Sector SVPWM Strategy for Asymmetrical Dual Stator Induction Machines

A modified space vector pulse width modulation (SVPWM) strategy based on vector space decomposition and its equivalent carrier-based PWM realization are proposed in this paper, which is suitable for six-phase asymmetrical dual stator induction machines (DSIMs). A DSIM is composed of two sets of symmetrical three-phase stator windings spatially shifted by 30 electrical degrees and a squirrel-cage type rotor. The proposed SVPWM technique can reduce torque ripples and suppress the harmonic currents flowing in the stator windings. Above all, the equivalent relationship between the proposed SVPWM technique and the carrier-based PWM technique has been demonstrated, which allows for easy implementation by a digital signal processor (DSP). Simulation and experimental results, carried out separately on a simulation system and a 3.0 kW DSIM prototype test bench, are presented and discussed.