Carbon Nanotube Field-effect Transistors Circuits Research Articles

Nonlinear Characterization and Modeling of Carbon Nanotube Field-Effect Transistors

We report for the first time to our knowledge large-signal measurements performed at 600 MHz and in time domain on carbon nanotube field-effect transistors (CNFETs) using a large-signal network analyzer. To overcome the very high mismatch between the high CNFET impedance and the basic 50-Omega configuration of the setup, the output impedance was matched with the help of an experimental active load-pull configuration. Hence, we were able to observe under large-signal conditions the nonlinear behavior of CNFETs. Static measurements and continuous-wave <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ij</sub> -parameter measurements were made for many different biases. They were used in order to determine a nonlinear electrical model that has been validated thanks to the nonlinear measurements. The developed model opens the way for electrical CNFET circuit simulation and nonlinear applications of these devices.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance.

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

Intrinsic carbon-nanotube field-effect transistors (CNFETs) have been shown to have superior performance over silicon transistors. In this letter, we provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device (gate) width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.