Capacitated Network Research Articles

A highly tunable quadruple quantum dot in a narrow bandgap semiconductor InAs nanowire.

Quantum dots (QDs) made from semiconductors are among the most promising platforms for the development of quantum computing and simulation chips, and they have the advantages of high density integration and compatibility with the standard semiconductor chip fabrication technology compared to other platforms. However, the development of a highly tunable semiconductor multiple QD system still remains a major challenge. Here, we demonstrate the realization of a highly tunable linear quadruple QD (QQD) in a narrow bandgap semiconductor InAs nanowire via a fine finger gate technique. The QQD is studied by electron transport measurements in the linear response regime. Characteristic two-dimensional charge stability diagrams containing four groups of resonant current lines of different slopes are obtained for the QQD. It is shown that these current lines arise from and can be individually assigned to resonant electron transport through the energy levels of different QDs. Benefitting from the excellent gate tunability, we also demonstrate the tuning of the QQD to regimes where the energy levels of two QDs, three QDs and all four QDs are energetically in resonance, respectively, with the Fermi level of the source and drain contacts. A capacitance network model is developed for the linear QQD and the simulated charge stability diagrams based on this model show good agreement with the experiments. Our work provides solid experimental evidence that narrow bandgap semiconductor nanowire multiple QDs could be used as a versatile platform to achieve integrated qubits for quantum computing and to perform quantum simulations of complex many-body systems.

A prototype of SiPM-based scintillator Compton camera with capacitive multiplexing readout

Compton camera is capable of visualizing the distribution of radioactivity based on the Compton scattering kinematics, and can be applied in nuclear accident emergency response, radioactivity decontamination, homeland security and etc. A prototype of Compton camera has been constructed consisting of two 4×4 SiPM-Ce: GAGG scintillator arrays. The signals of a SiPM array were converted into 4 position-weighted outputs with capacitive network circuit and collected by a CAEN digitizer. Two-dimensional flood images and energy responses of two detector modules were obtained. The average energy resolution of single elements of the two detector modules was 6.6% FWHM at 662 keV. Imaging performance of the prototype camera was evaluated with a 137Cs point source and a 22Na point source. Efficiency of the prototype for the 137Cs point source located right in front was measured to be 0.09%. The angular resolution of a 137Cs point source placed right in front of the camera was 7.2° FWHM. Isotopic images of the two gamma-ray sources were obtained with spatial resolutions of 8.2° FWHM for 137Cs and 8.8° FWHM for 22Na.

Determinations of Annual Investments of DisCo and Private Sector in Expansion Planning of Distribution Network

Ever-increasing load-demand, threaten the continuity of power supply and diminishes power quality causing serious technical challenges in distribution networks. In this regards, commonly used cheaper practices like capacitor allocation and network configuration, can enhance operational parameters of the network. On the other hand, supplying the future loaddemand, requires installing new substations or distributed generations (DGs). Because of DGs inherent technical and economic advantages, Distribution Company (DisCo), encourage private investment to install DGs, by signing long-term Power Purchase Agreement (PPA) with DG owners (DGO). In such a situation created, DG allocation and simultaneously capacitor allocation and network configuration can be economical for both DisCo and DGO and also can enhance the reliability and power quality. So, this paper is aimed to find the annual instants for network configuration; timing, sizing and sitting of capacitors and DGs, and PPA rates using Multi-Objective Particle Swarm Optimization (MOPSO). Also, the uncertainties of load-demand and electricity-price, voltage-sensitive loads and load priority in power supply are applied into the planning problem. Voltage deviation and voltage stability are considered as constraints which must be better in optimum solution. The effectiveness of the proposed scheme, is validated by computer simulation done on a 33-Bus IEEE distribution network and the outcomes are discussed.

A High Gain DC-DC Boost Converter with Active Switched LC-Network Employing BLDC Motor Drive for Water Pumping

The classical DC-DC boost converter switches has high power rating, since it is the voltage stress on the active switch that is obtained as the output voltage. As a result the conduction loss is increased and the voltage gain is limited accordingly. Active switched LC based high gain boost converter efficiently increases the voltage gain by combination of active switched inductor (ASL) and active switched capacitor(ASC) network. The voltage stresses on the additionally added diode and capacitor is low. In addition, high current transients which is a problem in switched capacitor circuits is also avoided in this topology. This network is used as first stage to generate required dc bus voltage for a BLDC motor drive fed via a three phase voltage source inverter(VSI). The above mentioned system is simulated in MATLAB Simulink environment and satisfactory results are obtained.

Closed-Form Extraction Strategy of Physically Meaningful Parameters of Small-Signal HEMT Models With Distributed Parasitic Capacitive Effects

In this article, closed-form physically consistent parameter extractions are presented for small-signal models with parasitic distributed capacitive effects. First, the effective gate-source, drain-source, and gate-drain capacitances of the device are obtained and partitioned into distributed capacitive elements. With the distributed capacitive network known, a novel closed-form inductance extraction is presented, and an original series-resistance extraction is also proposed, which takes into account the distributed nature of the parasitic capacitive effects in the device model. The proposed extraction strategy has been applied to a 1.2-mm GaN HEMT and an uncertainty analysis has been performed on the basis of artificial and real S-parameters, applying the measurement uncertainty model of a commercial vector network analyzer.

Universal Frequency-Domain Analysis of N-Path Networks

N-path commutated capacitive networks provide a practical solution to implement highly sought on-chip high-Q filtering applications in which the use of lumped inductors is undesirable due to their significant footprints and low Q-factors. Recently, it has been also revealed that N-path networks can also exhibit other interesting functionalities, such as nonreciprocal phase-shifting and ultra-wideband true time delay, providing a path to miniaturization of various reciprocal and nonreciprocal devices. The analytical treatment of these networks, however, remains challenging, because their operation involves frequency mixing produced by the time modulation. In this article, we present a highly accurate frequency-domain approach for the analysis of N-path networks based on perturbation theory. Our method compares favorably to the state-of-the-art polyphase analysis by being much simpler mathematically, yet providing results essentially indistinguishable from numerical simulations, while offering physical insights into the N-path filter operation. We particularize the solution for the high-Q operation regime and obtain simple closed-form analytical expressions for harmonic transfer functions, scattering parameters and baseband impedance.

Structured identification for network reconstruction of RC-models

Abstract Resistive–capacitive (RC) networks are used to model various processes in engineering, physics or biology. We consider the problem of recovering the network connection structure from measured input–output data. We address this problem as a structured identification one, that is, we assume to have a state-space model of the system (identified with standard techniques, such as subspace methods) and find a coordinate transformation that puts the identified system in a form that reveals the nodes connection structure. We characterize the solution set, that is, the set of all possible RC-networks that can be associated to the input–output data. We present a possible solution algorithm and show some computational experiments.

Modeling and analysis of microstrip annular ring antenna with capacitive coupling matching network

In this manuscript, microstrip annular ring antenna with capacitive coupling matching network is modeled and analyzed with equivalent circuit model and cavity model, which is simple and accurate for this structure. The proposed approach not only demonstrates physics lying behind the engineering design but also will be a good guideline for the microstrip annular ring antenna design. A prototype working UHF RFID band (902-928 MHz) is designed. Overall dimension of the proposed antenna is about 0.5λ0 × 0.5λ0 × 0.055λ0, and the realized gain is larger than 5 dB with axial ratio is smaller than 3 dB. The measured results agree well with simulated counterparts except slightly frequency shift.

(Invited) Computing with Memristive Devices and Arrays

Memristive devices have become a promising candidate for unconventional computing due to their attractive properties(1). The computing can be implemented on a Resistive Neural Network (ResNN) with memristor synapses and neurons or a Capacitive Neural Network (CapNN) with memcapacitor synapses and neurons(2).For ResNNs as computing accelerators, we have built a dot-product engine based on a 128 x 64 1T1R crossbar array using traditional non-volatile memristors with 64 stable analog resistance levels(3). With such computation accelerators, we have demonstrated efficient inference and learning with traditional Machine Learning algorithms(4-7), which is expected to significantly improve the speed and energy efficiency of neural networks.For ResNNs beyond accelerator applications, we developed diffusive memristors(8)with diffusion dynamics that is critical for neuromorphic functions. Based on the diffusive memristors, we have further developed artificial synapses(8)and neurons(9)to more faithfully emulate their bio-counterparts. We then integrated these artificial synapses and neurons into a small neural network, with which pattern classification and unsupervised learning have been demonstrated(9).For CapNNs, we have developed pseudo-memcapacitive devices based on the diffusive memristors. Capacitive synapses and neurons enabled by these memcapacitive devices have been developed and used to form a fully integrated CapNN(10), which can implement spiking signal classification and Hebbian-like learning. Z. Wanget al., Resistive switching materials for information processing. Nature Reviews Materials 5, 173–195 (2020). Q. Xia, J. J. Yang, Memristive crossbar arrays for brain-inspired computing. Nature materials 18, 309-323 (2019). C. Liet al., Analogue signal and image processing with large memristor crossbars. Nature Electronics 1, 52-59 (2018). Z. Wanget al., Reinforcement learning with analogue memristor arrays. Nature Electronics 2, 115-124 (2019). Z. Wanget al., In situ training of feed-forward and recurrent convolutional memristor networks. Nature Machine Intelligence 1, 434-442 (2019). C. Liet al., Long short-term memory networks in memristor crossbar arrays. Nature Machine Intelligence 1, 49-57 (2019). P. Linet al., Three-dimensional memristor circuits as complex neural networks. Nature Electronics 3, 225–232 (2020). Z. Wanget al., Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nature Materials 16, 101-108 (2017). Z. Wanget al., Fully memristive neural networks for pattern classification with unsupervised learning. Nature Electronics 1, 137-145 (2018). Z. Wanget al., Capacitive neural network with neuro-transistors. Nature Communications 9, 3208 (2018).

An efficient approach to optimization of semi‐stable routing in multicommodity flow networks

AbstractIdeally, the network should be dynamically reconfigured as traffic evolves. Yet, even within the software defined network paradigm, network reconfigurations cannot be too frequent due to a number of reasons related to route consistency, forwarding rules instantiation, individual flows dynamics, traffic monitoring overhead, and so on. In this paper, we focus on the fundamental issue of deciding whether, when, and how to reconfigure the network while traffic evolves. We consider a problem of optimizing semi‐stable routing in the capacitated multicommodity flow network when one may use at most a given maximum number of routing configurations (called routing clusters) and when each routing configuration must be used for at least a given minimum amount of time. We propose an efficient solution approach based on routing cluster generation that provides a tight lower bound on the minimum of a selected objective function (like maximum link delay or a sum of link delays) and suboptimal solutions very close to the calculated bound. The approach scales well with the size of the network.

A method to extract lumped thermal networks of capacitors for reliability oriented design

In this work we propose a procedure based on finite element simulations to compute a lumped-parameter thermal model of capacitors. The extracted Foster or Cauer network coupled to the electrical model can be useful to evaluate the temperature of capacitors in circuit simulators as SPICE or Simulink. In this way, it is possible to evaluate the expected maximum operative temperature of the capacitor embedded in a circuit before its real application, avoiding unexpected failures since the prototyping stage. Here, we describe the workflow of the method and, finally, the proposed approach will be used for designing snubber capacitors for medium power (60 kW) high frequency AC/AC converter.

A Wide Voltage Gain Bidirectional DC–DC Converter Based on Quasi Z-Source and Switched Capacitor Network

Bidirectional DC-DC converters are critical aspects of integrating energy storage units with hybrid electric vehicle. In this brief, a new bidirectional DC-DC converter is presented based on the quasi Z-source and switched capacitor network. The proposed converter can achieve higher voltage gain in a lower duty cycle as compared to existing converters reported in the literature. The proposed converter achieves high gain in low duty cycle range thus avoids the inductor core saturation problem in converters. In addition, the proposed converter exhibits lower voltage stress across capacitors. The proposed converter operation, steady-state analysis, voltage and current stress analysis are discussed along with comparative analysis is also presented. For validating the feasibility of the proposed converter, an simulation and experimental setup is designed.

A Variable-Gain Low-Noise Transimpedance Amplifier for Miniature Ultrasound Probes

This article presents a low-noise transimpedance amplifier (TIA) designed for miniature ultrasound probes. It provides continuously variable gain to compensate for the time-dependent attenuation of the received echo signal. This time-gain compensation (TGC) compresses the echo-signal dynamic range (DR) while avoiding imaging artifacts associated with discrete gain steps. Embedding the TGC function in the TIA reduces the output DR, saving power compared to prior solutions that apply TGC after the low-noise amplifier. The TIA employs a capacitive ladder feedback network and a current-steering circuit to obtain a linear-in-dB gain range of 37 dB. A variable-gain loop amplifier based on current-reuse stages maintains constant bandwidth in a power-efficient manner. The TIA has been integrated in a 64-channel ultrasound transceiver application-specific integrated circuit (ASIC) in a 180-nm BCDMOS process and occupies a die area of 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It achieves a gain error below ±1 dB and a 1.7 pA/√Hz noise floor and consumes 5.2 mW from a ±0.9 V supply. B-mode images of a tissue-mimicking phantom are presented that show the benefits of the TGC scheme.

An efficient macro model for CMOS-MEMS thermal wind speed sensor

In this paper, we propose a thermal wind speed sensor Verilog-A model with thermal-fluid-electric hybrid characteristics. Because the structure of the thermal wind sensor and the interface circuit chip are designed separately, which cannot effectively carry out MEMS-IC (integrated circuit) co-simulation, the overall performance of the sensor and interface circuit chip is prone to large deviation. At the same time, the separation of MEMS structure and IC design process leads to long product development cycle and high cost. This paper proposes an improved simulation model by analyzing the behavior characteristics of the thermal wind speed sensor. The simulation model consists of 11 thermistors, 3 capacitors, a voltage-controlled voltage source, and a voltage-controlled current source. The Taylor series expansion of the differential equation of heat conduction is carried out, and then the thermistor and capacitor networks are established according to the corresponding relationship between the thermal parameters and the electrical parameters, including the thermal conduction unit, the convection unit and the heat capacity in the chip. The model fully considers the effects of various physical effects and parasitic effects, and is implemented using the hardware description language Verilog-A. The sensor and interface circuit can be simulated simultaneously to optimize the circuit design. It is beneficial to the integration of sensors and interface circuit, reducing the number of tape-outs, increasing the success rate, and reducing costs. The consistency between the simulation results and the experimental curves verified the correctness of the macro model. The behavior characteristics of constant power (CP) and constant temperature heating were described. In CP mode, the output voltage error is less than ± 6.5%, the chip temperature error is less than 4.0%. The presented modeling approach can be the basis for the development of complete MEMS-IC design technology library of thermal wind speed sensor, aiming at optimum designs of integrated thermal wind speed sensor.

Deep Dual-Optimal Inequalities for Generalized Capacitated Fixed-Charge Network Design Problems

Capacitated fixed-charge network design problems and generalizations, such as service network design problems, have a wide range of applications but are known to be very difficult to solve. Many exact and heuristic algorithms to solve these problems rely on column-and-row generation (CRG), which frequently suffer from primal degeneracy. We present a set of dual inequalities, equivalent to a simple primal relaxation, that speed up CRG algorithms for generalized capacitated fixed charge network design problems. We investigate the impact of the dual inequalities theoretically as well as experimentally. For practical applications, the presented technique is simple to implement, has no additional computational cost and can accelerate CRG by orders of magnitude, depending on the problem size and structure.

A Learning-Based Matheuristic for Stochastic Multicommodity Network Design

This paper proposes a solution approach for the multicommodity capacitated fixed-charge network design problem with uncertain demand modeled as a two-stage stochastic program. The proposed learning-based matheuristic combines heuristic search techniques with mathematical programming. It provides a systematic approach to identifying structures of good-quality solutions by gradually considering scenarios and their influences on design decisions. Extensive computational experiments illustrate the efficiency of the proposed matheuristic in obtaining high-quality solutions with limited computational efforts.

Variable fixing heuristics for the capacitated multicommodity network flow problem with multiple transport lines, a heterogeneous fleet and time windows

ABSTRACT In this paper, we investigate a new variant of the multi-commodity network flow problem, taking into consideration multiple transport lines and time windows. This variant arises in a city logistics environment, more specifically in a long-haul passenger transport system that is also used to transport urban freight. We propose two mixed integer programming models for two objective functions: minimization of network operational costs and minimization of travel times. Since the problems under study are NP-hard, we propose three size reduction heuristics. In order to assess the performance of the proposed algorithms, we carried out computational experiments on a set of synthetic problem instances. We use the relative percentage deviation as performance criterion. For the cost objective function, a LP-and-Fix algorithm outperforms other methods in most tested instances, but for the travel time, a hybrid method (size reduction with LP-and-Fix algorithm) is, in general, better than other approaches.

Analysis of the Multi-Steps Package (MSP) for Series-Connected SiC-MOSFETs

In this paper, a multi-step packaging (MSP) concept for series-connected SiC-MOSFETs is analyzed. The parasitic capacitance generated by the dielectric isolation of each device in the stack has a significant impact on the dynamic behavior of SiC devices, which impacts the voltage-sharing performances. The study performed in this work reveals that the parasitic capacitance network introduced by the classical planar packaging unbalances the voltage across the series-connected SiC-MOSFETs. Therefore, a new drain-source parasitic capacitance network configuration provided by the MSP is proposed in order to improve the voltage balancing across the series-connected devices. The concept is introduced and analyzed thanks to equivalent models and time domain simulations. To verify the analysis, the voltage sharing between four series-connected 1.2 kV SiC MOSFETs is tested in a double pulse test setup. The experimental results confirm that the MSP has a better performance than the classical one in terms of voltage sharing. Furthermore, the proposed investigation shows that the MSP increases the middle point dv/dt of the switching cell. Sensitive analysis and thermal management considerations are also discussed in order to clarify the MSP limitations and indicate the ways to optimize the MSP from a thermal point of view.

Minimum-cost capacitated fuzzy network, fuzzy linear programming formulation, and perspective data analytics to minimize the operations cost of American airlines

Minimum-cost capacitated fuzzy network is formulated as a fuzzy linear programming problem. A novel fuzzy linear programming formulation for minimum-cost capacitated fuzzy network where the total resource constraints are fuzzy is proposed. The proposed model is then implemented to minimize the operations cost of American Airlines. The research is helpful to identify the most profitable destinations for the American Airlines. Twelve origin/destination pairs are taken into considerations namely Atlantic (A), Latin American (L), Pacific (P) and Domestic (D). Flight operations capacity, Available Seat Miles ASM, is taken as a measure of capacity. The goal is to minimize the flight operations cost while ensuring maximum flight operations capacities to all destinations. This is followed by perspective data analytics for “What American Airline should do to be more profitable?” Perspective analytics suggest the airline to extend flight operations capacity in certain origin/destination pairs, whereas to maintain the previous approximate average capacity for those having high operations costs. The solution of the proposed fuzzy model suggests that flight operations capacity ASM can be significantly increased by 22345148 (000) with relatively small increase 1539356 (000) USD in operations cost. The fuzzy model is superior for it emphasizes to increase flight operations capacity ASM for the origin/destination pairs with minimum flight operations costs.

Boost-Type Single-Stage Step-Down Resonant Power Factor Correction Converter

Conventional boost power factor correction (PFC) converter is only suitable for two-stage power conversion system due to its high output voltage. Inherent step-up characteristic limits its applications in single-stage low voltage output. In this article, a boost-type single-stage step-down resonant PFC converter, which combines a boost PFC converter and a resonant switched capacitor network by using one active switch, is proposed and analyzed. Similar to conventional boost PFC converter, the proposed converter can achieve unity power factor and low input current ripple in universal-input applications. Moreover, the proposed converter can achieve step-down voltage conversion. Furthermore, high-efficiency is realized due to single-stage power conversion. The proposed converter is studied in terms of operation principle, voltage gain, power factor analysis, and key circuit parameters design. Finally, a 70-W prototype with 96.05% peak efficiency is built to verify the theoretical analysis results.