Abstract
In this paper, a multi-step packaging (MSP) concept for series-connected SiC-MOSFETs is analyzed. The parasitic capacitance generated by the dielectric isolation of each device in the stack has a significant impact on the dynamic behavior of SiC devices, which impacts the voltage-sharing performances. The study performed in this work reveals that the parasitic capacitance network introduced by the classical planar packaging unbalances the voltage across the series-connected SiC-MOSFETs. Therefore, a new drain-source parasitic capacitance network configuration provided by the MSP is proposed in order to improve the voltage balancing across the series-connected devices. The concept is introduced and analyzed thanks to equivalent models and time domain simulations. To verify the analysis, the voltage sharing between four series-connected 1.2 kV SiC MOSFETs is tested in a double pulse test setup. The experimental results confirm that the MSP has a better performance than the classical one in terms of voltage sharing. Furthermore, the proposed investigation shows that the MSP increases the middle point dv/dt of the switching cell. Sensitive analysis and thermal management considerations are also discussed in order to clarify the MSP limitations and indicate the ways to optimize the MSP from a thermal point of view.
Highlights
Silicon (Si) power devices have dominated the world of power electronics in recent years, and they have proven to be efficient in a wide range of applications
Wide band-gap (WBG) devices such as silicon carbide (SiC) MOSFETs have been intensively researched and developed for power electronics applications due to the substantial advantages their inherent material properties could realize at device level, such as high breakdown voltage, high operating electric field, high operating temperature, high switching frequency, and low losses [1,2,3]
These prototypes, i.e., the MPS package and planar one, are built thanks to stacked FR4 layers so as to verify the electrical behaviors without thermal considerations. These prototypes are used in a pulsed mode to avoid a significant temperature increase in the SiC-MOSFETs
Summary
Silicon (Si) power devices have dominated the world of power electronics in recent years, and they have proven to be efficient in a wide range of applications. The voltage balancing across the series-connected is signal mainlytiming caused by the tolerance in selection of power semiconductor devices, which have parameters with low spread and device parameters, package/layout parasitic components, and gate signal timing delays [7,8,9]. In addition to [7,8,9,10,11], and new concepts of gate packaging as described in clamping [12,13] have been reported interesting this, snubber circuits, active drive circuits, voltage techniques [7,8,9,10,11], and as new concepts contributions in an attempt to reduce or even remove the voltage unbalance among the seriesof packaging as described in [12,13] have been reported as interesting contributions in an attempt connected power devices.
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