Abstract
This paper presents a Multi-Step Packaging (MSP) concept for optimizing implementation of series-connected SiC-MOSFETs devices. The proposed package geometry considers optimal dielectric isolation for each device leading to a stairs like a multi-step geometry. It has a significant impact on the parasitic capacitances introduced by the packaging structure that are responsible for voltage unbalances. The concept is introduced and analyzed thanks to equivalent models and time domain simulations. Then, experimental results confirm that the proposed packaging concept is better than traditional 2D planar power modules in terms of voltage balancing. Furthermore, the proposed concept can improve the switching speed of the switching cell as explained and shown in this paper.
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