Capacitively-coupled Chopper Instrumentation Amplifier Research Articles

A 1.87 µW Capacitively Coupled Chopper Instrumentation Amplifier with a 0.36 mV Output Ripple and a 1.8 GΩ Input Impedance for Biomedical Recording

Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input impedance. The amplifier can easily saturate due to the chopper ripple of the CCIA, especially in extremely low noise problems. Therefore, ripple attenuation is required when designing CCIAs. To record biomedical information, a CCIA with a low power consumption and a low noise, low output ripple, and high input impedance (Zin) is presented in this paper. By introducing a ripple attenuation loop (RAL) including the chopping offset amplifier and a low pass filter, the chopping ripple can be reduced to 0.36 mV. To increase the Zin of the CCIA up to 1.8 GΩ, an impedance boost loop (IBL) is added. By using 180 nm CMOS technology, the 0.123 mm2 CCIA consumes 1.87 µW at a supply voltage of 1 V. According to the simulation results using Cadance, the proposed CCIA architecture achieves a noise floor of 136 nV/√Hz, an input-referred noise (IRN) of 2.16 µVrms, a closed-loop gain of 40 dB, a power supply rejection ratio (PSRR) of 108.6 dB, and a common-mode rejection ratio (CMRR) of 118.7 dB. The proposed CCIA is a helpful method for monitoring neural potentials.

An ultrahigh input impedance low noise analog front‐end design for epilepsy brain recording system

SummaryThis paper presents an ultrahigh input impedance, low noise, and wide bandwidth four‐channels analog front‐end (AFE) for low‐power neural recording systems. To achieve high input impedance, the buffer channels are placed between the electrodes and the main amplifier stage of the AFE. The buffer is designed with low noise and low power consumption to obtain high input impedance of overall AFE while maintaining low input‐referred noise and low power consumption. A chopper capacitively coupled chopper instrumentation amplifier (CCIA) is placed after the buffer as the main amplifier stage of the AFE to improve the common mode rejection ratio (CMRR) and the input‐referred noise of the overall AFE design. A new chopper stabilization control technique is proposed and used in the CCIA stage to reduce the charge injection and clock feedthrough and consequently the high‐frequency ripple of the AFE output signal. A programmable gain amplifier (PGA) is designed as the third stage to adjust the overall gain of the AFE. Benefiting from PGA, the AFE can adapt its gain with both action potential and local field potential signals. To reduce the number of the electrode to be implanted and reduce the impedance mismatch that causes the degradation on overall CMRR performance, two AFE channels shared a reference electrode followed by a reference buffer. The proposed AFE is designed and simulated using a standard 180 nm CMOS process and operates in a wide frequency band of 2.1 to 2500 Hz with low input‐referred noise of 1.6 μVrms and a CMRR over 80 dB at 2.1 Hz. The total power consumption is lower than 4.3 μW per channel. With the proposed structure of AFE, the input impedance is 35 GΩ @ 21 Hz and the minimum impedance over operational bandwidth is 75 MΩ @ 2.5 kHz.

0.36 μW/channel capacitively-coupled chopper instrumentation amplifier in EEG recording wearable devices for compressed sensing framework

We evaluated the effectiveness of a low-current-consumption amplifier for a compressed-sensing (CS) framework in wearable electroencephalography (EEG) recording devices. The amplifier uses a capacitively coupled chopper instrumentation amplifier (CCIA) architecture which is often used for low-noise amplifier (LNA) to achieve low consumption and low-noise characteristics. According to measurements of the designed CCIA, the power consumption was 0.36 μW/channel, and the input referred noise (IRN) was 4.47 μVrms. The measured IRN and simulations were used to confirm the effect of CCIA noise on the CS-based EEG measurement framework. The difference in the normalized mean squared error at CR = 4 to the uncompressed conditions could be reduced to 0.008. The findings show that even with the LNA specialized for low power consumption, a slight signal degradation is observed when the compression ratio is increased up to 4 in the CS framework by utilizing the sparsity of EEG in the frequency domain.

A Capacitively Coupled Chopper Instrumentation Amplifier With Deadtime Offset Reduction Technique for Neural Signal Sensing

A Capacitively Coupled Chopper Instrumentation Amplifier With Deadtime Offset Reduction Technique for Neural Signal Sensing

Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications

This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.

A chopper amplifier with a low duty‐cycle sub‐sampling in the switched‐capacitor integrator for noise reduction

AbstractThis letter presents a low‐noise implementation of the switched‐capacitor (SC) DC servo loop (DSL) in the capacitively coupled chopper instrumentation amplifier (CCIA). The noise of the SC integrator in SC DSL is first analyzed, then a low duty‐cycle subsampling and unbalanced capacitor ratio are proposed to reduce the noise. Fabricated in a 65‐nm complementary metal‐oxide semiconductor (CMOS) process, the CCIA achieves 2.5 μVrms input‐referred noise, integrated from 0.5 to 250 Hz, and 110‐mV electrode‐DC offset (EDO) cancellation range. Besides, the calculated noise of the SC integrator well matches the measured, which proves the noise analysis. Compared with prior designs adopting similar SC integrators, this work reduces the noise level by 2× and increases the cancellation range by 2×.

100.5 dB SNDR Analog Front-End With a Resistor-Based Discrete-Time Delta-Sigma Modulator for Eliminating Switching Noise and Harmonics

This paper presents a high-resolution analog front-end (AFE) circuit operating in the 25 kHz signal bandwidth. The AFE consists of a capacitively-coupled chopper instrumentation amplifier (CCIA) and a third-order delta-sigma modulator (DSM). Signal distortion often occurs at the junction of CCIA and DSM, so the resistor-based discrete-time DSM (RB DT–DSM) is proposed to solve this problem. Both conventional DT–DSM and the proposed RB DT–DSM are designed and compared through simulations and chip measurements. When a conventional DT–DSM is used, a switched-capacitor integrator with a large capacitor and switch are connected to the CCIA output node, so large switching noise, significant charge injection, and a long settling time occur at the CCIA output, resulting in harmonic distortions. Therefore, CCIA requires more power consumption to reduce the settling time for conventional DT–DSM architectures. On the other hand, when the proposed RB DT–DSM is used, only a resistor and a small switch are connected to the CCIA output. Due to this novel interface technique, the switching noise is very small at the CCIA output, and the settling of the CCIA becomes fast. As a result, it is possible to effectively eliminate harmonic distortions while reducing the power requirement of the CCIA. Both the conventional and proposed AFE circuits were manufactured by a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> complementary metal-oxide-semiconductor (CMOS) process. The conventional AFE shows a peak SNR of 101.1 dB and a peak SNDR of 91.2 dB. The proposed AFE with RB DT–DSM shows a peak SNR of 101.3 dB and a peak SNDR of 100.5 dB, which verifies the significant reduction in harmonic distortions.

A 0.52 μW, 38 nV/√Hz Chopper Amplifier With a Low-Noise DC Servo Loop, an Embedded Ripple Reduction Loop, and a Squeezed Inverter Stage

To realize an ultralow-power, low-noise amplifier for bio-potential recording, we investigate three design techniques. The first technique uses a noise-efficient squeezed inverter (SQI) stage biased at the supply of the $2{V} _{\mathrm{ DSAT}}$ saturation limit. The challenge of interfacing the SQI stage with such a low supply is addressed by proposing a new capacitively-coupled chopper instrumentation amplifier (CCIA) with a low-noise DC servo loop (L-DSL) and an embedded ripple reduction loop (E-RRL). The second technique is reducing the high noise contribution of the conventional DSL. The proposed L-DSL reduces the input-referred noise (IRN) by removing the charge dividing effect. The proposed E-RRL inserted inside the gain stage cancels the offset and achieves a ripple suppression without loading the output. The CCIA is implemented using a $0.18~\mu \text{m}$ CMOS process. The measured results show that the L-DSL successfully creates a sub-Hz high-pass corner needed to block the electrode offset. The E-RRL achieves a ripple suppression of 39 dB. The CCIA achieves 32 nV/ $\surd $ Hz noise density, which is slightly increased to 38 nV/ $\surd $ Hz when the L-DSL is enabled. The integrated noise over 800 Hz bandwidth is 0.9 and 1.1 $\mu \text{V}_{\mathrm{ rms}}$ without and with the L-DSL, respectively. The mid-band gain of 39.6 dB is achieved by consuming $0.52~{\mu }\text{W}$ . These results correspond to a favorable noise efficiency factor (NEF) of 2.1 and a power efficiency factor (PEF) of 1.2.

A 4.5 GΩ-Input Impedance Chopper Amplifier With Embedded DC-Servo and Ripple Reduction Loops for Impedance Boosting to Sub-Hz

Achieving a high input impedance Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> is important for the instrumentation amplifier (IA) performing neural and biopotential signal sensing. Previously, impedance boosting techniques have been used with a positive feedback loop (PFL) driven by the output or auxiliary (AUX) path driven by the input. We propose that the conventional approach to DC-servo loop (DSL), which blocks the electrode offset (EOS), does not fully enable the function of a PFL or AUX path. This results in either limited impedance boosting or reduction of a low-frequency Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> in the sub-Hz band. To solve this problem and achieve Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> boosting down to sub-Hz, we propose a new approach to DSL for a capacitively-coupled chopper instrumentation amplifier (CCIA). The proposed DSL is realized using a 30-nA opamp, and the AUX path is designed using a 450-nA duty-cycled buffer. The CCIA achieves a gain of 40 dB and is implemented using a 0.18 μm CMOS process with an area of 0.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured results show that Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> is increased by 184 times up to 4.6 GQ at 0.01 Hz. Compared to the CCIA using conventional DSL, Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> is improved by 7.8 times. An input-referred noise of 2.1 μVrms is achieved at 2.14 μW.

A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing.

To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2VDSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µVrms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.

A 15.2-ENOB 5-kHz BW 4.5-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;W Chopped CT &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta\Sigma$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-ADC for Artifact-Tolerant Neural Recording Front Ends

Implantable closed-loop neural stimulation is desirable for clinical translation and basic neuroscience research. Neural stimulation generates large artifacts at the recording sites, which saturate existing recording front ends. This paper presents a low-power continuous-time delta-sigma analog to digital converter (ADC), which along with an 8 $\times $ gain capacitively-coupled chopper instrumentation amplifier (CCIA), realizes a front end that can digitize neural signals from 1 Hz to 5 kHz in the presence of 200-mVpp differential artifacts and 700-mVpp common-mode (CM) artifacts. A modified loop-filter is used in the ADC along with new linearization techniques to significantly reduce power consumption. Fabricated in 40-nm CMOS, the ADC occupies an area of 0.053 mm2, consumes 4.5 $\mu \text{W}$ from a 1.2-V supply, has an input impedance of 20 $\text{M}\Omega $ and bandwidth (BW) of 5 kHz, and achieves a peak signal to noise and distortion ratio (SNDR) of 93.5 dB for a 1.77- $\text{V}_{\mathrm {pp}}$ differential input at 1 kHz. The ADC’s figure of merit (FOM) (using SNDR) is 184 dB, which is 6 dB higher than the state of the art in high-resolution ADCs. The complete front end occupies an area of 0.113 mm2, consumes 7.3 $\mu \text{W}$ from a 1.2-V supply, has a dc input impedance of 1.5 $\text{G}\Omega $ , input-referred noise of 6.35 $\mu \text{V}_{\mathrm {rms}}$ in 1 Hz–5 kHz, and total harmonic distortion of −81 dB for a 200-mVpp input at 1 kHz, and is immune to 700-mVpp CM interference. Compared to front ends intended for closed-loop neural recording, this paper improves the linear input range by 2 $\times $ , the signal BW by 10 $\times $ , the dynamic range by 12.6 dB, the FOM by 12.4 dB and remains immune to large CM interference while maintaining comparable power, area, and noise performance.

A Current-Mode Capacitively-Coupled Chopper Instrumentation Amplifier for Biopotential Recording With Resistive or Capacitive Electrodes

This brief presents a high-density, low-noise analog front-end (AFE) for capacitively coupled neural recording applications. Conventional capacitively coupled AFEs, when chopper-stabilized, require large coupling capacitors or servo loops to minimize $ {1/f^{2}}$ input-referred noise and chopper-induced offsets, limiting channel density. In this brief, a current-mode capacitively coupled chopper instrumentation amplifier with embedded delta-sigma analog-to-digital converter (ADC) is presented that enables an area-efficient low-noise design via chopper-stabilized current-mode amplification. In this design, 60 channels are implemented in a $ {2 \times 2}$ mm2 180-nm CMOS chip, and each channel consumes $4~ {\mu }\text{W}$ , achieves an input referred noise of 160 nV/ $\sqrt {\text{Hz}}$ , and an ADC effective number of bits of 8.5 bits.

A micropower analogue front end for wireless ECG system

ABSTRACTRecently, the growing demand of low power, low noise and miniaturised size for biopotential integrated front end have drawn a lot of research interests. This paper proposed an analogue front end for wireless ECG system. It consists of a capacitively coupled chopper instrumentation amplifier (CCIA), chopper spike filter (CSF), band-pass filter and clock generator. 1/f noise and offset of the first stage are filtered by the chopping technology. The spikes generated by the input chopper of CCIA are filtered by the CSF. The band-pass filter sets the bandwidth of the front end. The front end was implemented in a 0.13-m complementary metal-oxide-semiconductor process. It achieves 46.3 dB gain, 100 dB common mode rejection ratio and 5 A current consumption. Meanwhile, other state-of-the-art performances in terms of input common mode, dc-electrode offset and noise were also achieved with a chip area of 0.075 mm2. The results prove that the chip has the possibility to apply into the wireless ECG system for long-term homecare.

Fully Integrated Biopotential Acquisition Analog Front-End IC.

A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 µm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm2. A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 µVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.