Capacitive Transimpedance Amplifier Research Articles

A Noninvasive Glucose Monitoring SoC Based on Single Wavelength Photoplethysmography.

Conventional glucose monitoring methods for the growing numbers of diabetic patients around the world are invasive, painful, costly and, time-consuming. Complications aroused due to the abnormal blood sugar levels in diabetic patients have created the necessity for continuous noninvasive glucose monitoring. This article presents a wearable system for glucose monitoring based on a single wavelength near-infrared (NIR) Photoplethysmography (PPG) combined with machine-learning regression (MLR). The PPG readout circuit consists of a switched capacitor Transimpedance amplifier with 1MΩ gain and a 10-Hz switched capacitor LPF. It allows a DC bias current rejection up to 20μA with an input-referred current noise of 7.3pA/√Hz. The proposed digital processor eliminates motion artifacts, and baseline drifts from PPG signal, extracts six distinct features and finally predicts the blood glucose level using Support Vector Regression with Fine Gaussian kernel (FGSVR) MLR. A novel piece-wise linear (PWL) approach for the exponential function is proposed to realize the FGSVR on-chip. The overall system is implemented using a 180nm CMOS process with a chip area of 4.0mm2 while consuming 1.62mW. The glucose measurements are performed for 200 subjects with R2 of 0.937. The proposed system accurately predicts the sugar level with a mean absolute relative difference (mARD) of 7.62%.

A Digital Readout IC for Microbolometer Imagers Offering Low Power and Improved Self-Heating Compensation

This paper presents a novel and power efficient readout architecture for uncooled microbolometers that offers adequate noise performance along with a circuit-based method for self-heating compensation. The proposed method employs an event-generation scheme and a time-mode readout chain to achieve dynamic mode of operation resulting in low power. The readout chain consists of a capacitive transimpedance amplifier (CTIA) based current-to-time converter followed by a two stage time-to-digital converter (TDC). The CTIA employs a novel integration scheme for time amplification along with a modified reset mechanism to achieve self-heating compensation. We also present a model to analyze the implications of time-mode readout on imager operation. An experimental readout chip, based on this approach, has been designed using a 130 nm bulk CMOS technology. The proposed architecture offers robust frontend processing and achieves a per channel power consumption of $66~\mu \text{W}$ , which is considerably lower than the most recently reported designs, while maintaining better than 10-mK readout noise equivalent temperature difference (NETD).

A Novel Current-Controlled Oscillator-Based Low-Supply-Voltage Microbolometer Readout Architecture

In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10–15[Formula: see text]pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach.

Investigation of soft ESD failure on capacitive transimpedance amplifier for hybrid integrated infrared sensor

Investigation of soft ESD failure on capacitive transimpedance amplifier for hybrid integrated infrared sensor

Chip-Scale Angle-Selective Imager for In Vivo Microscopic Cancer Detection.

We present an image sensor incorporating angle-selective gratings for resolution enhancement in contact imaging applications. Optical structures designed in the CMOS metal layers above each photodiode form the angle-selective gratings that limit the sensor angle of view to ±18 °, rejecting background light and deblurring the image. The imager is based on a high-gain capacitive transimpedance amplifier pixel using a custom 11fF MOM capacitor, achieving [Formula: see text] sensitivity. The pixel includes a leakage current minimization circuit to remove signal-dependent reset switch leakage and the corresponding dark current is [Formula: see text]. The resulting 4.7 mm by 2.25 mm sensor (80 by 36pixels) is designed specifically for intraoperative cancer imaging in order to solve the pervasive challenge of identifying microscopic residual cancer foci in vivo, where they can be removed. We demonstrate imaging and detection of foci containing less than 200 cancer cells labeled with fluorescent biomarkers in 50 ms with signal-to-noise ratios greater than 15 dB and the detection of microscopic residual tumor in mice models. The absence of large optical elements enables extreme miniaturization, allowing manipulation within a small, morphologically complex, tumor cavity.

Low-light-level CMOS imaging sensor with CTIA and digital correlated double sampling

This paper presents two low-light-level CMOS image sensors with capacitive transimpedance amplifier (CTIA) and digital correlated double sampling (CDS). In order to achieve high sensitivity for low-light-level CMOS image sensor, the CTIA pixel circuit with a small integration capacitor is used. In order to remove the noise of the low-light-level CMOS image sensor, a digital CDS is designed, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise, pixel fixed-pattern noise (FPN) and the column FPN can be greatly reduced by this digital CDS. Two test chips based on this method with 256 × 256 pixel array are fabricated in a 0.35 μm CMOS technology, one is based on DC-coupled CTIA pixel circuit, and the other one is based on AC-coupled CTIA pixel circuit. These two chips are designed with the same column sigma-delta analog-to-digital (∑∆ ADC), whose resolution is 15-bit. At a frame rate of 7 fps, the low-light-level CMOS image sensor with DC-coupled CTIA pixel circuit and digital CDS can capture recognizable images with the illumination down to 0.05 lux. The low-light-level CMOS image sensor with AC-coupled CTIA pixel circuit can reduce the dark current by reducing the reverse bias voltage of the photodiode.

Hybrid CMOS detectors for the Lynx x-ray surveyor high definition x-ray imager

X-ray hybrid CMOS detectors (HCDs) are a promising candidate for future x-ray missions requiring high throughput and fine angular resolution along with large field-of-view, such as the high-definition x-ray imager (HDXI) instrument on the Lynx x-ray surveyor mission concept. These devices offer fast readout capability, low power consumption, and radiation hardness while maintaining high detection efficiency from 0.2 to 10 keV. In addition, x-ray hybrid CMOS sensors may be fabricated with small pixel sizes to accommodate high-resolution optics and have shown great improvements in recent years in noise and spectral resolution performance. In particular, 12.5-{\mu}m pitch prototype devices that include in-pixel correlated double sampling capability and crosstalk eliminating capacitive transimpedance amplifiers, have been fabricated and tested. These detectors have achieved read noise as low as 5.4 e-, and we measure the best energy resolution to be 148 eV (2.5%) at 5.9 keV and 78 eV (14.9%) at 0.53 keV. We will describe the characterization of these prototype small-pixel x-ray HCDs, and we will discuss their applicability to the HDXI instrument on Lynx.

A high-precision and high-linearity readout integrated circuit for infrared focal plane array applications

This paper proposes a readout integrated circuit (ROIC) with high precision and high linearity based on the standard capacitive transimpedance amplifier (CTIA) structure. A high-swing cascode current mirror is introduced, which can restrain the influence of the front-end unstable voltage on the integrating unit. Also, the high-swing cascode current mirror can reduce the influence of the integral nonlinear error caused by the finite gain of the amplifier on the bias point, which will significantly increase the linearity and reduced the nonlinear error of the output. Moreover, buffered direct injection method is adopted in the bias circuit in order to ensure the bias point stability and reduce the non-uniformity. A 4 × 2 experimental chip have been fabricated by adopting AMS 0.35 μm CMOS process. The simulation and experimental results demonstrate the ROIC with the features of high linearity, high injection efficiency, stable bias point and low noise, which is suitable for high performance applications.

Pixel Optimizations and Digital Calibration Methods of a CMOS Image Sensor Targeting High Linearity

In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype image sensor designed in 0.18- $\mu \text{m}$ , 1-poly, and 4-metal CIS technology with a pixel array of $128 \times 160$ is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor $C_{\textit {FD}}$ on the floating diffusion node, which is remnant in VM.

A high-performance operational amplifier for infrared readout circuit application

The infrared readout circuit is a highly integrated circuit that integrates various functions into a single semiconductor chip. As the important part of readout circuit, the operational amplifier (OPA) decides the performance of the readout circuit. This paper describes a kind of OPA, which is used in infrared focal plane array (IRFPA) readout circuit structure based on the capacitive trans-impedance amplifier (CTIA) including the analysis and design of the OPA. Spectra is employed to simulate the circuit and obtain the results which is according with the designed objectives. The open-loop gain reaches 101 dB and the phase margin is 87°with the ICMR (input common-mode range) ranging from 201.6 mV to 4.01 V．

A High-SNR and Process-insensitive CMOS Capacitive Transimpedance Amplifier with Finely Tunable Conversion Gain

A High-SNR and Process-insensitive CMOS Capacitive Transimpedance Amplifier with Finely Tunable Conversion Gain

CMOS Image Sensor for Lateral Flow Immunoassay Readers

Point-of-care (POC) systems for the detection of infectious diseases are in great demand especially in developing countries. Lateral flow immunoassays are considered ideal biosensors for POC diagnostics due to their numerous advantages. However, to quantify their results a low power, robust electronic reader is needed. A low power CMOS image sensor is presented that can be used in quantitative lateral flow immunoassay readers. It uses a single low power processing capacitive transimpedance amplifier architecture which includes noise cancellation. A chip containing $4\times 64$ pixels was fabricated in CMOS 0.35- $\mu\text{m}$ technology. With uniform illumination at 525 nm and 67 frames/s the chip has 1.9 mVrms total output referred noise and a total power consumption of 21 $\mu\text{W}$ . In tests with lateral flow immunoassays the chip detected concentrations of influenza A nucleoprotein from 0.5 ng/mL to 200 ng/mL.

A Test Platform for the Noise Characterization of SiGe Microbolometer ROICs

This paper introduces an in-circuit performance evaluation system for SiGe microbolometer readout integrated circuits (ROICs) that can characterize the overall system noise performance by emulating microbolometers with MOSFETs biased in the triode region. Specifically, the proposed test platform is designed for the testing of imagers with high resistance SiGe microbolometers. The architecture of the ROIC is based on a bridge with active and reference bolometer pixels with a capacitive transimpedance amplifier input stage and column parallel integration with serial readout. Noise measurements along with simulated resistance curves of the dummy detectors are reported. The prototype with 17-μm pixel pitch has been designed and fabricated in a 0.25-μm SiGe BiCMOS process.

A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm2) responsivity and 4.38-nW/cm2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

低照度CMOS图像传感器设计与实现

A low-light-level CMOS image sensor with Capacitive Trans-impedance Amplifier(CTIA) pixel circuit and Delta Double Sampling(DDS) was proposed. By using CTIA circuit, stable bias voltage of the photodiode and high injection ratio can be realized, and the weak signal in low-light-level condition can be readout; Meanwhile, an off-chip digital DDS was used to reduce the fixed pattern noise (FPN) which was realizing the subtraction algorithm between the reset signal and pixel signal after A/D conversion off-chip, and improve the image quality of the low-light-level CIS. This low-light-level CMOS image sensor (CIS) based on CTIA pixel circuit was implemented in the 0.35 m standard CMOS technology. The pixel array was 256256, and the pixel size was 16 m16 m. The experimental results show that this low-light-level CIS can capture recognizable images with the illumination down to 0.05 lx.

Proof of Concept Coded Aperture Miniature Mass Spectrometer Using a Cycloidal Sector Mass Analyzer, a Carbon Nanotube (CNT) Field Emission Electron Ionization Source, and an Array Detector.

Despite many potential applications, miniature mass spectrometers have had limited adoption in the field due to the tradeoff between throughput and resolution that limits their performance relative to laboratory instruments. Recently, a solution to this tradeoff has been demonstrated by using spatially coded apertures in magnetic sector mass spectrometers, enabling throughput and signal-to-background improvements of greater than an order of magnitude with no loss of resolution. This paper describes a proof of concept demonstration of a cycloidal coded aperture miniature mass spectrometer (C-CAMMS) demonstrating use of spatially coded apertures in a cycloidal sector mass analyzer for the first time. C-CAMMS also incorporates a miniature carbon nanotube (CNT) field emission electron ionization source and a capacitive transimpedance amplifier (CTIA) ion array detector. Results confirm the cycloidal mass analyzer's compatibility with aperture coding. A >10× increase in throughput was achieved without loss of resolution compared with a single slit instrument. Several areas where additional improvement can be realized are identified. Graphical Abstract ᅟ.

A Mobile-Based High Sensitivity On-Field Organophosphorus Compounds Detecting System for IoT-Based Food Safety Tracking

A mobile-based high sensitivity absorptiometer is presented to detect organophosphorus (OP) compounds for Internet-of-Things based food safety tracking. This instrument consists of a customized sensor front-end chip, LED-based light source, low power wireless link, and coin battery, along with a sample holder packaged in a recycled format. The sensor front-end integrates optical sensor, capacitive transimpedance amplifier, and a folded-reference pulse width modulator in a single chip fabricated in a 0.18 μm 1-poly 5-metal CMOS process and has input optical power dynamic range of 71 dB, sensitivity of 3.6 nW/cm2 (0.77 pA), and power consumption of 14.5 μW. Enabled by this high sensitivity sensor front-end chip, the proposed absorptiometer has a small size of 96 cm3, with features including on-field detection and wireless communication with a mobile. OP compound detection experiments of the handheld system demonstrate a limit of detection (LOD) of 0.4 μmol/L, comparable to that of a commercial spectrophotometer. Meanwhile, an android-based application (APP) is presented which makes the absorptiometer access to the Internet-of-Things (IoT).

Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing

A new 96 $\times$ 96 array of $30 \mu\text{m}\times 30 \mu\text{m}$ readout integrated circuit (ROIC) with an individual pixel tunable bias control is demonstrated. Detailed IC design, test structures, readout circuit building blocks, and applied techniques are discussed. The new ROIC is capable of providing a large voltage swing for the bias in both positive and negative polarities to each individual pixel, independently. These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier (CTIA) CMOS ROIC architecture. An FPGA-based test bench has also been developed to test and characterize the new ROIC system, for which software and hardware are described in detail. The test chip has been fabricated with 2P4M 0.35 $\mu\text{m}$ high-voltage CMOS technology, where the bias voltage range is ±5 V and the output swing range is ±3.9 V. The demonstrated ROIC is an ideal infrastructure for implementation of region of interest enhancement and a solid base for infrared multispectral acquisition targeting an infrared retina.

A Global-Shutter Centroiding Measurement CMOS Image Sensor With Star Region SNR Improvement for Star Trackers

A star tracker is a critical sensor for determining and controlling the attitude of a satellite. It utilizes a complementary metal–oxide–semiconductor (CMOS)-active pixel sensor to map the star field onto the focal plane. Starlight is measured and star centroids are calculated to estimate attitude knowledge. In this paper, we present a CMOS image sensor for star centroid measurement in star trackers. To improve sensitivity to low-level starlight, the capacitive transimpedance amplifier pixel is used as the detector. To improve centroiding accuracy, the proposed sensor architecture allows star pixels, pixels that are above a star threshold, to cluster together. The mean value of all the pixels in this cluster is calculated. The star signals are then amplified in relation to this mean value. This increases the signal-to-noise ratio in star regions in line with their starlight intensity. An adaptive region-of-interest readout architecture is also proposed, which reports only star regions instead of the entire frame. The proof-of-concept chip, containing a $128 \times 128$ pixel array, was fabricated using AMS 0.35- $\mu \text{m}$ CMOS Opto process. Each pixel has a size of $31.2 \times 31.2~\mu \text{m}^{2}$ . The measurement results show that centroiding accuracy increases with higher centroiding gain. Within a limited exposure time, the relative centroiding accuracy can surpass that of a commercial image sensor by more than 1%.