A harmonic-tuned (HT) voltage-controlled oscillator in a 65-nm CMOS process is demonstrated in this letter. The oscillation frequency and harmonics are tuned independently by two separated high- $Q$ resonators. A novel F23 inductor–capacitor resonator resonating at the second and third harmonics simultaneously is introduced. The proposed F23 inductor has a high-quality factor of 15 and 24 in common-mode (CM) and differential-mode (DM), respectively. The simulation results show that a 4.3-dB phase noise (PN) improvement is achieved in the thermal noise region due to the high- $Q$ HT method. Meanwhile, less harmonic currents are injected into the fundamental resonator due to the source-degeneration principle, hence decreasing the Groszkowski effect and suppressing the flicker noise. The measured PN is −117.5 dBc/Hz at the 1-MHz offset, and the tuning range is 12% from 6.80 to 7.66 GHz. The flicker noise corner is around 220 kHz and the figure-of-merit is 187.2 dBc/Hz. The power consumption is 5 mW under a 0.55-V supply.