Capacitance-voltage Measurements Research Articles

Nanoporous GaN on p-type GaN: a Mg out-diffusion compensation layer for heavily Mg-doped p-type GaN

Embedding p-type gallium nitride (p-GaN) with controlled Mg out-diffusion in adjacent epitaxial layers is a key for designing various multi-junction structures with high precision and enabling more reliable bandgap engineering of III-nitride-based optoelectronics and electronics. Here, we report, for the first time, experimental evidence of how nanoporous GaN (NP GaN) can be introduced as a compensation layer for the Mg out-diffusion from p-GaN. NP GaN on p-GaN provides an ex-situ formed interface with oxygen and carbon impurities, compensating for Mg out-diffusion from p-GaN. To corroborate our findings, we used two-dimensional electron gas (2DEG) formed at the interface of AlGaN/GaN as the indicator to study the impact of the Mg out-diffusion from underlying layers. Electron concentration evaluated from the capacitance-voltage measurement shows that 9 × 1012 cm−2 of carriers accumulate in the AlGaN/GaN 2DEG structure grown on NP GaN, which is the almost same number of carriers as that grown with no p-GaN. In contrast, 2DEG on p-GaN without NP GaN presents 9 × 109 cm−2 of the electron concentration, implying the 2DEG structure is depleted by Mg out-diffusion. The results address the efficacy of NP GaN and its’ role in successfully embedding p-GaN in multi-junction structures for various state-of-the-art III-nitride-based devices.

4H-SiC p-i-n Low-Energy X-Ray Detectors With P-Layer Formed by Al Implantation

The results of electrical characterization and X-ray detection measurement of 4H-SiC p-i-n diodes with the p-layer formed by Al implantation are reported. From the capacitance-voltage measurement, the effective doping concentration of the 4H-SiC epitaxial layer is determined to be <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.88\times 10^{14}$ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup> . The detectors exhibited a consistently low leakage current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 6$ </tex-math></inline-formula> pA at −150 V, indicating excellent reverse blocking properties of the p-n junction formed by Al implantation. The measured full width at half maximum (FWHM) of the 59.5 keV gamma-ray peak is ~4.2 keV, corresponding to an energy resolution of 7%. In addition, the characteristic X-rays emitted from the V, Mn, Fe, Ni, Ge, Y, and Mo targets are detected by reducing the noise limit in the preamplifier. The linearity error between the peak channel and the featured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K\alpha $ </tex-math></inline-formula> line energy is within 0.02%. The detector demonstrates an FWHM of 1.76 ± 0.1 keV at 4.9 keV and 1.67 ± 0.05 keV at 17.5 keV. The obtained results show that the SiC p-i-n diodes with p-layer formed by Al implantation can be used as promising low-energy X-ray detectors with reasonable resolution.

Effects of absorber near-interface compensation on Cd(Se,Te) solar cell performance

Arsenic (As) has been shown to be an effective p-type dopant for CdTe, although high performance in As-doped devices remains difficult to achieve. Arsenic is prone to self-compensation in CdTe, as evidenced by the accumulation of dopant atoms in CdTe/Cd(Se,Te) near the interface with MgxZn1-xO (MZO). In this study, we use SCAPS 1D modeling software to investigate the effect of near-interface compensation, helping elucidate loss pathways in present-day As-doped devices and informing future growth directions. We consider three possible results of As accumulation: shallow donors, deep recombination centers, and a thin layer of excess acceptor accumulation. The reduction in near-interface carrier concentration caused by shallow donors is shown to improve open-circuit voltages (Voc), whereas deep levels are detrimental to all performance parameters. The thin charge layer affects capacitance-voltage (CV) measurements by reducing the depletion width while maintaining the same carrier concentration, replicating CV behavior that has been observed in actual devices. These results illustrate the importance of monitoring dopant accumulation within 100 nm of the interface, and suggest that reducing or eliminating the As concentration in this region would be beneficial. An undoped Cd(Se,Te) layer at the interface is suggested as a possible device structure to boost performance.

Influence of oxygen-related defects on In-Ga-Sn-O semiconductor due to plasma-enhanced atomic layer deposition of Al2O3 for low-temperature thin-film transistor in terms of electrical properties

In-Ga-Sn-O (IGTO) thin-film transistors (TFTs) were fabricated with Al2O3 gate insulators by plasma-enhanced atomic layer deposition (PEALD) at a temperature of 150 °C. Electrical performances of IGTO TFTs were significantly affected by plasma conditions when Al2O3 was deposited on IGTO thin films by PEALD. Analyses of X-ray photoemission spectroscopy revealed that excessive oxygen species activated at high plasma power above 150 W were chemisorbed to IGTO films to create excess oxygen bonds such as oxygen interstitials (Oi). Distributions of density of states in IGTO bandgap extracted by photonic capacitance-voltage measurement matched well with positive bias stress (PBS) instability of TFTs. Split-oxygen interstitials [Oi (split)] first created on IGTO by oxygen plasma might migrate to the octahedral site by a constant high gate bias to form octahedral-oxygen interstitials [Oi2- (oct)] by capturing electrons under PBS and reside deep states. Significant changes of subthreshold slope in I-V characteristics during the recovery time after removing PBS indicated that these octahedral-oxygen interstitials such as Oi (oct) and Oi2- (oct) obviously originated from Oi (split) initially formed by plasma and that Oi (oct) defects created by a relaxation process acted as a neutral acceptor-like state above Fermi level and deteriorated electrical properties of IGTO TFT.

Improved Surface Passivation of Rear SiNx/AlOx Stacks in p‐Type Boron‐Doped Czochralski Silicon Wafers During Dark Annealing at Elevated Temperatures

Herein, the surface passivation quality of p‐type boron‐doped Czochralski silicon (Cz‐Si) wafers with passivated emitter and rear cell (PERC) structure during 200 °C dark annealing is investigated. During such a treatment, a reduction in the saturation current density (J 0) along with the degradation and regeneration of minority carrier lifetime can only be observed in PERC‐structured wafers that fast fired at high temperatures instead of in unfired wafers, which is possibly correlated with hydrogen injected into the silicon bulk during fast firing. Besides, no notable variations in J 0 can be observed in fast‐fired SiN x /n + /p‐Si/n + /SiN x symmetrical structure wafers during the same treatment, although their minority carrier lifetime undergoes degradation and regeneration cycles, demonstrating that the improved surface passivation comes from the rear surface of PERC structure. The capacitance–voltage measurement on the fabricated rear surface samples with metal‐insulator‐semiconductor (MIS) structure further demonstrates that the improved surface passivation is not related to field‐effect passivation. By comparing the surface state density of rear surface during dark annealing, it can be concluded that the improved rear surface passivation originates from the hydrogenation of surface defects such as dangling bonds, possibly by the outdiffused hydrogen from silicon bulk during such a treatment.

Controlling the fixed negative charge formation in Si/high- k interfaces

High-$k$ dielectrics ${\mathrm{Al}}_{2}{\mathrm{O}}_{3}$ and ${\mathrm{HfO}}_{2}$ are widely used in combination with Si to produce electronic components and solar cells. A negative fixed charge is known to appear at Si/high-$k$ material interface after high-temperature annealing, yet the formation mechanism of the negative charge is poorly understood. In this work, we investigate the parameters affecting the charge formation to provide a better understanding and control of the charge in deposition and postprocessing steps. We observe negative charge formation in the interface after annealing by capacitance-voltage measurement. We demonstrate the effects of annealing temperature and high-$k$ film thickness on the charge formation. We further discuss the mechanism of the charge formation and present results supporting one recently suggested mechanism explaining the negative charge as an acceptor state in the interface. We observe a structural modification of the interface produced by annealing with photoelectron spectroscopy as a core-level shift in ${\mathrm{SiO}}_{2}$ binding energy. We investigate the electrostatic potential and electron distribution in the interface by ab initio calculations to understand the effect of the structural modification on the electronic structure of the interface.

Investigation of structural, optical and electrical properties of TiO2 thin film-nanowire-based device for photodetector application

In this work, titanium dioxide (TiO2) has been used for fabricating the thin film (TF) and perpendicular nanowire (NW) arrays using the glancing angle deposition (GLAD) technique on p-type silicon (Si) substrates. X-ray diffraction (XRD) plots confirmed the presence of anatase and rutile phases in both structures. Transmission electron microscopy (TEM) indicates a TF layer of ∼150 nm and NW of ∼280 nm in length. The selected area electron diffraction (SAED) and energy dispersive X-ray spectroscopy (EDS) present the amorphous morphology and elemental composition. Strikingly, a 1.25 times boost in UV–Vis absorption was observed in TiO2 NW/TiO2 TF as compared to TiO2 TF samples. Bandgaps of the fabricated TiO2 TF and TiO2 NW/TiO2 TF were also determined to be 3.5 eV and 3.59 eV, respectively. The frequency-dependent responses of the TiO2 TF and TiO2 NW/TiO2 TF devices were investigated by capacitance-voltage (C–V) measurements. Moreover, the current density-voltage (J-V) characteristics exhibit an average 100 times increment in the current conduction of TiO2 NW/TiO2 TF as compared to the TiO2 TF device, which can be an excellent candidate in photodetection.

Determination of the background doping polarity for unintentionally doped AlGaAsSb and AlInAsSb avalanche photodiodes on InP substrates

Background doping polarity is a critical design parameter for the performance of many optoelectronic devices, including avalanche photodiodes. We have applied a technique by using capacitance–voltage (CV) measurements on double mesa structures with a p-i-n or n-i-p homojunction to determine the background polarity type of the unintentionally doped intrinsic region. Because CV measurements scale with the size of the mesa, they support design flexibility in producing variable-sized top and bottom mesa diameters. In this work, we grew, fabricated, and tested AlGaAsSb and AlInAsSb random alloy double mesa p-i-n structures and undertook CV measurements at 295, 150, and 77 K. It was found that the capacitance varied with the top mesa diameter for both material systems, and not the bottom mesa diameter, indicating that the unintentionally doped intrinsic region is n-type in nature.

Analysis of the temperature dependent electrical parameters of the heterojunction obtained with Au nanoparticles decorated perovskite strontium titanate nanocubes

Strontium titanate (STO) is one of the important members of the perovskite family and has a wide range of applications in optoelectronics. In this study, the rectifying properties of the heterojunction produced by gold (Au) decorated STO were investigated. Morphological and structural characterization of Au-STO material coated as a thin film, such as SEM, TEM, XRD was performed and the results showed that this structure is a suitable material for heterojunction structures. Current-voltage (I-V) measurements of Ni/Au-STO/n-Si heterojunction devices obtained by coating the Si surface with the spin coating method of Au-STO were performed in the dark and between 60 and 400 K. Additionally, capacitance-voltage (C-V) measurements of the device were made under the same conditions and between 80 and 360 K. Basic diode parameters such as ideality factor (n), barrier height (Фb), series resistance (Rs) were determined from the I-V characteristic of the device using Thermionic emission (TE), Cheung and Norde functions. According to the TE method, the ideality factor of the device was calculated as 1.12 and the barrier height was 0.65 eV at 300 K. The obtained results showed that the Ni/Au-STO/n-Si heterojunction has rectifying properties. In all three calculation methods, as the application temperature increased, the ideality factor of the device decreased and on the other hand, the barrier height increased. This change showed the temperature sensitivity of the Au-STO/n-Si junction.

Extraction of effective mobility of In0.8Ga0.2As/In0.52Al0.48As quantum well high-electron-mobility transistors on InP substrate

In this work, we explored the effective mobility of In-rich InxGa1-xAs/In0.52Al0.48As (x > 0.53) quantum well (QW) high-electron-mobility transistors (HEMTs) on an InP substrate. Historically, the carrier transport properties of these types of devices have been assessed mostly using their Hall mobility, not using the effective mobility, mainly because the excessive gate leakage current degrades and contaminates their measured capacitance voltage (CV) characteristics. However, our recent studies on these devices achieved a significant reduction in the gate leakage current, which motivated us to explore their effective mobility. In this work, therefore, we used a conventional split CV technique to determine and analyze the effective mobility of In0.8Ga0.2As/In0.52Al0.48As QW HEMTs. We also attempted to model the extracted effective mobility by considering three different scattering mechanisms—Coulombic scattering, phonon scattering and surface-roughness scattering— under the guidance of Matthiessen’s rule.

High Velocity, Low-Voltage Collective In-Plane Switching in (100) BaTiO3 Thin Films.

Ferroelectrics are being increasingly called upon for electronic devices in extreme environments. Device performance and energy efficiency is highly correlated to clock frequency, operational voltage, and resistive loss. To increase performance it is common to engineer ferroelectric domain structure with highly‐correlated electrical and elastic coupling that elicit fast and efficient collective switching. Designing domain structures with advantageous properties is difficult because the mechanisms involved in collective switching are poorly understood and difficult to investigate. Collective switching is a hierarchical process where the nano‐ and mesoscale responses control the macroscopic properties. Using chemical solution synthesis, epitaxially nearly‐relaxed (100) BaTiO3 films are synthesized. Thermal strain induces a strongly‐correlated domain structure with alternating domains of polarization along the [010] and [001] in‐plane axes and 90° domain walls along the [011] or [011¯] directions. Simultaneous capacitance–voltage measurements and band‐excitation piezoresponse force microscopy revealed strong collective switching behavior. Using a deep convolutional autoencoder, hierarchical switching is automatically tracked and the switching pathway is identified. The collective switching velocities are calculated to be ≈500 cm s−1 at 5 V (7 kV cm−1), orders‐of‐magnitude faster than expected. These combinations of properties are promising for high‐speed tunable dielectrics and low‐voltage ferroelectric memories and logic.

Electrical characteristics and deep-level transient spectroscopy of a fast-neutron-irradiated 4H–SiC Schottky barrier diode

The dependence of the electrical characteristics on the fast neutron fluence of an epitaxial 4H–SiC Schottky barrier diode (SBD) was investigated. The 30 MeV cyclotron was used for fast neutron irradiation. The neutron fluences evaluated through Monte Carlo simulation were in the 2.7 × 1011 to 1.45 × 1013 neutrons/cm2 range. Current–voltage and capacitance–voltage measurements were performed to characterize the samples by extracting the parameters of the irradiated SBDs. Neutron-induced defects in the epitaxial layer were identified and quantified using a deep-level transient spectroscopy measurement system developed at the Korea Atomic Energy Research Institute. As the neutron fluence increased from 2.7 × 1011 to 1.45 × 1013 neutrons/cm2, the concentration of the Z1/2 defects increased by approximately 20 times. The maximum defect concentration was estimated as 1.5 × 1014 cm−3 at a neutron fluence of 1.45 × 1013 neutrons/cm2.

Pyrite as promising monograin layer solar cell absorber material for in-situ solar cell fabrication on the Moon

Reliable energy sources are needed in order to keep a Lunar Base on the run, and solar energy is one of the most attractive options. There are two ways to achieve it – to bring necessary solar panels from the Earth or find a way to produce them in-situ on the Moon from local resources. We propose the monograin layer (MGL) solar cell technology, that could be used for the in-situ production of solar panels on the Moon. One of the most promising compounds, that can be used as an absorber material in a monograin layer solar cell is pyrite FeS2. There are considerable amounts of iron and sulphur in the lunar regolith. Conditions for the synthesis-growth of FeS2 monograin powders were found and are presented in this study. The synthesis-growth of FeS2 powder at 740 °C in potassium iodide for one week followed by slow cooling to 575 °C and rapid cooling to the room temperature, resulted in single phase pyrite monograin powder. Powder crystals had round shape and the median size of about 50 μm was appropriate for making monograin layers. The produced FeS2 MGLs were used as absorber layers in MGL solar cells with structure as graphite/FeS2/NiO/TCO and in FeS2/Pt Schottky diodes. Charge carrier concentration of 6.2 × 1016 cm−3 was determined from capacitance-voltage measurements of FeS2/NiO heterostructure and 2.5 × 1017cm−3 from FeS2/Pt Schottky diode.

First demonstration of hetero-epitaxial ε-Ga2O3 MOSFETs by MOCVD and a F-plasma surface doping

This letter reports on the demonstration of ε-phase gallium oxide (ε-Ga2O3) based metal-oxidesemiconductor field effect transistors (MOSFETs) for the first time. Phase-pure ε-Ga2O3 film was hetero-epitaxially grown on a sapphire substrate by metal organic chemical vapor deposition (MOCVD) using a two-step growth method. The high crystalline quality of the epilayer was confirmed with the X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM) investigations. Through a proper surface cleaning and CF4-plasma treatment process, fluorine (F) atoms were incorporated and acted as donors in the ε-Ga2O3 film, by which the sheet resistance (Rsh) of the epilayer was decreased by 105. Based on this F-plasma doped ε-Ga2O3 film, MOSFETs with a maximum output current density exceeding 3 mA/mm were successfully demonstrated. The doping profile extracted from the capacitance-voltage (C-V) measurement showed a significant carrier accumulation near the ε-Ga2O3 film surface with a peak concentration of 5 × 1017 cm−3 and an integrated carrier density of ∼6.4 × 1011 cm−2. The peak electron effective mobility (μeff) within the MOSFET channel was extracted to be as high as 19 cm2/Vs, indicating a great potential of ε-Ga2O3 based electronics for future high-speed and high-power applications.

Study of Vertical Capacitance in an n-Type 4H-SiC Stepped Thick-Oxide Trench MOS Structure

In this work, characteristics of trench sidewall capacitance were investigated in a 4H-SiC stepped thick-oxide (STO) trench metal–oxide–semiconductor (MOS) structure. Multigroup SiC trench MOS capacitor test patterns with different structures and geometric parameters were designed and fabricated. From the capacitance–voltage measurements, the characteristics of the described SiC STO trench MOS were calculated and analyzed, including the thicknesses of the oxide at different locations in trench, the position of the oxide step at trench sidewall, and the flat-band voltages as well as the oxide charge densities of MOS from the upper part and lower part of oxide step at trench sidewall. Results showed that the flat-band voltages of MOS from the upper part (10.2 V) and lower part (12.5 V) of trench sidewall step had pronounced positive shifts over the ideal flat-band voltage (0.36 V), indicating a massive negative charges in the sidewall oxide film. Meanwhile, the net oxide charge density of MOS from the lower part of sidewall step ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 0.92\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> ) was smaller than that from the upper part ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 2.41\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> ), which was likely attributed to the massive shallow states in the oxide and to the poor quality of the thick-oxide film grown via chemical vapor deposition technology. The present works are providing a convenient technology to monitor the trench MOS structure by measuring the capacitance during SiC trench MOSFETs fabrication.

Electrical properties of 2H-Si microwire grown by mixed-source hydride vapor phase epitaxy

Hexagonal 2H polytypes of Si (2H-Si) exhibit promising mechanical and optical properties owing to their crystal structures with quasi-direct bandgap characteristics. However, few studies have investigated the electrical properties of 2H-Si semiconductors. In this study, we used a hot-probe measurement to determine the doping type of 2H-Si microwires (MWs) prepared by hydride vapor-phase epitaxy (HVPE). It was found that the 2H-Si MWs had unintentional n-type characteristics. For the first time, a heterojunction PN diode with n-type 2H-Si MW and p-type Si (100) was fabricated. According to the current–voltage and capacitance–voltage measurements, the n-type doping concentration of the unintentionally doped 2H-Si MWs was 4.3–9.5 × 1015 cm−3 and the electron mobility was 260–580 cm2/V·s.

Bovine Serum Albumin-Based Thin-Film Capacitors for Flexible Electronic Applications

Metal–insulator–metal (MIM) thin-film capacitors having different dielectric layer thicknesses have been fabricated by forming bovine serum albumin (BSA) layers on electrically conductive and optically transparent indium tin oxide (ITO) coated polyethylene terephthalate (PET) substrates by using spin coating technique; the metal contacts at the top surface of BSA films have been deposited via thermal evaporation of gaseous phase aluminum. The capacitance-voltage (CV) measurements reveal the fact that the CV-characteristics of the BSA-based MIM capacitors show variable non-linearity with the change in the thickness of the insulating layer (BSA-layer). The experimentally measured CV-data are fitted with 2nd degree polynomial equations and it has been found that the quadratic voltage coefficient of capacitance (VCC) changes its sign from negative to positive as the thickness of the BSA-layer reduced below 2.0 µm. Finally, successful mechanical flexibility tests, as well as curvature tests have been carried out in order to confirm the possibility of using BSA-based MIM thin-film capacitors in flexible electronic applications in near future.

(Invited) Rare Earth Oxides on Wide Band Gap Semiconductors

Globally, most recent power electronics converter and device technology has been driven by the unprecedented demand seen within the automotive sector [1]. The latter demands power converters with near 100% energy efficiency, lightweight, compact and reliable. Wide band gap (WBG) semiconductor materials such as GaN and 4H-SiC have emerged as contenders to replace Si in many power electronics applications. Currently, GaN devices based on the high electron mobility transistor (HEMT) architecture are limited commercially to a maximum of 650 V [2,3]. GaN HEMTs have traditionally suffered from a poor thermal conductivity and the “current collapse” phenomenon, limiting their ability to operate within harsh environments. On the other hand, 4H-SiC has a few reliability issues that limit its ubiquitous application in the automotive sector [2]. Currently the GaN based Metal-Insulator-Semiconductor (MIS)-HEMT device is seen to demonstrate superior performance in power electronics applications over the Schottky gate counterpart, due to its inherently lower gate leakage current, together with the ability to provide larger forward gate voltage swing by engineering the threshold voltage between depletion and enhancement mode operation and also an improved gate-drain breakdown voltage. High band gap gate dielectric materials are preferable as they can provide higher tunnelling barriers for electrons and holes, which result in lower gate leakage current. Furthermore, high dielectric constant (high-k) material is also necessary for improved electrostatic control over the channel and improved on-current, which in-turn results in higher transconductance. In terms of SiC based devices, the use of SiO2 proves to be a bottleneck in exploiting full potential of SiC due to the low value of dielectric constant of SiO2 [4]. Since the oxide is subjected to an electric field that is ~2.5x the field in the semiconductor, the breakdown of SiO2 occurs first, and hence causes the breakdown of SiO2/4H-SiC based devices well below the critical electric field of SiC. This shortcoming led to the exploration of high-k dielectrics as gate stacks in 4H-SiC MIS based devices as well as for surface passivation. It is worth noting that SiO2 is the only dielectric commercially used for SiC devices largely due to the unavailability of a reliable high-k dielectric alternative. Most published results focus on use of Al2O3 and HfO2 films [5], however they have yet to become used mainstream in 4H-SiC devices.In this paper, two rare earth high-k oxides, Y2O3 and Sc2O3, both with dielectric constant >10, have been studied in terms of their suitability as gate dielectrics on GaN and 4H-SiC. The oxide films were prepared by radio frequency (RF) magnetron sputtering (Sc2O3) and ion gun sputtering (Y2O3). The substrates were cleaned with Kr ions with anode current of ~ 50 mA and accelerating voltage of 3 kV for 1-2 hours. Then metallic Y was sputtered using pressure of 1.5 x 10-5 mbar and current of 26 mA, which was followed by exposure to O2 to form Y2O3 films. Sc2O3 films were deposited using Moorfields nano-PVD (physical vapour deposition) equipment with circular Sc2O3 target of 99.99% purity using RF power of 60 W and a gas flow of 0.5 sccm for 3 nm film and 3 sccm for 40 nm film. The films were also deposited simultaneously on Si to be used as reference samples for variable angle spectroscopic ellipsometry (VASE) measurements to ascertain their thickness and optical properties. The X-ray photoelectron spectroscopy (XPS) was used to characterise comprehensively the oxide/semiconductor interface. The capacitance voltage measurements on MIS stacks were used to determine permittivity of deposited oxides. The complete band alignment of oxide/WBG semiconductor as well as comprehensive comparison to state of the art data will be presented and discussed in full paper. Acknowledgement. The UKIERI IND/CONT/G/17-18/18 and F.No.184-1/2018(IC) project funded by the British Council; UKRI GCRF GIAA award 2018/19 and EP/P510981/1, funded by the EPSRC, UK. References. [1] http://www.yole.fr/Compound_Semiconductor_Monitor_Q1.aspx. [2] Li et al., Materials 14, 5831 (2021); [3] Gonzalez et al. IEEE Trans. Ind. Electron. 67, 7375 (2020); [4] A. Siddiqui et al., J. Mater. Chem. C 9, 5055 (2021); [5] Bencherif et al., Appl. Phys. A 126, 854 (2020).

(Invited, Digital Presentation) Exploring the Potential and Limits of Gallium Oxide Electronics: In-Situ Dielectrics, Heterointegration and High-k Field Plates

The intrinsic properties of beta phase Gallium Oxide such as the high breakdown field strength makes it a very attractive material for next generation electronics. Rapid progress has been made over the last few years in pushing the performance of Gallium Oxide-based vertical Schottky diodes and lateral field effect transistors and impressive figure of merit has been reported. However, the device performance is farther from the expected performance based on intrinsic properties. Exploration of the intrinsic potential is rather limited by several factors such as the quality of dielectrics and dielectric/semiconductor interfaces, electric field management challenges due to the lack of p-type material, to name a few. In this work, we will highlight a few approaches to tackle some of these challenges.(1) In-situ dielectrics: High quality dielectric-semiconductor interfaces are critical for reliable high-performance transistors. We report in situ metal–organic chemical vapor deposition of Al2O3 on β-Ga2O3 as a potentially better alternative to the most commonly used atomic layer deposition (ALD) [1]. The growth of Al2O3 is performed in the same reactor as Ga2O3 using trimethylaluminum and O2 as precursors without breaking the vacuum at a growth temperature of 600 °C. The fast and slow near interface traps at the Al2O3/β-Ga2O3 interface are identified and quantified using stressed capacitance–voltage (CV) measurements on metal oxide semiconductor capacitor (MOSCAP) structures. The density of shallow and deep level initially filled traps (Dit) are measured using ultraviolet-assisted CV technique. The average Dit for the MOSCAP is determined to be 6.4 × 1011 cm−2eV−1. The conduction band offset of the Al2O3/ Ga2O3 interface is also determined from CV measurements and found out to be 1.7 eV which is in close agreement with the existing literature reports of ALD Al2O3/Ga2O3 interface. The current–voltage characteristics are also analyzed and the average breakdown field is extracted to be approximately 5.8 MV cm−1.(2) Field management using High-K field Plate: We report a vertical (001) β-Ga2O3 field-plated (FP) Schottky barrier diode (SBD) with a novel extreme permittivity dielectric field oxide [2] . A thin drift layer of 1.7μm was used to enable a punch-through (PT) field profile and very low differential specific on-resistance (Ron-sp) of 0.32 mΩ-cm2. The extreme permittivity field plate oxide facilitated the lateral spread of the electric field profile beyond the field plate edge and enabled a breakdown voltage (Vbr) of 687 V. The edge termination efficiency increases from 13.2%for non-field plated structure to 61% for high permittivity field plate structure. The high permittivity field plated SBD demonstrated a record high Baliga's figure of merit (BFOM) of 1.47 GW/cm2 showing the potential of Ga2O3 power devices for multi-kilovolt class applications.(3) p-type III-nitride/Ga2O3 integration for field management: This work presents the simulation and analysis of a novel Ga 2 O 3 vertical Schottky diode with three different guard ring (GR) configurations to reduce the peak electric field at the metal edges [3]. Highly doped p-type GaN, p-type nonpolar AlGaN, and polarization-doped graded p-AlGaN are simulated and analyzed as the GR material, which forms a heterojunction with the Ga 2 O 3 drift layer. GR with nonpolar graded p-AlGaN with a bandgap larger than Ga 2 O 3 is found to show the best performance in terms of screening the electric field at the metal edges. The proposed GR configuration is also compared with a reported Ga 2 O 3 Schottky diode with no GR and a structure with high-resistive nitrogen-doped GR. The optimized design is predicted to have a breakdown voltage as high as 6.2 kV and a specific ON-resistance of 3.55 mΩ-cm 2, which leads to an excellent power figure of merit of 10.8 GW/cm 2.The approaches discussed here can offer a pathway towards understanding the true potential and limitations of Gallium Oxide for extreme electric field devices. We acknowledge funding support from NSF (DMR-1931652) and the AFOSR MURI program (FA9550-18-1-0507).

(Invited, Digital Presentation) High-κ Gate Oxide Integration and Ohmic Contact Development for AlGaN/GaN MISHEMTs

GaN based devices are one of the main candidates for current power electronics and RF applications [1,2]. For optimizing device performance, a detailed understanding of the defects contained in the material and the passivation capability of dielectric layers, i.e., the interfacial defect states formed, is mandatory. Here, we will focus on the surface defect passivation and gate leakage current reduction by introducing thin dielectric films as gate insulator in a so-called MISHEMT (metal insulator semiconductor high electron mobility transistors) device using different materials. The impact of a fully amorphous dielectric (Al2O3), which was kept amorphous by the integration of a low thermal budget ohmic contact [3], was compared to an epitaxial dielectric film (GdScO3) [4]. Due to the band alignment and the high dielectric constant of GdScO3, the spillover effect as it was seen for Al2O3 [5] has been suppressed and a reduction of threshold voltage shift due to the additional capacitance by the dielectric layer has been achieved. In addition, AlTiOx films were investigated as gate dielectrics [6]. To avoid further deterioration of the dielectric layer by the ohmic contact formation anneal, a gate last integration scheme was carried out using Ti based gold free ohmic source and drain contacts [7]. By varying the Al content, the band alignment between the underlying GaN capping layer to the thin film dielectric was controlled. By this means and additional charge engineering in the dielectric layer, a gate leakage reduction with limited threshold voltage increase has been realized. All dielectric layers have been electrically characterized in detail. Interface trap densities were measured by photo-assisted capacitance voltage measurements and an in-depth comparison of the dielectric layers and their impact on the device performance will be given.[1] Yole Developpement, RF GaN Market: Applications, Players, Technology and Substrates 2019, Market & Technology Report, (2019)[2] T. Kimoto, Jpn. J. Appl. Phys. 54, 40103 (2015).[3] Schmid, A.; Schröter, Ch.; Otto, R.; Schuster, M.; Klemm, V.; Rafaja, D.; Heitmann, J., Appl. Phys. Lett. 106, 053509 (2015)[4] Seidel, S., Schmid, A., Miersch, C., Schubert, J., Heitmann, J. Appl. Phys. Lett., 118(5), 052902 (2021)[5] P. Lagger, P. Steinschifter, M. Reiner, M. Stadtmüller, G. Denifl, A. Naumann, J. Müller, L. Wilde, J. Sundqvist, D. Pogany, C. Ostermaier, Appl. Phys. Lett. 105, 033412 (2014)[6] N Siebdrath, S. Seidel, A. Schmid, J. Heitmann, Mikro-Nano-Integration; 8th GMM-Workshop, 2020, pp. 1-3.[7] Garbe, V.; Schmid, A.; Seidel, S.; Abendroth, B; Stöcker, H.; Doering P.; Meyer, D.C.; Heitmann, J., Phys. Stat. Sol. (B), 2100312 (2021)