Capacitance-to-digital Converter Research Articles

Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation

In this work, a capacitance-to-digital converter (CDC) suitable for direct energy harvesting is introduced. The nW peak power and the ability to operate at any supply voltage in the 0.3-1.8 V range allow complete suppression of any intermediate DC-DC conversion, and hence direct supply provision from the harvester, as demonstrated with a mm-scale solar cell. The proposed CDC architecture eliminates the need for any additional support circuitry, preserving true nW-power operation, and reducing design and integration effort. In detail, the architecture is based on a pair of double-swappable oscillators, and avoids the need for any voltage/current/frequency reference circuit in the oscillator mismatch compensation. The digital and differential nature of the architecture counteracts the effect of process/voltage/temperature variations. A load-agnostic one-time self-calibration scheme compensates mismatch, and can be run from boot to run stage of the chip lifecycle. The proposed self-calibration scheme suppresses any trimming or testing time for low-cost systems, and avoids any input capacitance disconnection requirement. A 180-nm testchip shows 7-bit ENOB down to 0.3 V and 1.37-nW total power, when powered by a 1-mm2 indoor solar cell down to 10 lux (i.e., late twilight).

An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter

This article presents an energy-efficient noise-shaping successive-approximation register (SAR) capacitance-to-digital converter (CDC) for high-resolution capacitive sensor applications. Based on a 12-bit SAR architecture, quantization noise is shaped by the first-order FIR-IIR loop filter. The proposed loop filter comprises dynamic amplifiers (DAs), and it is designed to be insensitive to DA gains’ variations. Under process, voltage, and temperature (PVT) variations, the loop filter is stable and retains in-band noise suppression ability without the gain calibration. The CDC is implemented in a differential configuration for a single-sensor measurement with an energy-efficient capacitive digital-to-analog converter (CDAC) switching method. It does not require any replica or dual capacitor sensor for differential operation. In the proposed CDC, a dynamic comparator with a common-mode (CM) rejection is proposed to compensate for the instability because the parasitic capacitance causes CM voltage deviation of the CDAC and loop instability. The proposed CDC is fabricated in a 180-nm CMOS technology with an active area of 0.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It dissipates 63.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> at a sampling frequency of 320 kHz. Given that all circuits operate dynamically, the sampling frequency is scalable from 3.2 to 320 kHz. The prototype CDC achieves an 88.9-dB signal-to-noise ratio (SNR) and a figure-of-merit of 139 fJ/conversion-step.

A Capacitance to Digital Converter Using Continuous Time ΔΣ Modulator for Microphone-Based Auscultation

This paper presents a novel Capacitance to Digital Converter (CDC) for ultra-low power microphone-based auscultation. The proposed CDC utilizes a continuous-time Capacitance to Voltage Converter (CVC) inside a delta-sigma (ΔΣ) modulator to perform the Delta operation. The multi-bit feedback in the embedded CVC with a capacitive DAC reduces the voltage swing at its output, which permits a larger capacitive signal gain and relaxes the noise requirements. The multi-bit feedback also allows a larger signal swing at the CVC output, and improves the dynamic range. The proposed CDC was fabricated in 0.18 μm CMOS technology and was measured with a commercial capacitive sensor. Measurement results demonstrate that the proposed CDC consumes only 6.3 nJ while achieving 13-bit resolution. This corresponds to a FoM of 0.84 pJ/conversion-step.

A high-precision time-to-digital converter applied to CDC

This paper presents a high-precision CMOS time-to-digital converter (TDC) applied to a capacitance-to-digital converter (CDC). The time-to-digital converter in the capacitance-to-digital converter is used to measure the time interval between the charging time of the capacitor under test and the charging time of the internal reference capacitor. The time resolution of the TDC directly determines the capacitance resolution of the CDC. In order to improve the measurement resolution of TDC, a TDC structure based on phase-locked loop (PLL) is proposed. This paper first gives a capacitance-to-digital converter scheme, and then introduces the time-to-digital converter used in the scheme. The frequency multiplication technology of the phase-locked loop optimizes the integral nonlinearity (INL) of the interpolator and greatly improves the interpolation of the interpolation ratio. The TDC was realized in a 0.13-μm CMOS process, and the measurable time interval is 21.14μs. When the external reference clock is 200MHz, the resolution is 40.3ps and only 31 delay units are needed.

Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy

We report a scanning photocapacitance microscopy technique for the localization of open electrical defects in hybrid bonding wafer-to-wafer (W2W) interconnect structures for 3-D system integration. Whereas the well-known optical beam induced resistance change (OBIRCH) method is effective for the localization of resistive opens and shorts, it cannot be applied on full electrical opens. Our approach uses a focused laser beam to stimulate the photocapacitance of the W2W interconnect, and by measuring its response, we can verify the electrical continuity of the structure. We show how illuminating the interconnects with the light of a suitable wavelength leads to an increase of the depletion capacitance due to carrier generation in the silicon substrate. Our measurement instrument uses a commercially available sigma-delta ( $\Sigma -\Delta$ ) capacitance-to-digital converter (CDC) chip with a capacitance sensing resolution down to 4 aF. We demonstrate this methodology on large open-failed W2W interconnect chains with sub-micrometer hybrid-bonded interconnect pad dimensions and confirm our results by optical and transmission electron microscopy (TEM).

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter

This article presents an incremental two-step capacitance-to-digital converter (CDC) with a time-domain $\Delta \Sigma $ modulator (TD $\Delta \Sigma \text{M}$ ). Unlike the classic two-step CDCs, this work replaces the operational transconductance amplifier (OTA)-based active- RC integrator by a voltage-controlled oscillator (VCO)-based integrator, which is mostly digital and low-power. Featuring the infinite dc gain and intrinsic quantization in phase domain, this TD $\Delta \Sigma \text{M}$ enables a CDC design achieving 76-dB SNDR while requiring only a first-order loop, and a low oversampling ratio (OSR) of 15. Fabricated in 40-nm CMOS technology, the prototype CDC achieves a resolution of 0.29 fF while dissipating only 0.083 nJ/conversion, which improves the energy efficiency by over two times comparing to the similar performance designs.

A Compact Fully Dynamic Capacitance-to-Digital Converter With Energy-Efficient Charge Reuse

An ultra-low-power fully dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed. The CDC includes a capacitive bridge as the sensing frontend and an asynchronous successive approximation register ADC for signal digitization. Passive charge sharing between the frontend and ADC is used to enable a fully dynamic operation. Instead of resetting the capacitive bridge (with large sensing and reference capacitors) for each measurement, the charge is maintained and reused over many measurements to save energy. A power-gating technique is employed to reduce the stand-by power. As a result, a figure of merit as low as 4.3 fJ/conv-step is achieved for the CDC, which is >3× better than the state of the art. Furthermore, it supports an inherent scaling of power versus speed with a minimum power of only 44 pW and a compact chip area of 6440 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 117-dB In-Band CMRR 98.5-dB SNR Capacitance-to-Digital Converter for Sub-nm Displacement Sensing With an Electrically Floating Target

This article describes a high-performance capacitance-to-digital converter (CDC) for sub-nm displacement sensing with an electrically floating target. Intended to be integrated into a displacement sensor probe, the CDC consumes only $560~\mu \text{W}$ . It achieves 98.5-dB SNR in a 1-ms conversion time. With a sensing O 8-mm probe and a 25- ${\mu }\text{m}$ stand-off distance from the target, it achieves 0.18-nm resolution. Moreover, it offers an in-band common-mode rejection ratio (CMRR) higher than 117 dB, providing decent electric field interference immunity.

An 8.2-$\mu$ W 0.14-mm2 16-Channel CDMA-Like Capacitance-to-Digital Converter

This article presents a multi-channel capacitance-to-digital converter (CDC) circuits using the continuous-time Walsh coding multiplexing. The proposed circuits modulate the input capacitive sensors with orthogonal codes, enable simultaneous read-in of 16 capacitive sensors, and provide the combined 16 digitized outputs in a single conversion. By correlating 16 successive digitized outputs with the corresponding orthogonal codes in post-processing, the 16 capacitive channels can then be demodulated separately. The proposed continuous-time Walsh coding modulation preserves temporal information with minimum circuitry duplication and bandwidth requirement. This chip is fabricated in 130-nm CMOS technology and occupies an area of 0.14 mm2. With a reference clock of 4 MHz, the proposed multi-channel CDC achieves 11.4 ENOB with an average conversion time of 482 $\mu \text{s}$ . It consumes 0.51 $\mu \text{W}$ /channel and achieves an FoM of 87 fJ/conversion step.

A CMOS VEGF Sensor for Cancer Diagnosis Using a Peptide Aptamer-Based Functionalized Microneedle.

This paper presents the first CMOS Vascular Endothelial Growth Factor (VEGF) sensor for cancer diagnosis directly from human blood. The sensor incorporates a peptide aptamer-based microneedle that allows the detection of electrochemical reactions with VEGF. This results in a capacitance change between the microneedles and then reads out by a two-step capacitance-to-digital converter (CDC). The proposed two-step CDC consists of a coarse 5b slope ADC and a fine 14b continuous-time delta-sigma modulator (CTDSM). During slow peptide-binding, the slope ADC performs a coarse conversion and the results are used to adjust the current level of the stimulator. After settling of the peptide-binding, based on an adjusted stimulation current, the CTDSM measures the small capacitance changes of the sensor. The prototype chip is fabricated in a 65-nm CMOS process, occupying a 0.87mm 2 active area. The power consumption is 270muW. Thanks to the two-step approach, this work achieves a wide dynamic range of 18.3b, covering a large sensor-to-sensor variation. It also achieves a peak resolution of 13.7b, while maintaining errors in 1 to 100nF baseline capacitance. The overall sensor system successfully detects the VEGF in both phosphate-buffered saline (PBS) and human blood serum. Without the use of precision instruments, this work achieves a resolution of 15 fM [Formula: see text] in range of 0.1 to 1000 pM and denotes the clear VEGF selectivity at 40× in PBS and 5× in the blood serum compared to other proteins (IgG, Con A, and cholera toxin).

A 2.92-$\mu$ W Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-$\mu$ m CMOS

This paper presents a sensor front end for air pressure sensor, relative humidity (RH) sensor, and accelerometer in a standard CMOS process, equipped with a wide input range high-resolution capacitance-to-digital converter (CDC). For air pressure and RH, interdigitated top metals in air and polyimide are exploited, respectively, which exhibit the change in dielectric constant. For acceleration, separation among three bondwires is exploited. These sensing transducers induce capacitance change that is quantized by a CDC based on a dual-quantization architecture that employs a single-bit first-order $\Delta \Sigma $ modulator and a 7-bit SAR analog-to-digital converter (ADC). Implemented in 0.18- $\mu \text{m}$ CMOS, the air pressure sensor, RH sensor, and accelerometer achieve a noise floor of 0.14 psi/ $\sqrt {\textrm {Hz}}$ , 0.001 %RH/ $\sqrt {\textrm {Hz}}$ , and 4.6 mg/ $\sqrt {\textrm {Hz}}$ , respectively. The CDC achieves a resolution of 864 aF (minimum resolution of 116 aF) when the sensing capacitance is 10 pF and consumes $3~\mu \text{W}$ from 1.1-V supply.

An Extended Study on an Interference-Insensitive Switched Capacitor CDC

A new Switched Capacitor (SC) Capacitance-to-Digital Converter (CDC) is presented in this paper. Its output exhibits a high-level of insensitivity to interference, by virtue of the conversion mechanism itself. The proposed scheme is a combination of an SC relaxation oscillator and an integrating type analog-to-digital converter (ADC). Its conversion time is independent of the measurand and hence can be set, such that it is an integral multiple of the interference period, unlike in a dual-slope ADC where the de-integration time is a function of the measurand. The final output is proportional to the number of transitions in the oscillator output, which is directly proportional to the value of the sensor capacitance and has negligible sensitivity to the presence of the interference signal. The proposed scheme has been realized and tested as a hardware prototype unit. The non-linearity of the scheme was found to be 0.4%, and the resolution, in terms of the effective number of bits (ENOB), was 11.13, when tested, with sensor capacitance varied from 10 to 32.5 pF. The studies conducted to evaluate the effect of capacitively coupled interference to the sensitive node on the CDC showed that it is negligible for a wide range of magnitude.

A Large Measurable Range Capacitance-to-Digital Converter for Smart Humidity Sensors.

This study aims to propose a capacitance-to-digital converter (CDC) based on a third-order cascade of integrators with a feed-forward (CIFF) incremental sigma-delta modulator for smart humidity sensor application. Disguised zoom-in technology was proposed to enlarge the measurable range of the CDC. The input range of the CDC was 0–388 pF. The proposed CDC was realized using 0.18 μm complementary metal-oxide-semiconductor technology. Results show that the CDC performs a 13-bit capacitance-to-digital conversion in 0.8 ms. The analog system consumes 169.7 μA from a 1.8 V supply, which corresponds to a figure of merit (FOM) of 3.0 nJ/step. The proposed CDC was combined with a HS1101 humidity sensor to demonstrate its incorporation in an overall system design. The resolution was 0.7% relative humidity (RH) over a range of 30%–90% RH.

A 0.1-nW–1-$\mu$ W Energy-Efficient All-Dynamic Versatile Capacitance-to-Digital Converter

A versatile, low-power, and energy-efficient capacitance-to-digital converter (CDC) for Internet-of-Things (IoT) is presented, based on an all-dynamic architecture with adaptable speed, resolution, and range. The proposed CDC includes a single-armed capacitive bridge and a differential switched-capacitor 10-b asynchronous successive approximation register (SAR) analog-to-digital-converter (ADC). The bridge output is directly sampled by the ADC through fully passive correlated-double-sampling (CDS) approach, which enables a fully dynamic operation. The design is fabricated in a 65-nm CMOS technology. Thanks to the dynamic nature of the CDC, sampling rates from 1 S/s up to 100 kS/s are supported and capacitances from 1.23 to 24.59 pF can be digitized, while the power scales inherently from 0.1 nW to $1~\mu \text{W}$ . Optionally, the range can be further extended to >100 pF, and oversampling can be used to enhance resolution. This makes the design versatile to efficiently deal with a variety of sensors having different speed and resolution requirements and different capacitance values. The 0.1 nW lowest absolute power is $> 20\times $ smaller than the prior art, and the figure of merit (FoM) from 18 to 59 fJ/conv-step is also the lowest among prior designs. To provide application examples, this chip is further verified with a microelectromechanical (MEMS) pressure sensor and a MEMS accelerometer. It can measure environmental pressure consuming only 0.8 nW at a speed of 100 S/s, and measure acceleration using 1.4 nW at a speed of 200 S/s.

A 15-nW per Sensor Interference-Immune Readout IC for Capacitive Touch Sensors

This paper presents a readout IC that uses an asynchronous capacitance-to-digital-converter (CDC) to digitize the capacitance of a touch sensor. A power-efficient tracking algorithm ensures that the CDC consumes negligible power consumption in the absence of touch events. To facilitate its use in wake-on-touch applications, the CDC can be periodically triggered by a co-integrated ultra-low-power relaxation oscillator. At a 38-Hz scan rate, the readout IC consumes 15 nW per touch sensor, which is the lowest reported to date.

A Precision, Energy-Efficient, Oversampling, Noise-Shaping Differential SAR Capacitance-to-Digital Converter

This paper introduces an oversampling, noise-shaping differential successive-approximation-register capacitance-to-digital converter (CDC) architecture for interfacing capacitive sensors. The proposed energy-efficient CDC achieves high-precision capacitive resolution by employing oversampling and noise shaping. The switched-capacitor (SC) integrator is inserted between the comparator and the charge-redistribution digital-to-analog converter to implement noise shaping and to make the interface circuit insensitive to parasitic capacitances. An inverter-based operational transconductance amplifier with a common-mode feedback circuit is employed to implement the SC integrator with subthreshold biasing for low voltage and low power. The ring-oscillator-based comparator is implemented to achieve high energy efficiency. The test chip is fabricated in a 0.18- $\mu \text{m}$ CMOS technology. The proposed CDC experimentally achieves 150 aF absolute resolution and 12.74-ENOB with an oversampling ratio of 15 and a sampling clock of 18.51 kHz. The fabricated prototype dissipates 1.2 and 0.39 $\mu \text{W}$ from analog and digital supplies, respectively, with an energy efficiency figure-of-merit of 187 fJ/conversion step.

A Low-Power Delta-Sigma Capacitance-to-Digital Converter for Capacitive Sensors

This paper proposes a low-power delta-sigma capacitance-to-digital converter (CDC) for a capacitive sensor. The input of the capacitive sensor employs a zoomed-in technique with the offset capacitor to extend the input capacitance range. The proposed CDC uses a third-order switched capacitor delta-sigma modulator to provide a digital output, based on a cascade of integrators with a feed forward (CIFF) structure. The current-starved operational transconductance amplifiers (OTAs) are applied in the delta-sigma modulator's first integrator to improve the current efficiency and reduce the power consumption. An auto-zeroing technique is used in the OTAs to reduce their offset and noise. The circuit was implemented in a 0.18-μm CMOS technology and occupies an area of 0.496 mm 2 . The measurable capacitance range of the CDC can be varied from 0 to 8 pF. In a measurement time of 0.8 ms, the delta-sigma CDC achieved a 12.7 effective number of bits while consuming 18.6-μA current from a 2-V supply voltage.

Three-Dimensional Model and Evaluation of an Insulin Injection Pen for Precise Dose Capacitive Measurement

A fully parameterized three-dimensional model with specific dimensions has been developed in ANSYS for an insulin injection pen used by diabetic persons. The insulin injection pen has a smart pen cap which hosts four electrodes used for the smart pen cap electrode capacitive measurement. The addition of the smart cap on top of the insulin injection pens is novel and essential for storing and transmitting injection dose and time data to help patients successfully manage their treatment. The simulations can be used to decide the number and exact shape of the electrodes, as well as to evaluate different misalignment and asymmetries of the electrode fabrication process or of the liquid misplacement. Using Maxwell 3D tool the electrode capacitance was numerically evaluated, which is necessary for sensing and ultimately for insulin dose precise detection. Experimental results have been provided using an AD7746 high-resolution sigma-delta capacitance-to-digital converter (CDC). Simulation and experimental results for the sense electrode capacitance, in the case of both smart pen cap and complete insulin injection pen + smart pen cap system, have been obtained, using two different configurations (1 vs 3 and 2 vs 2 respectively). Smart pen cap electrode capacitance variation for different insulin fill states has been numerically evaluated and the linear behavior of the injection has been proven.

A Robust Switched-Capacitor CDC

A capacitance-to-digital converter (CDC) designed to possess negligible sensitivity to non-ideal circuit parameters is presented in this paper. The scheme is based on switched capacitor integrating technique and the conversion process is such that the final output is fundamentally insensitive to leakage resistance and stray capacitance of the sensor, offset voltage and bias current of the opamp, delay, offset voltage, and bias current of the comparator, leakage current, delay, and charge injection of the switches employed, and so on. Such a characteristic is highly useful for precision measurement. The proposed CDC achieves it without any special compensating circuits, unlike some of the existing CDCs that partially meet the above feature. The performance of the CDC has been experimentally evaluated. Results show high insensitivity to the non-ideal circuit parameters. In addition, the worst case non-linearity error of the prototype CDC was found to be less than 0.1%, when tested for a range of 10 to 400 pF.

CMOS based capacitance to digital converter circuit for MEMS sensor

Most of the MEMS cantilever based system required costly instruments for characterization, processing and also has large experimental setups which led to non-portable device. So there is a need of low cost, highly sensitive, high speed and portable digital system. The proposed Capacitance to Digital Converter (CDC) interfacing circuit converts capacitance to digital domain which can be easily processed. Recent demand microcantilever deflection is part per trillion ranges which change the capacitance in 1-10 femto farad (fF) range. The entire CDC circuit is designed using CMOS 250nm technology. Design of CDC circuit consists of a D-latch and two oscillators, namely Sensor controlled oscillator (SCO) and digitally controlled oscillator (DCO). The D-latch is designed using transmission gate based MUX for power optimization. A CDC design of 7-stage, 9-stage and 11-stage tested for 1-18 fF and simulated using mentor graphics Eldo tool with parasitic. Since the proposed design does not use resistance component, the total power dissipation is reduced to 2.3621 mW for CDC designed using 9-stage SCO and DCO.