Capacitance-time Measurements Research Articles

Photodiode performance and infrared light sensing capabilities of quaternary Cu2ZnSnS4 chalcogenide

In this study, quaternary Cu2ZnSnS4 chalcogenide nanocrystal compound prepared by hydrothermal method was coated on Si with the help of spin coating technique to be used as the interfacial layer. SEM and EDX analyzes were performed to investigate the morphological and structural properties of the coated film. In order to determine the optical properties, IR and UV–Vis measurements were made and it was determined that the absorption properties of the material were good in the visible and infrared region, and the optical band gap value was found to be 1.49 eV. In addition, photoelectrical measurements (current-voltage and photo-transient) were performed and evaluated under both solar and infrared lights. As a result of these measurements, it was determined that the photoresponse value gave better results in the measurements made under sunlight. The calculated ideality factor (barrier height) values in the light of the data obtained were found to be 5.087 (0.456 eV), 6.422 (0.449 eV) and 7.789 (0.443 eV) under dark, solar light and infrared light conditions, respectively. As seen from the results, the ideality factor value in the measurements made under solar light is lower than the measurements made under infrared, but the barrier height value is higher. In addition, capacitance-time measurements were performed depending on the light intensity and the produced device showed photocapacitive properties for both light sources. In addition to these measurements, the capacitive properties of the device were also analyzed by taking capacitance and conductivity measurements as a function of frequency and voltage. These measurements revealed that the capacitance and conductivity characteristics of the device are strongly dependent on voltage and frequency. The results of the performed experimental studies confirm that the produced Al/Cu2ZnSnS4/p-Si device is highly sensitive to infrared and sunlight to which it is exposed, and also shows that the produced device configuration can be used in optoelectronic applications.

Dielectric relaxation and AC conductivity behaviour of Se80Te15Bi5/PVA nanocomposite film

Abstract An analytical approach has been applied to investigate the dielectric properties and ac conductivity behaviour of a new polymer nanocomposite (PNC) of polyvinyl alcohol (PVA) doped with nanocolloids of Se80Te15Bi5 glass over a frequency range of 100 Hz–5 MHz for temperatures ranging from 298 K to 448 K. An increase in dielectric constant and relaxation time for PNC has been seen as compared to pure PVA. The Cole-Cole model of relaxation shows good agreement with experimental data. The ac conductivity (σac) behaviour has been found to follow the Jonscher's power law Aωs. Prevailing mechanism of conduction has been confirmed to be correlated barrier hopping (CBH) type. The synthesized PNC has been used as an active layer in the fabrication of a memory device. Electrical characterization of the device has been done by current-voltage (I–V) and capacitance-voltage (C–V) measurements. The switching between high conductive (ON) and low conductive (OFF) states of the device may be attributed to charge trapping and de-trapping in Se80Te15Bi5 nanocolloids. The retention characteristic of the device, determined by capacitance-time (C-t) measurements indicates its good reliability and stability.

Reversible capacitance changes in the MOS capacitor with an ITO/CeO2/p-Si structure

A reversible capacitance changes with respect to the polarity of applied voltage is demonstrated in a MOS (metal-oxide-semiconductor) capacitor consisting of a high-k CeO2 and oxygen-reactive indium-tin-oxide (ITO) electrode on p-Si substrate, i.e., an ITO/CeO2/p-Si structure. The capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements exhibit consistently that the accumulation capacitance is gradually increased upon repeatedly applying negative voltage to the ITO, while the depletion capacitance is reversibly decreased upon applying positive voltage. Particularly, the capacitance change is observed even at a low voltage of ±0.5 V from the device with 40-nm-thick CeO2 layer. The capacitance change is further enhanced as increasing measurement temperature from 25 to 100 °C, implying that the capacitance change is associated with the thermally activated process under the applied voltage. In addition, the resistance of ITO gate electrode is found to decrease upon applying negative voltage, but it is increased reversibly upon applying positive voltage. The reversible capacitance changes in the MOS capacitor with oxygen-reactive ITO gate electrode are explained with voltage-driven oxygen ion migration between ITO and CeO2 layers that can alter the CeO2 dielectric permittivity and induce the gate depletion in the ITO. These reversible capacitance changes have a potential to be employed to modulate the MOSFET (MOS field-effect-transistor) properties such as on-state current, threshold voltage, and transconductance.

A novel quaternary chalcogenide KBiCu2S3 based linear-dynamic-range optoelectronic device for optic communications systems

A solar light optoelectronic device was fabricated using KBiCu2S3 and p-type silicon semiconductor. Electrical behavior of the optoelectronic device was characterized under solar light using current-electric field and phototransient current and capacitance-time measurements. Under solar light, the current at reverse bias region varies while the forward current did not change. The photoresponse ratio of photocurrent to dark current under 1000 W/m2 was determined to be 79. This ratio suggests that the KBiCu2S3/p-type silicon device is a photodevice with its photovoltaic behavior. The junction interface behavior of the device was analyzed by capacitance-electric field (CV) characteristics. The CV behavior of the device was corrected by the series resistance. KBiCu2S3/p-type silicon optoelectronic device. The device is called as FYTRONIX optoelectronic device as it works both photodevice and photocapacitor modes. The FYTRONIX optoelectronic device can be used as a optoelectronic device in optic communication system applications.

Multi-layered metal nanocrystals in a sol-gel spin-on-glass matrix for flash memory applications

A simple and low-cost process of embedding metal nanocrystals as charge storage centers within a dielectric is demonstrated to address leakage issues associated with the scaling of the tunnelling oxide in flash memories. Metal nanocrystals with high work functions (nickel, platinum and palladium) were prepared as embedded species in methyl siloxane spin-on-glass (SOG) films on silicon substrates. Sub-10 nm-sized, well-isolated, uniformly distributed, multi-layered nanocrystals with high particle densities (1011–1012 cm−2) were formed in the films by thermal curing of the spin-coated SOG films containing the metal precursors. Capacitance-Voltage measurements performed on metal-insulator-semiconductor capacitors with the SOG films show that the presence of metal nanocrystals enhanced the memory window of the films to 2.32 V at low operating voltages of ±5 V. These SOG films demonstrated the ability to store both holes and electrons. Capacitance-time measurements show good charge retention of more than 75% after 104 s of discharging. This work demonstrates the applicability of the low-cost in-situ sol-gel preparation in contrast to conventional methods that involve multiple and expensive processing steps.

Hierarchically built gold nanoparticle supercluster arrays as charge storage centers for enhancing the performance of flash memory devices.

Flash memory devices with high-performance levels exhibiting high charge storage capacity, good charge retention, and high write/erase speeds with lower operating voltages are widely in demand. In this direction, we demonstrate hierarchical self-assembly of gold nanoparticles based on block copolymer templates as a promising route to engineer nanoparticle assemblies with high nanoparticle densities for application in nanocrystal flash memories. The hierarchical self-assembly process allows systematic multiplication of nanoparticle densities with minimal increase in footprint, thereby increasing the charge storage density without an increase in operating voltage. The protocol involves creation of a parent template composed of gold nanoclusters that guides the self-assembly of diblock copolymer reverse micelles which in turn directs electrostatic assembly of gold nanoparticles resulting in a three-level hierarchical system. Capacitance-voltage (C-V) measurements of the hierarchical nanopatterns with a metal-insulator-semiconductor capacitor configuration reveal promising enhancement in memory window as compared to nonhierarchical nanoparticle controls. Capacitance-time (C-t) measurements show that over half the stored charges were retained when extrapolated to 10 years. The fabrication route can be readily extended to programmed density multiplication of features made of other potential charge storage materials such as platinum, palladium, or hybrid metal/metal oxides for next generation, solution-processable flash memory devices.

Writing and erasing mechanisms of stable nonvolatile memory devices based on SnO2 nanoparticle/polystyrene nanocomposites.

X-ray photoelectron spectroscopy spectra and transmission electron microscopy images showed that SnO2 nanoparticles were randomly distributed in the polystyrene (PS) layer. Capacitance-voltage (C-V) measurements on the Al/SnO, nanoparticles embedded in PS layer/p-Si devices at 300 K showed a clockwise hysteresis with a large flatband voltage shift due to the existence of SnO2 nanoparticles. Capacitance-time measurements showed that the devices exhibited excellent memory retention characteristics at ambient conditions. The writing and the erasing mechanisms for the Al/SnO, nanoparticles embedded in PS layer/p-Si devices are described on the basis of the C-V results and energy band diagrams.

Multilevel charging and discharging mechanisms of nonvolatile memory devices based on nanocomposites consisting of monolayered Au nanoparticles embedded in a polystyrene layer

Capacitance-voltage (C-V) curves for Al/Au nanoparticles embedded in a polystyrene (PS) layer/p-Si devices at 300 K showed a metal-insulator-semiconductor behavior with flat-band voltage shifts of the C-V curves due to the existence of charge trapping. Memory windows between 2.6 and 9.9 V were observed at different sweep voltages, indicative of multilevel behavior. Capacitance-time measurements demonstrated that the charge-trapping capability of Au nanoparticles embedded in a PS layer was maintained for retention times larger than 1 × 104 s without significant degradation. The multilevel charging and discharging mechanisms of the memory devices are described on the basis of the experimental results.

The Charge Storage of Doubly Stacked Nanocrystalline-Si based Metal Insulator Semiconductor Memory Structure

Doubly stacked nanocrystalline-Si (nc-Si) based metal insulator semiconductor memory structure was fabricated by plasma enhanced chemical vapor deposition. Capacitance-Voltage (C-V) and capacitance-time (C-t) measurements were used to investigate electron tunnel, storage and discharging characteristic. The C-V results show that the flatband voltage increases at first, then decreases and finally increases, exhibiting a clear deep at gate voltage of 9 V. The de-creasing of flatband voltage at moderate programming bias is attributed to the transfer of electrons from the lower nc-Si layer to the upper nc-Si layer. The C-t measurement results show that the charges transfer in the structure strongly de-pends on the hold time and the flatband voltage decreases markedly with increasing the hold time.

Electrical characteristics and operating mechanisms of nonvolatile memory devices fabricated utilizing core-shell CuInS2-ZnS quantum dots embedded in a poly(methyl methacrylate) layer

Nonvolatile memory devices were fabricated with core-shell CuInS2-ZnS quantum dots (QDs) embedded in poly(methyl methacrylate) (PMMA). Capacitance-voltage (C-V) measurements at 300 K on the Al/CuInS2-ZnS QDs embedded in PMMA layer/p-Si device showed capacitance hysteresis behaviors with a flatband voltage shift. The memory window of the device increased with increasing applied sweep voltage and saturated at high electric fields due to the current leakage. Capacitance-time measurements showed that the retention time was larger than 1 × 105 s that was more than 10 years. The operating mechanisms for the devices are described on the basis of the C-V curves.

Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al2O3 were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD) techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.

Investigation of Moisture Uptake in Low-$\kappa$ Dielectric Materials

The influence of moisture on the electrical properties of PECVD SiCOH and a PECVD porous ultralow- κ (pULK) material has been investigated in comparison with a thermal oxide and a PECVD oxide. Capacitance-time (C -t) measurements are performed on metal-insulator-metal structures during exposure to different humidity conditions (0% to 80% RH) to determine the effect on the relative permittivity. The results show a big difference in the amounts of moisture absorbance of the investigated materials. While the PECVD oxide and the thermal oxide show no effect on exposure to a humid atmosphere, the increase in the permittivity of SiCOH due to moisture uptake is 7%, and surprisingly, the change in the permittivity of the porous dielectric material is 1.75%. Within these experiments, the diffusion process of moisture into the dielectric materials could be observed in situ, and a diffusion model is created to extract diffusion constants and a value for the saturation concentration. Furthermore, the flatband voltage shift of SiCOH and the pULK material in metal-insulator-semiconductor structures at different ambient humidity levels has been studied. The findings suggest that moisture uptake causes a positive charge inside the dielectric materials, which is responsible for the observed flatband voltage shift.

Humidity sensing properties of CNT–OD–VETP nanocomposite films

In this study, the blend of orange dye (OD), C 17H 17N 5O 2 (5 wt%), vinyl-ethynyl-trimethyl-piperidole (VETP), C 12H 19NO, (5 wt%) and carbon nanotube (CNT) powder (10 wt%) in a mixture of distilled water (80 wt%) and spirit were drop-casted on glass substrates with pre-deposited surface-type silver electrodes to fabricate CNT–OD–VETP nanocomposite thin films. In the process of thin films deposition, 2 V DC was applied to Ag electrodes. The thicknesses of the CNT–OD–VETP films were in the range of 10–15 μm. The I–V characteristics of the surface-type Ag/CNT–OD–VETP/Ag samples showed rectification behavior. The effect of humidity on the electrical properties of the nanocomposite films was investigated by measurement of the capacitance and dissipation of the samples at two different frequencies of the applied voltage: 120 Hz and 1 kHz. The resistance of the samples was determined from values of dissipation. It was observed that at 120 Hz and 1 kHz, under humidity of up to 90% RH, the capacitance of the cell increased by 7.4×10 3 and 740 times and resistance decreased by 2.3×10 4 and 3.8×10 4 times, accordingly, with respect to 40% RH conditions. The average response and recovery times of the films were obtained by capacitance-time measurements to evaluate the dynamics of the water vapor absorption and desorption processes. The experimental results have been supported by the simulation of the capacitance–humidity relationship. It is assumed that the humidity response of the cell is associated with diffusion of water vapors and doping of the semiconductor nanocomposite by water molecules.

Nonvolatile Memory Effects of ZnO Nanoparticles Embedded in an Amorphous Carbon Layer

Nonvolatile memory devices utilizing ZnO nanoparticles (NPs) embedded in an amorphous carbon (a-C) dielectric layer were investigated by capacitance–voltage (C–V) measurements. C–V curves for the Al/ZnO NPs embedded in an amorphous carbon layer/SiO2/p-Si capacitor at 298 K showed a clockwise hysteresis with flat band voltage shift due to charge trapping in the ZnO NPs. Capacitance–time measurements showed that the devices exhibited excellent memory retention ability under ambient conditions. Operating mechanism for the memory devices was proposed based on the C–V results.

Carrier Transport Mechanisms of the Writing and the Erasing Processes for Al/ZnO Nanoparticles Embedded in a Polymethyl Methacrylate Layer/C<SUB>60</SUB>/p-Si Diodes

Transmission electron microscopy images showed that ZnO nanoparticles were randomly distributed inside the polymethyl methacrylate (PMMA) layer. Capacitance-voltage (C-V) measurements on the Al/ZnO nanoparticles embedded in a PMMA layer/C60/p-Si diode at 300 K showed a clockwise hysteresis with a flatband voltage shift due to existence of the ZnO nanoparticles and a C60 buffer layer. The insertion of the C60 layer enlarged the memory window of the device containing the ZnO nanoparticle, as estimated by the flatband voltage shift in the C-V hysteresis. Capacitance-time measurements showed that the devices exhibited excellent memory retention ability at ambient conditions. Operating mechanisms of the charge injection, capture, and emission in the active layer and the charging and the discharging processes in the devices are described on the basis of the C-V results.

Capacitance characteristics of metal-oxide-semiconductor capacitors with a single layer of embedded nickel nanoparticles for the application of nonvolatile memory

This paper reports that metal-oxide-semiconductor (MOS) capacitors with a single layer of Ni nanoparticles were successfully fabricated by using electron-beam evaporation and rapid thermal annealing for application to nonvolatile memory. Experimental scanning electron microscopy images showed that Ni nanoparticles of about 5 nm in diameter were clearly embedded in the SiO2 layer on p-type Si (100). Capacitance–voltage measurements of the MOS capacitor show large flat-band voltage shifts of 1.8 V, which indicate the presence of charge storage in the nickel nanoparticles. In addition, the charge-retention characteristics of MOS capacitors with Ni nanoparticles were investigated by using capacitance–time measurements. The results showed that there was a decay of the capacitance embedded with Ni nanoparticles for an electron charge after 104 s. But only a slight decay of the capacitance originating from hole charging was observed. The present results indicate that this technique is promising for the efficient formation or insertion of metal nanoparticles inside MOS structures.

Effects of CdSe shell layer on the electrical properties of nonvolatile memory devices fabricated utilizing core-shell CdTe-CdSe nanoparticles embedded in a poly(9-vinylcarbazole) layer

Nonvolatile memory devices were fabricated with core-shell CdTe-CdSe nanoparticles embedded in a poly(9-vinylcarbazole) (PVK) layer to investigate the variations in the electrical properties due to a CdSe shell layer. Capacitance-voltage measurements on Al/CdTe nanoparticles embedded in PVK layer/p-Si devices and on Al/core-shell CdTe-CdSe nanoparticles embedded in PVK layer/p-Si devices at 300 K showed hysteresis behaviors with a flatband voltage shift due to the existence of the CdTe and the CdTe-CdSe nanoparticles. Capacitance-time measurements showed that the retention time for devices fabricated utilizing core-shell CdTe-CdSe nanoparticles was larger than that for devices fabricated utilizing CdTe nanoparticles.

Silicon nanocrystals synthesized by electron-beam co-evaporation method and their application for nonvolatile memory

In this paper, the silicon nanocrystals (Si NCs)/SiO 2 hybrid films designed for nonvolatile memory applications are prepared by electron-beam co-evaporation of Si and SiO 2. Transmission electron microscopy images and Raman spectra verify the formation of Si NCs. Metal-oxide-semiconductor capacitor structure with Si NCs embedded in the gate oxide is fabricated to characterize the memory behaviors. High-frequency capacitance–voltage and capacitance–time measurements further demonstrate the memory effect of the structure resulting from the charging or discharging behaviors of Si NCs. It is found that the memory window can be changed by adjusting the Si/SiO 2 wt. ratio in source material. The memory devices with Si NCs/SiO 2 hybrid film as floating gate yield good retention characteristics with small charge loss.

Silicon Nanocrystals Synthesized by Electron-beam Co-evaporation Method and Their Application for Nonvolatile Memory

The Silicon nanocrystals designed for nonvolatile memory applications are firstly prepared by electron beam co-evaporation of Si and SiO2 hybrid. Transmission electron microscopy observation and Raman scattering certify the formation of Si NCs. Metal-oxide-semiconductor capacitor structure with Si NCs embedded in the gate oxide is fabricated to characterize the memory behaviors. High-frequency capacitance-voltage and capacitance-time measurements demonstrate the memory effect of the structure resulting from the charging/discharging behaviors of Si NCs. It is found that flat-band voltage can be changed by adjusting the concentration of Si and SiO2 in hybrids. The Si nanocrystals memory device has yielded good retention characteristics with small charge loss.

Electrical investigations on metal/ferroelectric/insulator/semiconductor structures using poly[vinylidene fluoride trifluoroethylene] as ferroelectric layer for organic nonvolatile memory applications

Poly[vinylidene fluoride trifluoroethylene] (P[VDF/TrFE]) is a ferroelectric polymer and a candidate for the application in a ferroelectric field effect transistor, which is considered as a nonvolatile and nondestructive readout memory cell. In this contribution the authors focus on metal/ferroelectric/insulator/semiconductor capacitor structures with P[VDF/TrFE] as ferroelectric layer. Measuring the capacitance of Al/P[VDF/TrFE]/SiO2/Si stacks in dependence of the applied bias and analyzing the oxide capacitance in dependence of the thickness of the ferroelectric layer, they observe a formation of an interfacial nonferroelectric layer. This layer is responsible for reduced values of polarization profound for thinner P[VDF/TrFE] layers in this system. Capacitance-time measurements at such stacks show the possibility to distinguish between a higher and a lower capacitance state for more than 5 days. Long-time measurements revealed imprint and fatigue-like behavior.