Capacitance Equivalent Thickness Research Articles

Vertically grown metal nanosheets integrated with atomic-layer-deposited dielectrics for transistors with subnanometre capacitance-equivalent thicknesses

Vertically grown metal nanosheets integrated with atomic-layer-deposited dielectrics for transistors with subnanometre capacitance-equivalent thicknesses

Vertically grown metal nanosheets integrated with atomic-layer-deposited dielectrics for transistors with subnanometre capacitance-equivalent thicknesses

Vertically grown metal nanosheets integrated with atomic-layer-deposited dielectrics for transistors with subnanometre capacitance-equivalent thicknesses

(Invited) High-Performance Field-Effect Transistors Based on Two-Dimensional Materials for VLSI Circuits

Introduction Nowadays, the scaling of silicon very large-scale integration(VLSI) technologies has reached channel thicknesses of 7nm. However, further downscaling becomes increasingly difficult as the gate electrostatics require a substantial reduction of the channel thickness to about a fourth of the gate length. As a result, the actual gate length of high-performance(HP) FETs at the current state-of-the-art amounts to 16nm and is projected to stall at 12nm for the 1.5nm node and the following nodes, according to the International Roadmap for Devices and Systems(IRDS)[1]. For these nodes, two-dimensional(2D) materials could have the potential to replace silicon as the channel material. They can maintain sizable mobilities at atomic thicknesses, thus providing enhanced gate control in stacked channel nanosheet transistor structures[2]. Even though FETs based on 2D materials hold the promise to serve as FETs at the front end of the line, numerous challenges still need to be overcome. Downscaling Dimensions For ultra-scaled device designs, 2D materials can be used as a channel in stacked nanosheet FETs. In such a structure, the 2D material is gated from both sides, as depicted in Fig.1(a). By stacking multiple double-gated channels on top of each other, the required on-current density of around 1mA/μm can be achieved[3]. The first experimental demonstrations have achieved sub-5nm gate lengths[4] or, in a different design, a gate pitch of only 42nm[5], meeting the requirements for the 1.5nm node. While these prototypes show that 2D FETs can be scaled down, they have been fabricated in a laboratory. Many challenges must be overcome before such small devices can be fabricated in industry-compatible batch processes which require a high yield and low variability. Contact Engineering In order to enable sufficiently high on-current densities, small contact resistances to 2D semiconductors are required, which are inhibited by the formation of Schottky barriers at the metal to semiconductor interface. Schottky contacts to 2D materials are so prevalent because there is, on one side, a lack of stable doping schemes, and on the other side, pronounced Fermi-level pinning at the metal-to-semiconductor interface. Semi-metallic bismuth contacts can provide low-resistive contacts to n-type MoS2 FETs, as the bismuth suppresses the metal-induced gap states which pin the Fermi-level[6]. This way, a small contact resistance of 123Ωμm has been achieved, reaching the IRDS limit for the 1.5nm node. While comparable results have been realized for antimony contacts to n-type FETs, low-resistive contacts to p-type FETs are more challenging. Gate Stack Design A good gate stack for 2D FETs must provide excellent gate control while maintaining small gate leakage currents, which requires a capacitive equivalent thickness(CET) smaller than 0.9 nm. At these small CETs, a small gate leakage can only be obtained with a high-dielectric constant gate insulator and sizable band offsets, rendering some insulators, e.g. hexagonal boron nitride, unsuitable. Simultaneously, the gate insulator should form a van-der Waals interface with the 2D semiconductor, as otherwise, interface traps degrade the carrier mobility and the sub-threshold slope[7]. Charge traps within the insulator are the root cause of the limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in pronounced Bias Temperature Instabilities(BTI). The electrical stability can be improved, if the defect bands in the gate insulator are energetically far away from the semiconductor’s conduction and valence band edges, see Fig.1(b)[8]. Conclusions Despite all the progress achieved within the last decade, the challenges for VLSI integration of 2D materials are enormous. First, stacked 2D FETs with scaled dimensions still need to be realized at an industrial scale. Second, despite low contact resistance demonstrations for n-type FETs, the resistances for p-type FETs are one order of magnitude too high. Finally, one of the most serious obstacles is identifying a suitable gate stack. Even though promising combinations of insulators to semiconductors have been suggested, like Bi2O5Se/Bi2O2Se, CaF2/MoS2 or SrTiO3/MoS2, it is at the moment unclear, which of them provides the best performance. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no. 101055379.

(Invited) Gate Stack Design for Field-Effect Transistors Based on Two-Dimensional Materials

1.Introduction Two-dimensional(2D) materials hold the promise to allow for ultrathin channels built of single atomic monolayers in ultimately scaled field-effect transistors (FETs). Due to this small thickness, an enhanced gate control is achieved while at the same time sizable mobilities in the 2D materials can be maintained[1]. In this way, the on-current density of the devices could potentially be increased to up to 1mA/μm by stacking six nanosheets on top of each other, combining p-type and n-type FETs in vertical integration. Even though FETs based on 2D materials hold a lot of promise, numerous challenges still need to be overcome. One of the most serious obstacles is the identification of a suitable gate stack. Over the last years, several insulators have been suggested, including layered insulators like hBN[2], ionic insulators like CaF2[3], amorphous high-k dielectrics like HfO2[4], see Fig.1. In addition, crystalline perovskites like SrTiO3[5] or native oxides like Bi2SeO5[6] have been explored. However, which of these materials provides the best performance is at the moment unclear and needs to be evaluated according to the criteria of scalability (Section 2), the minimization of charge traps (Section 3), and batch-processing compatible deposition technology for double-gated device designs (Section 4). 2.Scalable Gate Stacks High-performance FETs require a high on/off current ratio and steep subthreshold slopes. In order to preserve these characteristics in devices with ultimately scaled channel lengths, the insulator capacitance needs to be higher than 1.5μFcm-2, corresponding to a capacitive equivalent thickness smaller than 1nm. At the same time, if the insulator thickness becomes too small, the gate leakage current often easily exceeds the low-power limit of 0.015 Acm-2, thereby increasing the standby power consumption in the off-state. In fact, the gate leakage currents through thin hBN layers are high, rendering it unsuitable as a gate insulator for scaled FETs, while CaF2, HfO2 or Bi2SeO5 show promise[7]. 3.Minimizing Charge Traps The gate insulator should form a van der Waals interface with the 2D semiconductor, as otherwise, interface traps will degrade the carrier mobility and the sub-threshold slope[8]. Charge traps within the insulators cause limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in Bias Temperature Instabilities. As a consequence, the stability can be enhanced if the defect bands in the gate insulator are energetically far away from the conduction and valence band edges[9]. Thus, the number of electrically active charge traps can be minimized by selecting a suitable combination of 2D semiconductor to insulator or by reducing the width of the defect bands by using crystalline insulators. 4.Deposition Technology Gate insulators need to be deposited on top of 2D semiconductors for top gate formation. However, the inert planes of 2D materials inhibit direct nucleation of insulators from the gaseous phase in an atomic layer deposition process. In this context, a promising approach is to use a self-assembled polymer monolayer to nucleate the precursors[4]. Molecular beam epitaxy is an alternative growth approach for gate insulators which offers the advantage of van der Waals epitaxy for layered materials, where the lattice-matching conditions are relaxed[10]. In order to avoid the growth of the insulator on top of the 2D semiconductor altogether the in-situ oxidation of the 2D semiconductor to its native oxide is a promising option, like for Bi2SeO5. 5.Conclusions Even though many novel insulator systems for 2D FETs have been proposed over the last couple of years, it is still unclear which of them best meets the requirements formulated. The most important questions to be addressed in the future will be to identify systems with reproducibly small interface and border trap densities and high thermal stability and to develop suitable batch-processing compatible top gate deposition methods for these material systems. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no.101055379.

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO2/Al2O3 dielectric for a SiGe channel FinFET transistor

In this paper, the optimization of SiGe interface properties for the SiGe channel fin field effect transistor (FinFET) transistor is explored in detail. First, optimal low-temperature ozone oxidation at 300 °C for 30 min was confirmed based on Al2O3/Si0.7Ge0.3 metal-oxide-semiconductor (MOS) capacitors. This is because a higher oxidation temperature and a longer oxidation time can suppress the formation of GeO X in the interface layer (IL) and significantly improve the interface state density (D it). Moreover, compared with the Al2O3 sample, the HfO2 sample can obtain a thinner capacitance equivalent oxide thickness (CET), but it is more vulnerable to deterioration of Si0.7Ge0.3 interface properties because the GeO X in the IL is more likely to diffuse into the HfO2 layer. To further optimize the D it and CET of the Si0.7Ge0.3 MOS capacitor simultaneously, a stacked HfO2/Al2O3 dielectric is proposed. Compared with the HfO2 sample, its frequency dispersion characteristics and D it have been improved significantly, as the thin Al2O3 layer prevents the diffusion of GeO X to the HfO2 layer and controls the growth of GeO X . Therefore, a high-quality Si0.7Ge0.3 interface property optimization technology is realized via the development of a low-temperature ozone oxidation (300 °C, 30 min) method combined with a stacked HfO2/Al2O3 dielectric. In addition, a Si0.7Ge0.3 FinFET utilizing this newly developed interface property optimization scheme is successfully prepared. Its excellent subthreshold swing performance indicates that good interface quality of the Si0.7Ge0.3 is obtained. The above results prove that this newly developed interface property optimization scheme is a practical technology for high-mobility SiGe FinFET.

(Invited, Digital Presentation) Heterogeneous Integration of Ultrahigh-Κ Single-Crystalline SrTiO3 Membranes for Two-Dimensional Electronics

Even though competitive 2D field-effect transistors (FETs) with the scaled channel dimensions have been demonstrated, it still is a challenge to integrate 2D semiconductors and high-κ dielectrics without deteriorating their interfaces, while decreasing capacitance equivalent thickness (CET) of dielectrics to maintain the gate controllability. In particular, the dielectric/channel interface is one of the predominant factors to affect device performance, including carrier mobility, switching behavior, and drifts of device parameters. This is often caused by the nature of dielectrics used, and the integrating methodologies applied.Typically, high-κ dielectrics used in silicon technology (i.e., Al2O3 and HfO2) are inherited by 2D FETs. The amorphous nature of these oxides makes the elimination of charge scattering and trapping sites at the dielectric/channel interfaces extremely difficult, not to mention that the direct deposition of dielectrics usually damages the 2D channel and results in poor uniformity in sheer thickness. Some interfacial passivation layers and processes have been developed, but they lead to thickening overall CET instead. Alternative approaches with the crystalline dielectric materials such as multilayer hBN and epitaxial calcium fluoride (CaF2), whose surfaces are well-constructed and atomic-flat, have demonstrated the competitive advantages of crystalline dielectric over the conventional amorphous oxides in spite of relatively lower κ values.Here, we demonstrate ultra-scaled 2D FETs with desirable sub-1 nm CET through heterogeneous integration of monolayer CVD MoS2 and quasi-2D single-crystalline SrTiO3 membranes, where the optimized SrTiO3 gate dielectrics exhibit a low gate leakage (J leak < 10-2 A/cm2 at 2.5 MV/cm). Typical transistors manifest good reliability and competitive performance characteristics, including steep subthreshold swings (SS) down to ~70 mV dec-1 and ON/OFF current ratios up to 107, matching low-power specifications suggested by the latest International Roadmap for Devices and Systems (IRDS). In addition, the van der Waals (vdW) interface between quasi-2D dielectrics and 2D semiconductors moderates the unfavorable fringing-induced barrier lowering (FIBL) effect occurring in ultra-scaled Si transistors with very high-κ dielectrics, which broadens the dielectric selection in 2D electronics for future technology node.

Oxygen‐Scavenging Effects of Added Ti Layer in the TiN Gate of Metal‐Ferroelectric‐Insulator‐Semiconductor Capacitor with Al‐Doped HfO2 Ferroelectric Film

AbstractTi layer inserted in the TiN gate electrode effectively scavenges the oxygen in the low‐k interfacial SiO2 of the metal–ferroelectric–insulator–semiconductor (MFIS) capacitors with the ferroelectric Al‐doped HfO2 (HAO) thin film. The scavenging effect increases remanent polarization (Pr) and reduces coercive voltage (Vc) and capacitance equivalent thickness (CET) of the HAO films, particularly when the MFIS capacitor is annealed at 800 °C. Additionally, frequency dispersion of capacitance characteristics and interface trap density (Dit) calculations reveal that actively‐triggered oxygen‐scavenging effects also reduce defect or trap‐induced degradation. The Ti‐inserted MFIS structure exhibits fatigue‐free endurance and relatively low leakage current characteristics as compared to a structure without the Ti scavenging layer in high annealing temperature conditions required for crystallization of the HAO ferroelectric films.

High-κ perovskite membranes as insulators for two-dimensional transistors.

The scaling of silicon metal-oxide-semiconductor field-effect transistors has followed Moore's law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents1. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors2,3. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10-2 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxidedielectricsand 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics4. Typical short-channel transistors made of scalable molybdenum-disulfidefilms by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 107, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems5.

Group IV Transition Metal (M = Zr, Hf) Precursors for High-κ Metal Oxide Thin Films.

This paper describes the synthesis of eight novel zirconium and hafnium complexes containing N-alkoxy carboxamidate-type ligands, as potential precursors for metal oxides and atomic layer deposition (ALD) for HfO2. A series of ligands, viz., N-ethoxy-2,2-dimethylpropanamide (edpaH), N-ethoxy-2-methylpropanamide (empaH), and N-methoxy-2,2-dimethylpropanamide (mdpaH), were used to afford complexes Zr(edpa)4 (1), Hf(edpa)4 (2), Zr(empa)4 (3), Hf(empa)4 (4), Zr(mdpa)4 (5), Hf(mdpa)4 (6), ZrCp(edpa)3 (7), and HfCp(edpa)3 (8). Thermogravimetric analysis curves assessed for the evaporation characteristics of complexes 1-8 revealed single-step weight losses with low residues, except for the mdpa-containing complexes. Single-crystal X-ray diffraction studies of 1, 2, 5, and 6 revealed that all the complexes have monomeric molecular structures, with the central metal ion surrounded by eight oxygen atoms from the four bidentate alkoxyalkoxide ligands. Among the complexes prepared, 8 exhibited a low melting point (64 °C), good volatility (1 Torr at 112 °C), high thermal stability, and excellent endurance over 6 weeks at 120 °C. Therefore, an ALD process for the growth of HfO2 was developed using HfCp(edpa)3 (8) as a novel precursor. Furthermore, the HfO2 film exhibited a low capacitance equivalent oxide thickness of ∼1.5 nm, with Jg as low as ∼3 × 10-4 A/cm2 at Vg -1 V in a metal-insulator-semiconductor capacitor (Au/HfO2/p-Si).

ALD-ZrO2 gate dielectric with suppressed interfacial oxidation for high performance MoS2 top gate MOSFETs

To enhance the feasibility of 2-dimensional transition metal dichalcogenides (TMDCs) channels in future nano-electronic and optoelectronic devices, a top gate device structure fabricated with very-large-scale-integration compatible process is mandatory. High-κ dielectric ZrO2 has been directly deposited on MoS2 through low-temperature atomic layer deposition (ALD) without any surface protection layers. The uniform growth of ZrO2 on MoS2 was confirmed to be caused by the physical adsorption, resulting in the suppressed interfacial oxidation and the reduced damage of monolayer (1L) MoS2 channel. Low thermal budget post-deposition annealing was found to be effective for reducing interfacial traps between ZrO2 and MoS2 interface, thus enhancing the device performances of 1L MoS2 nMOSFETs. Low capacitance equivalent thickness (CET) of ZrO2 of 2.3 nm has been achieved while maintaining decent device performance, indicating low-temperature ALD is promising for future TMDC top gate devices with a high-quality interface and thin CET.

Al2O3 blocking layer inserted ZrO2 Metal-Insulator-Metal capacitor for the improved electrical and interfacial properties

Atomic layer deposition with O3 reactant is widely used to deposit thin and conformal films in a ZrO2 based metal-insulator-metal (MIM) capacitor. Post-deposition annealing (PDA) improves the MIM capacitor's performances by crystallizing tetragonal ZrO2 with high dielectric constant but it inevitably causes formation of excessive TiN/ZrO2 interface. Oxygen diffusion from ZrO2 to TiN bottom electrode oxidizes TiN to TiOx and TiOxNy during PDA, which increases the capacitance equivalent thickness of interlayer (CETint) and leakage current of the MIM capacitor. In this study, we inserted a Al2O3 thin film as the oxygen diffusion blocking layer (ODBL) between ZrO2 dielectric and bottom TiN electrode to improve the interfacial properties in TiN/ZrO2/TiN MIM capacitor. The angle-resolved X-ray photoelectron spectroscopy is employed to study the effects of Al2O3 OBDL on the chemical states of the interfacial layer in MIM capacitor, which confirmed that the Al2O3 ODBL inhibits the growth of TiN/ZrO2 interface. In addition, the electrical analysis of MIM capacitor showed that the CET of TiN/ZrO2 interface decreased from 0.493 to 0.209 nm and the leakage current highly decreased from 10−7 to 10−9 A/cm2 at 1 V although the dielectric constant slightly reduced from 35.1 to 30.7 with the insertion of Al2O3. This study offers a systematic investigation of interfacial layers in Al2O3 OBDL inserted ZrO2 MIM capacitor in the points of chemical and electrical characterization.

Gate leakage current reduction and improved reliability with an ultra-thin Ti layer for low-power applications

This study analyzed the physical and electrical characteristics of the interface reactions between hafnium-based high-k gate dielectrics and a TiN-based metal gate. Decreasing the N2 gas flow ratio (RN2 = N2/Ar+N2) from the physical-vapor-deposited TiN decreased the gate leakage current (JG) and the effective work function (EWF) of the metal gate. X-ray photoelectron spectroscopy analysis confirmed that TiN deposited with a lower RN2 condition can be easily oxidized to form TiOx at the gate oxide and metal gate interface after annealing at 1050 °C. This newly created oxide layer can prevent oxygen diffusion from the gate oxide through TiN to the TiN/poly-silicon interface, resulting in improved gate oxide quality. Inserting a thin Ti layer (< 1 nm) on the gate oxide formed a TiOx layer without a change in EWF, indicating that TiN composition variation followed the same trend as capacitance equivalent thickness (CET) versus JG. Therefore, an oxygen-blocking layer can have the same effect as gate oxide quality improvement for both scenarios—low RN2 of TiN and the thin Ti insertion—due to decreased oxide charge density. The Ti insertion process was associated with improved gate oxide leakage, negligible CET increase (0.2 Å), and gate oxide reliability, including time-dependent dielectric breakdown characteristics due to the blockage of oxygen up-diffusion.

Four-terminal polycrystalline Ge1−xSnx thin-film transistors using copper-induced crystallization on glass substrates and their application to enhancement/depletion inverters

Polycrystalline germanium–tin (Ge1−xSnx) thin films with a thickness of 15 nm were grown at 500 °C using Cu-induced crystallization. The films were applied to fabricate four-terminal (4T) thin-film transistors (TFTs) on a glass substrate. The top gate (TG) was fabricated from 30 nm thick SiO2, while the bottom gate (BG) consisted of a double layer of HfO2 and SiO2 with a capacitance equivalent thickness of 16 nm. Aluminum-induced lateral metallization of the source and drain (SD) was implemented to decrease the parasitic resistance of the SD. The Ion/Ioff of the double gate approximately corresponded to 1 × 104. Furthermore, 4T poly-Ge1−xSnx TFTs operated with a field-effect mobility of 20 cm2 V−1 s−1 for the TG drive and 12 cm2 V−1 s−1 for the BG drive at a control gate voltage of 0 V in both cases. A p-channel enhancement/depletion inverter was validated based on the precise control of threshold voltage using a control gate.

Leakage current lowering and film densification of ZrO2 high-k gate dielectrics by layer-by-layer, in-situ atomic layer hydrogen bombardment

A layer-by-layer, in-situ H2 plasma treatment in each cycle of atomic layer deposition, referred to as “atomic layer hydrogen bombardment” (ALHB), is applied to improve electrical properties of ZrO2 high-k gate dielectrics. The H2 plasma bombardment facilitates the adatom migration due to energy delivery to each as-deposited monolayer from the H2 plasma. In addition, the H2 plasma treatment contributes to the removal of precursor ligands for the release of steric hindrance. Hence the ALHB treatment leads to film densification and suppression of oxygen vacancies of ZrO2, as evidenced by X-ray reflectivity and X-ray photoelectron spectroscopy characterizations. As a result, ~90% decrease of gate leakage current is achieved in the ZrO2 high-k gate dielectrics with capacitance equivalent thicknesses of ~1.3 nm and ~0.6 nm in metal-insulator-semiconductor and metal-insulator-metal capacitors, respectively. The results manifest that the ALHB treatment is a promising technique to enhance dielectric and electrical characteristics of nanoscale thin films, for further progress of advanced devices such as sensors, solar cells, memories, and nanoelectronics.

Improvement in Electrical Characteristics of ZnSnO/Si Bilayer TFET by W/Al₂O₃ Gate Stack

We have examined impacts of gate insulator (Al2O3 or HfO2) and gate electrode (TiN or W) on electrical performance of ZnSnO/Si bilayer tunneling fieldeffect transistors (TFETs). It is found from the capacitance-voltage ( ${C}$ - ${V}$ ) characteristics that the W gate is effective to reduce the counter-clockwise hysteresis. Additionally, the optimal temperature of post-metallization annealing (PMA) is different for each gate stack, and this optimization is critically important for the high ON-state current ( ${I} _{\mathrm{ ON}}$ ) and steep ON/OFF switching. The W/Al2O3/ZnSnO/Si bilayer TFET provides the hysteresis-free steep ON/OFF switching with the minimum sub-threshold swing ( SS ) of 65.4 mV/dec. and average SS of 72.0 mV/dec. in a gate-voltage swing of 0.3 V, which are 19% and 18% lower than the control TiN/Al2O3/ZnSnO/Si bilayer TFET. When the gate stack is replaced by W/HfO2/Al2O3, the TFET exhibits less steep ON/OFF switching in spite of thinning capacitance equivalent thickness (CET) from 5.9 and 2.3 nm. These results indicate the importance of improvement in the gate stack quality on the sub-threshold characteristics of the bilayer TFETs.

(Invited) Characteristics of Several High-k Gate Insulators for GaN Power Device

Introduction Vertical GaN metal-oxide-semiconductor (MOS) devices on freestanding GaN substrates have been widely investigated as a means of reducing the dimensions of devices intended for applications associated with high power and high frequency [1]. Inserting a gate insulator in such as MOS structures has been found to result in low leakage currents and high breakdown strengths. Oxide (High-k) with a high dielectric constant (k)-value have been studied instead of SiO2 from the viewpoint of increasing the physical thickness. Numerous High-k gate insulators, including Al2O3, HfO2, Al2O3-HfO2 bilayers, AlSiOx and HfSiOx have been studied for use in MOS units [2, 3]. These films are typically fabricated using atomic layer deposition (ALD) because ALD has a big advantage of conformal film fabrication on three-dimensional structure, which is required when producing vertical GaN devices. To improve electrical properties of these gate insulators and GaN/insulator interface, annealing process was carried out after High-k deposition (post-deposition annealing: PDA) and post-metal deposition (post-metal deposition annealing: PMA). Actually, GaN capacitors with Al2O3 reduced significantly the interface state density (Dit) at GaN/Al2O3 interface by PMA at low temperarure ~ 300 °C [4]. On the other hand, Ga diffusion and additional electrical defects were also found to be easily introduced into GaN/High-k stack structure by PDA at a high temperarure above 700 °C. Here, we have an interesiting about how the PDA and PMA processes affect to characteristics of GaN devices with several High-k gate insulators. In this paper, we present influence of the PDA and PMA processes on characteristics of GaN capacitors with Al2O3, HfO2, and HfSiOx gate insulators. Experiment Pt-gated n-GaN MOS capacitors were fabricated as follows: Firstly, ~20-nm-thick High-k gate insulators such as Al2O3, HfO2, and HfO2/SiO2 laminate were deposited on n+-GaN/n-GaN epilayer by plasma-enhanced ALD at 300 °C. Next, PDA was carried out at 800 °C in N2. HfSiOx was formed from HfO2/SiO2 laminate after PDA. Finally, Pt gate electrode and Pt/Ti ohmic cntact were deposited to fabricate n-GaN/High-k/Pt MOS capacitors. PMA was performed at 300 °C in N2. Results and discussion The Al2O3 and HfO2 films had polycrystalline structure of g phase and monoclinic phase, respectively, while the HfSiOx film had an amorphous structure after PDA at 800 °C. The k values for the Al2O3, HfO2, and HfSiOx films which esgtimated from capacitance (C)-voltage (V) data were 8, 17.6, and 15.1, respectively. The Al2O3 capacitor exhibited a large frequency dispersion while the HfO2 and HfSiOx capacitors were negligible small, indicating that the charging state of the interface traps occur at GaN/Al2O3 interface. The frequency dispersion of the Al2O3 capacitor significantly decreases after PMA at 300 °C. To better understand the characteristics of the GaN/High-k interface, the Dit was also estimated using a conductance method. The Dit values of all capacitors before PMA at the energy level of Ec-E = 0.4 V was decreased in the following order: Al2O3 (5 × 1012 cm-2eV-1) > HfO2 (1.4 × 1012 cm-2eV-1) > HfSiOx (4 × 1011 cm-2eV-1). As expected from the C-V characteristics, the Al2O3 capacitor had a large Dit value due to the electron traps. From the leakage current density (J)-electric field (E) characteristics, The J values of the HfSiOx capacitor was significantly reduced compared to those of the Al2O3 and HfO2 capacitors. It is thought that the difference in the J properties between the HfSiOx and other Al2O3, HfO2 can be primarily attributed to the presence of amorphous or polycrystalline structures, because grain boundaries in polycrystalline structures can act current leakage paths. Considering the bias application for the same amount of charge accumulation at the interface, effective breakdown electric field (Ebd) values, which was estimated from the applied voltage divided by capacitance equivalent thickness, were 15, 14, and 35 MV/cm in Al2O3, HfO2, and HfSiOx capacitors, respectively. Summary We conclude that the HfSiOx film is an attractive material as gate insulator because of amorphous structure, higher k, relatively low Dit, and high effective Ebd. Acknowledgement The authors wish to thank Prof. T. Hashizume of Hokkaido University for helpful discussion. This work was supported in part by the MEXT Program for the Research and Development of Next-generation Semiconductors to Realize an Energy-saving Society.

Border Trap Extraction with Capacitance- Equivalent Thickness to Reflect the Quantum Mechanical Effect on Atomic Layer Deposition High-k/In0.53Ga0.47As on 300-mm Si Substrate

This study presents a model to calculate the border trap density (Nbt) of atomic layer deposition high-k onto In0.53Ga0.47As on a 300-mm (001) Si substrate. This model considers the quantum confinement effect and band nonparabolicity. Capacitance-equivalent thickness (CET) was used to reflect the distance of the charge centroid from the oxide–semiconductor interface. The border trap values based on CET were found to be approximately 65% lower than the extracted values based on physical thickness in the In0.53Ga0.47As material. In an investigation of two different post-metal annealing effects on border traps, the border trap was more effectively passivated by N2-based forming gas annealing (FGA) compared with rapid thermal annealing (RTA), whereas a lower interface state density was observed in RTA-annealed samples compared with FGA-annealed samples. Nbt extraction at different bias voltages demonstrated that the applied frequencies travel deep into the oxide and interact with more traps as more the Fermi level passes the conduction band, thus creating tunneling with the carriers.

Effects of ZrO2/Al2O3 Gate-Stack on the Performance of Planar-Type InGaAs TFET

We investigate the impact of gate-stack engineering using W/ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> on the performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that 1-nm-thick capacitance equivalent thickness (CET) with low leakage current is achieved by using ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> with the dielectric constant of around 40 on In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As. On the other hand, the reduction of Dit by insertion of ALD 1-5 cycle Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interfacial layers (ILs) is found to be mandatory for obtaining TFET performance enhancement. The planar-type InGaAs TFETs using the ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> IL gate-stack with CET of 1 nm exhibit the minimum subthreshold swing (S.Smin) of 55 mV/dec and ION of 0.88 μA/μm (VG-VOFF = 0.5 V, VD = 0.2 V, and IOFF = 10 pA/μm). Furthermore, the ZrO2/Al2O3 IL gatestack is applied to the optimized In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> As quantum well (QW) channel TFETs. The low S.Smin of 50 mV/dec and high ION of 1.2 μA/μm (VG-VOFF = 0.5 V, VD = 0.2 V, IOFF = 10 pA/μm, and CET = 1.1 nm) are demonstrated by combing the present ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate-stack with the optimum In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> As QW channel structure.

High-Mobility Ge pMOSFETs With Crystalline ZrO2 Dielectric

High-mobility Ge pMOSFETs with crystalline ZrO2 gate dielectric are realized and compared against devices with O3/ZrO2, amorphous ZrO2, and Al2O3/ZrO2 gate dielectrics. The crystallization of ZrO2provides for significantly improved effective hole mobility ( $\boldsymbol {\mu }_{\textsf {eff}}$ ) and reduced capacitance equivalent thickness (CET), boosting the transistor drive current. An interfacial Al2O3 passivation layer enhances $\boldsymbol {\mu }_{\textsf {eff}}$ but increases the CET. Passivation-free Ge pMOSFETs with 2.5-nm crystalline ZrO2gate dielectric achieve a higher $\boldsymbol {\mu }_{\textsf {eff}}$ than previously reported unstrained Ge pMOSFETs with the CET below 1 nm, at a high inversion-layer charge density.

Improvement of the electrical and interfacial propertie of TiN/ZrO2 by a modulated atomic layer deposition process with controlled O3 dosing

In this work, we have studied the atomic layer deposition (ALD) of ZrO2 under various O3 dosing conditions and systematically investigated the interfacial properties of ZrO2/TiN during ALD fabrication using the CpZr(N(CH3)2)3 and O3 reactant combination. In a typical ZrO2 ALD process, the oxidation condition fundamentally determines the interface oxidation and bulk film properties. High oxidation power is required to enhance the crystallinity of the ZrO2 film with low defect densities but inevitably causes the growth of the interfacial oxide, which reduces the dielectric constant of the resulting film. In the current study, we propose a modulated ALD process with controlled O3 dosing to realize the high performance of a metal-insulator-metal (MIM) capacitor device. The initial ALD cycles proceeded with low O3 dosing to suppress the oxidation of the TiN substrate, and the subsequent bulk film was grown with high O3 dosing to improve the crystallinity of the ZrO2. As a result, we achieved a high dielectric constant ZrO2 material with a reduced defect density and a minimum interface capacitance equivalent thickness (CET) of the TiN/ZrO2/TiN MIM capacitor under modulated oxidation conditions. This work provides a useful method to control the interface and bulk properties of dielectric layers at the atomic level.