Canonical Signed Digit Representation Research Articles

Resource minimization and power reduction of ESPFFIR filter using unified adder/subtractor

Digital filters are the important processing elements in most of the digital signal processing system designs, ranging from medical signal processing to wireless communication. Low power and area efficient Finite Impulse Response filter is designed with the aid of parallel processing which increases the throughput. Symmetric property reduces the multipliers into half in Even Symmetric Parallel Fast Finite Impulse Response (ESPFFIR) filters. The adder and the subtractor present in the pre/post-processing blocks increase in accordance with the block size L of ESPFFIR filter which in turn increases the numbers of unified operators. The canonical signed digit representation of the coefficient in the design Multiple Constant Multiplications (MCM) based multipliers has the advantages of utilizing unified operators in sub-filter block of ESPFFIR. To reduce the power consumption and resource utilization of the ESPFFIR filter, the unified operator used in the pre/post processing and MCM blocks are replaced by unified adder subtractor (UAS). The UAS utilizes fewer resources for simultaneous calculation of sum and difference of two operands with less area and low power consumption. This paper shows the design of 16-bit Square Root (SQRT) UAS CSLA adder using UAS logical element to reduce the area utilization, power consumption and delay. Then the Heuristic of cumulative benefit (Hcub) based MCM multiplier is designed using UAS. The existing SQRT BEC CSLA adder and subtractor with same input present in the pre/post processing block of the ESPFFIR filters are replaced by a single SQRT UAS CSLA in suitable places. The Hcub MCM used in the sub-filter blocks of the ESPFFIR are replaced using SQRT UAS CSLA based MCM multiplier. The SQRT UAS CSLA consumes 78% less area, 29.51% less power and 24% less delay when compared to the BEC CSLA 2 (one BEC based CSLA Adder plus one BEC based CSLA Subtractor). Finally, the SQRT UAS CSLA adder and Hcub based UAS MCM multipliers are used to design the filter, the overall area and power consumption of UAS based ESPFFIR is reduced compared with the existing BEC based ESPFFIR filter. Cadence RC tool is used for analysis.

Protective effect and treatment of cucurbitacin B on mice with sepsisassociated acute kidney injury

Ground Penetrating Radar (GPR) is vastly utilized for non-invasive study of man-made structures, particularly for determining depth of pipes which are buried under the ground. However, shallow objects might obscure GPR raw data which is reflected from deeper ones. The current work suggests a signal processing method known as the parallel lifting-based Canonical Signed Digit (CSD) 2D Discrete Wavelet Transform (DWT) infrastructure is suggested to realize a multiplier less architecture with lesser hardware complexity, smaller area and power consumption. The flipping structure of the lifting scheme can be recognized to reduce the longest critical path. CSD based structure is demonstrated with only adders and free of multipliers. A stripe based scanning method is adopted in order to achieve an efficient memory. JPEG 2000 lossy 9/7 filter is structured and the same scanning method with CSD is used to design 6/10 filter to contribute the evidence for the proposed methodology. In the existing method, memory efficiency is achieved with less speed. The new architecture is proposed using CSD multiplier with more speed. The filter coefficients are multiplied by 256 and are converted to integer form and then CSD representation is considered. The suggested architecture provides multiplier-less infrastructure for DWT utilizing CSD. This infrastructure is appropriate for high speed online applications with less area and power consumption. For an N× (N+1) image, the suggested CSD based lifting infrastructure utilizes solely 3N temporal memory, 2S transposition memory as well as Tm+Ta critical path.

Reconfigurable Low Pass FIR Filter Design using Canonic Signed Digit for Audio Applications

Objectives: This paper highlights the design of multiplier-less FIR filter. The binary coefficients are replaced by Canonic Signed Digit representation which reduces the complexity of the design. Methods/Statistical Analysis: In the current scenario more research is going on the optimization of Finite Impulse Response filters with less complex hardware design. The FIR filters performance depends on number of coefficient multipliers. The multipliers are expensive in terms delay area and power. In the CSD based filter, the number of non-zero bits is reduced. This proposed filter is designed in MATLAB, simulated in ISE environment and implemented on FPGA. Findings: The proposed filter is implemented on three FPGA devices, Xilinx's Spartan-3E, xc3s500e-4fg320, Virtex 2P, 2vp30ff1152-5 and Virtex 5P xc5v1x50t-3ff1136. Improvements: The designed structure uses reduced number of hardware components like slices, look up tables (LUTs) and flip-flops as compared to different structures and offers better performance.

Comparative study of 16‐order FIR filter design using different multiplication techniques

This study represents designing and implementation of a low power and high speed 16 order FIR filter. To optimise filter area, delay and power, different multiplication techniques such as Vedic multiplier, add and shift method and Wallace tree (WT) multiplier are used for the multiplication of filter coefficient with filter input. Various adders such as ripple carry adder, Kogge Stone adder, Brent Kung adder, Ladner Fischer adder and Han Carlson adder are analysed for optimum performance study for further use in various multiplication techniques along with barrel shifter. Secondly optimisation of filter area and delay is done by using add and shift method for multiplication, although it increases power dissipation of the filter. To reduce the complexity of filter, coefficients are represented in canonical signed digit representation as it is more efficient than traditional binary representation. The finite impulse-response (FIR) filter is designed in MATLAB using equiripple method and the same filter is synthesised on Xilinx Spartan 3E XC3S500E target field-programmable gate array device using Very High Speed Integrated Circuit Hardware Description Language (VHDL) subsequently the total on-chip power is calculated in Vivado2014.4. The comparison of simulation results of all the filters show that FIR filter with WT multiplier is the best optimised filter.

Error‐free computation of 8‐point discrete cosine transform based on the Loeffler factorisation and algebraic integers

An 8-point discrete cosine transform (DCT) fast algorithm based on the Loeffler DCT factorisation and algebraic integer (AI) representation is proposed. The proposed algorithm is an error-free implementation of the Loeffler algorithm and it is capable of computing the 8-point DCT multiplierlessly. Decoding architectures are also proposed for mapping AI encoded quantities back to usual fixed point arithmetic using canonical signed digit representation and the expansion factor method. The proposed algorithm is mapped into systolic-array digital architectures and physically realised as digital prototype circuits using field-programmable gate array technology on a Reconfigurable Open Architecture Computing Hardware board and mapped to 0.18 μm complementary metal–oxide–semiconductor technology using AMS Encounter Digital Implementation libraries at 1.8 V supply.

Multiplierless filter‐bank based multicarrier system by using canonical signed digit representation

ABSTRACTThe filter‐bank based multicarrier (FBMC) system is a candidate for designing the physical layer of a cognitive radio because of its spectral efficiency and the spectral containment. The main drawback of such a system compared with orthogonal frequency division multiplexing systems is its high computation complexity, because each subcarrier is shaped by a non‐rectangular prototype filter. Although poly‐phase decomposition is suggested to decrease the sampling rate of filtering, the number of filtering operations (multiplications) is dramatically increased by the growing number of subcarriers and the amount of the desired spectral containment. Hence, hardware implementation of the FBMC system faces challenges such as high electrical power consumption and large silicon area occupation. In order to reduce computational complexity, a multiplierless filter design based on the canonical signed digit (CSD) representation is proposed. In this technique, at first, a prototype filter is designed. Then a pre‐optimization step is employed to adapt the prototype filter coefficients to system objectives and produce an enriched initial seed for genetic algorithm (GA) optimization. Finally, a customized GA is employed to jointly optimize and synthesize filter coefficients into the finite precision CSD representation so that the system objectives such as intersymbol‐interference, interchannel‐interference, and stop‐band attenuation remain unchanged against the full‐precision representation of coefficients. Copyright © 2014 John Wiley & Sons, Ltd.

Multiplier-less Farrow Structure based Linear Phase Low Pass Interpolation Filter

This paper proposes a totally multiplier-less farrow structure based linear phase low-pass interpolation filter. When implemented using farrow structure, it has inherently low number of multipliers and adders compared to that using finite impulse response (FIR) filter structure. To further reduce the implementation complexity, the structure is made totally multiplier-less. Canonic signed digit (CSD) representation of the filter coefficients is made use of in this paper. A meta-heuristic optimization algorithm is deployed to obtain optimal CSD representation. Reduction in the implementation complexity leads to lower power consumption, chip area and cost.

Reconfigurable channel filtering and digital down conversion in optimal CSD space for software defined radio

Software defined radio (SDR) is a platform for using the same hardware to support multiple wireless communication standards. The channelizer in the SDR is used to separate the channels from the wideband signal. The features required for using the same hardware to switch between different standards are reconfigurability and low complexity. To achieve this, we use a variable bandwidth filter (VBF) with facility for the reduction and enhancement of the bandwidth, without changing the filter coefficients. This paper proposes an optimal and multiplier-less implementation of a baseband channel filter for supporting the bandwidth requirements of various wireless communication standards. This paper also discusses the concept for using it as a multi-band SDR channelizer for the direct conversion of signals from a wideband input to the baseband signal without using an intermediate stage. Frequency response masking (FRM) filter with continuous coefficients is designed and modified harmony search algorithm is used for finding the optimal canonic signed digit representation for the multiplier-less implementation. This reduces the complexity and power consumption. The VBF with the optimized FRM filter is evaluated for the selectable bandwidths starting from 1.25 to 8MHz, which covers the bandwidth requirements of a wide range of wireless communication standards.

VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers

This paper proposes a novel algebraic integer (AI) based multi-encoding of Daubechies-4 and -6 2-D wavelet filters having error-free integer-based computation. Digital VLSI architectures employing parallel channels are proposed, physically realized and tested. The multi-encoded AI framework allows a multiplication-free and computationally accurate architecture. It also guarantees a noise-free computation throughput the multi-level multi-rate 2-D filtering operation. A single final reconstruction step (FRS) furnishes filtered and down-sampled image outputs in fixed-point, resulting in low levels of quantization noise. Comparisons are provided between Daubechies-4 and -6 designs in terms of SNR, PSNR, hardware structure, and power consumptions, for different word lengths. SNR and PSNR improvements of approximately 30% were observed in favour of AI-based systems, when compared to 8-bit fixed-point schemes (six fractional bits). Further, FRS designs based on canonical signed digit representation and on expansion factors are proposed. The Daubechies-4 and -6 4-level VLSI architectures are prototyped on a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device at 282 MHz and 146 MHz, respectively, with dynamic power consumption of 164 mW and 339 mW, respectively, and verified on FPGA chip using an ML605 platform.

Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression

The canonical signed digit (CSD) representation of constant coefficients is a unique signed data representation containing the fewest number of nonzero bits. Consequently, for constant multipliers, the number of additions and subtractions is minimized by CSD representation of constant coefficients. This technique is mainly used for finite impulse response (FIR) filter by reducing the number of partial products. In this paper, we use CSD with a novel common subexpression elimination (CSE) scheme on the optimal Loeffler algorithm for the computation of discrete cosine transform (DCT). To meet the challenges of low-power and high-speed processing, we present an optimized image compression scheme based on two-dimensional DCT. Finally, a novel and a simple reconfigurable quantization method combined with DCT computation is presented to effectively save the computational complexity. We present here a new DCT architecture based on the proposed technique. From the experimental results obtained from the FPGA prototype we find that the proposed design has several advantages in terms of power reduction, speed performance, and saving of silicon area along with PSNR improvement over the existing designs as well as the Xilinx core.

Design of frequency response masking FIR filter in the Canonic Signed Digit space using modified Artificial Bee Colony algorithm

Frequency response masking (FRM) technique along with the Canonic Signed Digit (CSD) representation is a good alternative for the design of a computationally efficient, sharp transition width, high speed finite impulse response (FIR) filter. This paper proposes two novel approaches for the joint optimization of an FRM FIR digital filter in the CSD space. The first approach uses the recently emerged Artificial Bee Colony (ABC) algorithm and the second approach uses the Differential Evolution (DE) algorithm. In this paper, both the algorithms are modified in such a way that, they are suitable for the solution of the optimization problem posed, in which the search space consists of integers and the objective function is nonlinear. The optimization variables are encoded such that they permit the reduction in computational cost. The salient feature of the above approaches is the reduced computational complexity while obtaining good performance. Simulation results show that the ABC based design technique performs better than that using DE, which in turn outperforms the one using integer coded genetic algorithm (GA). The proposed optimization approaches can be extended to the solution of integer programming problems in other engineering disciplines also.

Optimal design of CSD coefficient FIR filters subject to number of nonzero digits

AbstractIn the hardware implementation of FIR (Finite Impulse Response) digital filters, it is desirable to reduce the total number of nonzero digits used for representation of the filter coefficients. In general, the design problem of FIR filters with CSD (Canonical Signed Digit) representation, which is efficient for reduction of the number of multiplier units, is often treated as a 0–1 combinational problem. In such problems, certain difficult constraints hinder linearization of the problem. Although many kinds of heuristic approaches have been used to solve the problem, the solutions obtained in such a manner cannot be guaranteed to be optimal. In this paper, we attempt to formulate the design problem as a 0–1 mixed integer linear programming problem and to solve it by using the branch and bound technique, which is a powerful method for solving integer programming problems. Several design examples are presented to illustrate the efficient performance of the proposed method. © 2011 Wiley Periodicals, Inc. Electron Comm Jpn, 94(6): 10–16, 2011; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/ecj.10331

Fast and VLSI efficient binary-to-CSD encoder using bypass signal

The generation of a canonical signed digit representation from a binary representation is revisited. Based on the property that each nonzero digit is surrounded by a zero digit, a hardware-efficient conversion method using bypass instead of carry propagation is proposed. The proposed method requires less area per digit and the required bypass signal can be generated or propagated with only a single NOR gate. It is shown that the proposed converter outperforms previous converters and a look-ahead circuitry to speed up the generation of bypass signals is also proposed.

Fully synthesised decimation filter for delta-sigma A/D converters

Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm2 and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filter does not have process-dependent ROM or RAM circuits.

An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth

It is well known that common subexpression elimination techniques minimize the two main cost metrics namely logic operators and logic depths in realizing finite impulse response (FIR) filters. Two classes of common subexpressions occur in the canonic signed digit representation of filter coefficients, called the horizontal and the vertical subexpressions. Previous works have not addressed the trade-offs in using these two types of subexpressions on the logic depth and the number of logic operators of coefficient multipliers. In this paper, we analyze the impact of the horizontal and the vertical common subexpression elimination techniques on reducing the logic depth and number of logic operators in FIR filters. Further, we present an algorithm to optimize the common subexpression elimination that produces FIR filters with fewer numbers of logic operators when compared with other common subexpression elimination algorithms in literature. The design examples show that the average reduction of logic operators achieved using our method over the weight-2 horizontal common subexpression elimination method which produced the best trade-off between logic operators and logic depth (contention resolution algorithm, CRA-2 [F. Xu, C.-H. Chang, C.-C. Jong, Contention resolution algorithm for common subexpression elimination in digital filter design, IEEE Trans. Circuit Syst. II 52(10) (2005) 695–700 (October)]) is 15%. This reduction of logic operators is achieved without any increase in the logic depth. When compared with the recently proposed multiple adder graph (MAG) algorithm [Jeong-Ho Han, In-Cheol Park, FIR filter synthesis considering multiple adder graphs for a coefficient, IEEE Trans. Comput.-Aid. Design Integ. Circuit Syst. 27(5) (2008) 958–962 (May)], the average reduction of logic operators obtained using our method is 5% and the reduction of logic depth is 25%.

Optimal Design of CSD Coefficient FIR Filters Subject to Number of Nonzero Digits

In a hardware implementation of FIR(Finite Impulse Response) digital filters, it is desired to reduce a total number of nonzero digits used for a representation of filter coefficients. In general, a design problem of FIR filters with CSD(Canonic Signed Digit) representation, which is efficient one for the reduction of numbers of multiplier units, is often considered as one of the 0-1 combinational problems. In such the problem, some difficult constraints make us prevent to linearize the problem. Although many kinds of heuristic approaches have been applied to solve the problem, the solution obtained by such a manner could not guarantee its optimality. In this paper, we attempt to formulate the design problem as the 0-1 mixed integer linear programming problem and solve it by using the branch and bound technique, which is a powerful method for solving integer programming problem. Several design examples are shown to present an efficient performance of the proposed method.

Low Power Realization and Synthesis of Higher-Order FIR Filters Using an Improved Common Subexpression Elimination Method

The complexity of Finite Impulse Response (FIR) filters is mainly dominated by the number of adders (subtractors) used to implement the coefficient multipliers. It is well known that Common Subexpression Elimination (CSE) method based on Canonic Signed Digit (CSD) representation considerably reduces the number of adders in coefficient multipliers. Recently, a binary-based CSE (BSE) technique was proposed, which produced better reduction of adders compared to the CSD-based CSE. In this paper, we propose a new 4-bit binary representation-based CSE (BCSE-4) method which employs 4-bit Common Subexpressions (CSs) for implementing higher order low-power FIR filters. The proposed BCSE-4 offers better reduction of adders by eliminating the redundant 4-bit CSs that exist in the binary representation of filter coefficients. The reduction of adders is achieved with a small increase in critical path length of filter coefficient multipliers. Design examples show that our BCSE-4 gives an average power consumption reduction of 5.2% and 6.1% over the best known CSE method (BSE, NR-SCSE) respectively, when synthesized with TSMC-0.18 μm technology. We show that our BCSE-4 offers an overall adder reduction of 6.5% compared to BSE without any increase in critical path length of filter coefficient multipliers.

Hamming weight pyramid – A new insight into canonical signed digit representation and its applications

Signed-power-of-two terms are widely used in design automation algorithms for digital filter synthesis and optimization, linear transformation and other multiple constant multiplication problems. In these applications, the computation efficiency or solution quality tends to degrade with the number of nonzero digits in the signed digit representation of the a priori fixed coefficients. This paper provides a new perspective to interpret the hamming weights of fixed-point coefficients represented in signed-power-of-two terms with minimal number of nonzero digits, called the minimal signed digit (MSD) representation. A new hamming weight pyramid (HWP) is proposed to succinctly compress the information about the distribution of the hamming weights of canonical signed digit (CSD) representation in a visually appealing manner for analysis and synthesis. CSD is a unique and popularly used subset of the general MSD representation. Many interesting properties of CSD are uncovered in this regularly structured HWP. These properties are exploited to develop a novel and elegant algorithm for the direct conversion of decimal number to CSD representation. We also show that the HWP can also be employed to overcome the limit imposed on the word length of the coefficients for the reduced adder graph (RAG) algorithm and filter coefficient synthesis.

Simplified Design of Constant Coefficient Multipliers

In many digital signal processing algorithms, e.g., linear transforms and digital filters, the multiplier coefficients are constant. Hence, it is possible to implement the multiplier using shifts, adders, and subtracters. In this work two approaches to realize constant coefficient multiplication with few adders and subtracters are presented. The first yields optimal results, i.e., a minimum number of adders and subtracters, but requires an exhaustive search. Compared with previous optimal approaches, redundancies in the exhaustive search cause the search time to be drastically decreased. The second is a heuristic approach based on signed-digit representation and subexpression sharing. The results for the heuristic are worse in only approximately 1% of all coefficients up to 19 bits. However, the optimal approach results in several different optimal realizations, from which it is possible to pick the best one based on other criteria. Relations between the number of adders, possible coefficients, and number of cascaded adders are presented, as well as exact equations for the number of required full and half adder cells. The results show that the number of adders and subtracters decreases on average 25% for 19-bit coefficients compared with the canonic signed-digit representation.

Multiplierless FIR filter design algorithms

This letter concerns the design of multiplierless implementations of finite impulse response (FIR) filters to achieve minimum adder cost. Existing approaches include dependence-graph multiplier-block methods and Common Subexpression Elimination (CSE) techniques applied either to the Canonic Signed Digit (CSD) representation of the coefficients or to other Signed Digit (SD) representations. We introduce a new CSE algorithm, which searches a bounded number of Minimal Signed Digit (MSD) representations. The performance of existing algorithms and the new algorithm is compared. It is shown that the relative performance of different algorithms depends on filter length and wordlength and that the new algorithm gives significant improvements in some cases.