Candidate Codewords Research Articles

Enhancing Erasure Resilience in Reed-Solomon Codes: Theory and Applications in Data Storage Systems

Reed-Solomon (RS) codes are widely utilized in data storage and communication systems due to their robust error detection and correction capabilities. However, traditional RS codes encounter challenges in addressing the increasing data corruption rates demanded by modern storage systems. This paper aims to overcome these limitations by modifying and extending the structure of traditional RS codes, particularly enhancing their recovery capabilities in the face of significant data loss. We begin by reviewing the theoretical foundations of RS codes and existing extension methods and discussing emerging technologies integrated into RS codes. We then present detailed methodologies for RS code encoding, erasure recovery mechanisms, soft decision decoding, and interleaving coding techniques, followed by a series of experiments designed to test the proposed methods. The experimental results indicate that soft-decision decoding outperforms traditional hard-decision decoding under high signal-to-noise ratio conditions, albeit with increased computational complexity as the list of candidate codewords grows. Interleaved Reed-Solomon (IRS) coding offers improved performance under low signal-to-noise ratio conditions but may introduce additional system complexity due to the interleaving and deinterleaving processes. We conclude with a summary of the research findings, a discussion of the study’s limitations, and suggestions for future research directions.

Low-Overhead Beam Training Scheme for Extremely Large-Scale RIS in Near Field

Extremely large-scale reconfigurable intelligent surface (XL-RIS) has recently been proposed and is recognized as a promising technology that can further enhance the capacity of communication systems and compensate for severe path loss. However, the pilot overhead of beam training in XL-RIS-assisted wireless communication systems is enormous because the near-field channel model needs to be taken into account, and the number of candidate codewords in the codebook increases dramatically. To tackle this problem, we propose two deep learning-based near-field beam training schemes in XL-RIS-assisted communication systems, where deep residual networks are employed to determine the optimal near-field RIS codeword. Specifically, we first propose a far-field beam-based beam training (FBT) scheme in which the received signals of all far-field RIS codewords are fed into the neural network to estimate the optimal near-field RIS codeword. In order to further reduce the pilot overhead, a partial near-field beam-based beam training (PNBT) scheme is proposed, where only the received signals corresponding to the partial near-field XL-RIS codewords are input to the neural network. Moreover, we further propose an improved PNBT scheme to enhance the performance of beam training by fully exploring the neural network’s output. Finally, simulation results show that the proposed schemes outperform the existing beam training schemes and can reduce the beam sweeping overhead by approximately 95%.

Soft Decision Decoding with Cyclic Information Set and the Decoder Architecture for Cyclic Codes

The soft decision decoding algorithm for cyclic codes, especially the maximum likelihood (ML) decoding algorithm, can obtain significant performance superior to that of algebraic decoding, but the complexity is much higher. To deal with this problem, an improved soft decision decoding algorithm based on a cyclic information set and its efficient implementation architecture are proposed. This algorithm employs the property of the cyclic codes to generate a series of cyclic information sequences by circularly shifting, constructing the cyclic information set. Then, a limited number of candidate information sequences are efficiently generated using an iterative computation method, and the candidate codewords are generated using the very concise encoding method of the cyclic codes. Furthermore, the efficient hardware architecture based on systolic arrays is also proposed to generate candidate information sequences and to select the optimal candidate codewords. An emulation platform is constructed to verify the error correction performance and to determine the optimal decoder parameters. Emulation results indicate that, with appropriate parameter selection, the proposed decoding algorithm can achieve a bit error rate approaching the ML performance while maintaining low complexity.

Improved Hierarchical Codebook-Based Channel Estimation for mmWave Massive MIMO Systems

A novel approach is proposed to improve channel estimation accuracy in hierarchical codebook-based beam search for millimeter-wave (mmWave) massive multiple-input and multiple-output (MIMO) transmissions with channels that are accessible only through analog beamforming. Our approach is targeted at overcoming the resolution limit of directional angle estimation. In the proposed method, the data transmission beam is determined based on either two or three candidate codewords in the bottom layer and their beamforming gains. Design of the optimal beam is derived by exploiting the analytic structure of codewords in the bottom layer of the hierarchical codebook. Compared to conventional schemes used to increase the angle estimation resolution, the proposed scheme presents a higher achievable data rate in practical signal-to-noise ratio (SNR) ranges as well as superior channel estimation accuracy. This is verified through simulation results. The proposed method requires fewer codewords to be probed for beam training compared to the conventional methods, which reduces complexity.

Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link

We propose an area- and power-efficient four-level pulse amplitude modulation (PAM-4) encoder/decoder for an AC coupled link system that guarantees DC balance and limited run length. Configured as 10B6Q, input data of 10 bits are mapped to 5 quaternary symbols. One of four candidate codewords that have inverted symbols at predefined positions is selected that best satisfies the requirements of DC balance and the number of transitions. One quaternary symbol is added at the end to indicate which candidate codeword is selected. This coding scheme not only guarantees the PAM-4 DC balance but also increases transition density from 75% (PRBS) to 85.6% and limits the maximum run length down to six, thus facilitating timing recovery of the receiver. Although the input data width of 10 bits is used in this implementation, the proposed scheme can be extended to wider input data with higher coding efficiency. The proposed 10B6Q encoder is fabricated in the 40 nm CMOS technology and occupies an active area of 0.0009 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a synthesized gate count of 645. It consumes 0.23 mW at the operating clock frequency of 667 MHz.

Fast Soft Decision Decoding Algorithm for Linear Block Codes Using Permuted Generator Matrices

The Gaussian elimination algorithm is an essential part of the ordered statistics-based decoding (OSD); the algorithm is required to be executed at least once for a typical OSD algorithm, with its computational complexity serving as the lower bound of the total computational complexity. When the signal-to-noise ratio (SNR) is relatively low, the computational complexity of the Gaussian elimination algorithm can be ignored as the decoding process is relatively complex. However, with an increase in the SNR, this cannot be ignored. In this letter, we propose a fast soft decision decoding algorithm using templates that are precalculated and permuted generator matrices, enabling us to decode a received vector without having to perform the OSD algorithm. In particular, if the Hamming distance between the received vector and the candidate codeword generated by one of the templates is less than a certain threshold, we can terminate the decoding process without executing the typical OSD algorithm. This aids in reducing the computational complexity in high SNR regimes without compromising the decoding performance.

An Efficient Codebook Search Algorithm for Line Spectrum Frequency (LSF) Vector Quantization in Speech Codec

A high-performance vector quantization (VQ) codebook search algorithm is proposed in this paper. VQ is an important data compression technique that has been widely applied to speech, image, and video compression. However, the process of the codebook search demands a high computational load. To solve this issue, a novel algorithm that consists of training and encoding procedures is proposed. In the training procedure, a training speech dataset was used to build the squared-error distortion look-up table for each subspace. In the encoding procedure, firstly, an input vector was quickly assigned to a search subspace. Secondly, the candidate code word group was obtained by employing the triangular inequality elimination (TIE) equation. Finally, a partial distortion elimination technique was employed to reduce the number of multiplications. The proposed method reduced the number of searches and computation load significantly, especially when the input vectors were uncorrelated. The experimental results show that the proposed algorithm provides a computational saving (CS) of up to 85% in the full search algorithm, up to 76% in the TIE algorithm, and up to 63% in the iterative TIE algorithm. Further, the proposed method provides CS and load reduction of up to 29–33% and 67–69%, respectively, over the BSS-ITIE algorithm.

An Efficient Decoding Algorithm for Block Codes Based on the Communication Channel Reliability Information

For channel codes in communication systems, an efficient algorithm that controls error is proposed. It is an algorithm for soft decision decoding of block codes. The sufficient conditions to obtain the optimum decoding are deduced so that the efficient method which explores candidate code words can be presented. The information vector of signal space codes has isomorphic coherence. The path metric in the coded demodulator is the selected components of scaled regions. The carrier decision is derived by the normalized metric of synchronized space. An efficient algorithm is proposed based on the method. The algorithm finds out a group of candidate code words, in which the most likely one is chosen as a decoding result. The algorithm reduces the complexity, which is the number of candidate code words. It also increases the probability that the correct code word is included in the candidate code words. It is shown that both the error probability and the complexity are reduced. The positions of the first hard-decision decoded errors and the positions of the unreliable bits are carefully examined. From this examination, the candidate codewords are efficiently searched for. The aim of this paper is to reduce the required number of hard-decision decoding and to lower the block error probability.

Binary Block Codes for Noisy Channels With Unknown Offset

Decoders minimizing the Euclidean distance between the received word and the candidate codewords are known to be optimal for channels suffering from Gaussian noise. However, when the stored or transmitted signals are also corrupted by an unknown offset, other decoders may perform better. In particular, applying the Euclidean distance on normalized words makes the decoding result independent of the offset. The use of this distance measure calls for alternative code design criteria in order to get good performance in the presence of both noise and offset. In this context, various adapted versions of classical binary block codes are proposed, such as (i) cosets of linear codes, (ii) (unions of) constant weight codes, and (iii) unordered codes. It is shown that considerable performance improvements can be achieved, particularly when the offset is large compared to the noise.

Efficient Chase‐2 decoding algorithm for linear block codes

All test patterns are decoded in the conventional Chase-2 algorithm, but only a few candidate codewords are derived. In this work, a highly efficient Chase-2 decoding algorithm has been proposed, where only the test patterns that can be decoded into distinct candidate codewords are processed. It means that the total number of decoding attempts is reduced from that of the test patterns to that of the candidate codewords, which consequently reduces the complexity, especially in high signal-to-noise ratio (SNR) region. The criterion of the test pattern selection is based on the property of minimum Hamming distance, it can be expected that the proposed algorithm can be applied to all linear block codes without performance degradation compared to the conventional Chase-2 algorithm.

Soft‐input bit‐flipping decoding of generalised concatenated codes for application in non‐volatile flash memories

Error correction coding based on soft-input decoding can significantly improve the reliability of non-volatile flash memories. This work proposes a soft-input decoder for generalised concatenated (GC) codes. GC codes are well suited for error correction in flash memories for high reliability data storage. The authors propose GC codes constructed from inner extended binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon (RS) codes. The extended BCH codes enable an efficient hard-input decoding. Furthermore, a low-complexity soft-input decoding method is proposed. This bit-flipping decoder uses a fixed number of test patterns and an algebraic decoder for soft-decoding. An acceptance criterion for the final candidate codeword is proposed. Combined with error and erasure decoding of the outer RS codes, this acceptance criterion can improve the decoding performance and reduce the decoding complexity. The presented simulation results show that the proposed bit-flipping decoder in combination with outer error and erasure decoding can outperform maximum-likelihood decoding of the inner codes.

Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM)

This paper presents a new write latency reduction scheme for a Phase Change Memory (PCM) made of Multi-Level Cells (MLCs). This scheme improves over an existing scheme found in the technical literature and known as CABS. The proposed scheme is based on the utilization of a new coding arrangement for the selection of candidate codewords. The code relies on the two-step feature found in the write operation of a MLC PCM and avoids the symbol that incurs in the largest latency at a higher rate than CABS. A detailed simulation based evaluation and comparison are also pursued; the proposed scheme accomplishes improvements in write latency (for parallel writing) as well as coding rate (16/17 for the proposed scheme versus 16/18 for CABS for 16 symbols or 32-bit word). As the proposed scheme utilizes novel selection criteria for the candidates, the design of the required circuitry (encoder and decoder) has also been changed with respect to CABS; in terms of hardware, the areas of the encoder and decoder for the proposed scheme are reduced by 73 and 56 percent respectively compared with CABS.

Multi‐beam receive scheme for millimetre wave wireless communication system

Different from the conventional receive scheme for millimetre wave (mmWave) communication, this study proposes a multi-beam receive scheme to improve the quality of the received signal and enhance the robustness of the system. The authors proposal is firstly formulated as an optimisation problem, where each signal received by different beams is combined through phase compensation to harvest more transmission energy. Then the original problem is divided into a series of sub-problems and an analytical solution is further obtained for each sub-problem. Furthermore, considering the spatial sparsity of the mmWave channel, they propose further a low-computational complexity algorithm by choosing a few candidate codewords with non-negligible receive signal power. Numerical results show that their proposal achieves remarkable performance improvements even with a small size codebook and is more robust for different scenarios, especially for a non-line of sight scenario. Compared with doubling receive antennas to obtain diversity gain, their proposal obtains larger signal-to-noise ratio gain while using fewer hardware resources.

Efficient decoding of block turbo codes

Block turbo codes (BTCs) under iterative decoding are product codes showing excellent performance with reasonable complexity, whose component codes are conventionally decoded in two stages. The Chase algorithm is employed in the first stage to make a list of candidate codewords from the received vector, while the extrinsic information for iterative decoding is generated in the second stage. In this paper, we propose an efficient decoding algorithm for BTCs. The proposed algorithm can avoid a number of unnecessary hard-decision decoding operations by imposing two conditions on the Chase algorithm. Also, it simply computes the extrinsic information for the decision codeword. Numerical results demonstrate that the proposed algorithm has not only much lower computational complexity, but also a little better performance than the conventional decoding scheme based on the Chase algorithm. Furthermore, it can provide a trade-off between the performance and the computational complexity of BTCs by properly selecting a decoding parameter.

Low Complexity Syndrome-Based Decoding Algorithm Applied to Block Turbo Codes

This paper presents a technique for reducing the decoding complexity of block turbo code with an extended Hamming code as a component code. In conventional decoding algorithms, when an input vector has a zero syndrome, complexity can be reduced by using the hard-input soft-output (HISO) algorithm. Although sufficient error correction can be achieved using hard decision decoding (HDD) of a component code, conventional methods have used the soft-input soft-output (SISO) algorithm for input vectors with a single error. However, when HDD is applied to all input vectors in which the syndrome is detected as a single error, performance loss occurs owing to the occasional presence of input vectors with triple errors. To solve this problem, we used two criteria for distinguishing between instances of single and triple errors. We maximized the applied rates of the HDD-based HISO algorithm depending on whether the criteria were satisfied. The SISO algorithm was applied when the two criteria were not met. In this case, the number of HDD usages can be reduced to half by removing duplicates or unnecessary candidate codewords. Simulation results show that the proposed algorithm can considerably reduce decoding complexity without performance loss compared with conventional algorithms.

Low-Complexity Decoding of Block Turbo Codes Based on the Chase Algorithm

Block turbo codes (BTCs) are constructed by serially concatenating linear block codes and iteratively decoded by letting each component code be decoded in two stages. The Chase algorithm is employed in the first stage to make a list of candidate codewords by generating a fixed number of test sequences (TSs) and algebraically decoding them, regardless of the signal-to-noise ratio or the iteration number. In the second stage, the extrinsic information is generated for iterative decoding. In this letter, we propose a low-complexity decoding algorithm for BTCs. The proposed algorithm first checks whether an algebraic hard-decision decoder outputs a codeword for a given decoder input vector, and then adaptively applies one of the two estimation rules. Based on these two rules, the number of TSs in the proposed algorithm can be made monotonically decreasing with iterations. Numerical results demonstrate that the proposed algorithm has much lower computational complexity with a negligible performance loss, compared with the conventional decoding scheme based on the Chase algorithm.

Reliability level list-based decoding of multilevel modulated block codes

Different soft decision decoding approaches for block codes which refine the hard decision decoding have been reported. These approaches have varying degrees of complexity and performance enhancement. The reliability level list RLL-based decoding scheme for block codes directly uses the reliability of the received bit with corresponding dividend in decoding. With this scheme, it has become possible to identify the target codeword TCW directly obviating the need for forming an intermediate set of candidate codewords and then selecting the decoded codeword from them. This opens up the possibility of exploring a comprehensive generalisation of the RLL concept for any block code and any baseband scheme. Such a generalisation for block codes with M-QAM signalling scheme is established in the paper.

A High-Capacity Covering Code for Voice-Over-IP Steganography

Although steganographic transparency and embedding capacity are considered to be two conflicting objectives in the design of steganographic systems, it is possible and necessary to strike a good balance between them in Voice-over-IP steganography. In this paper, to improve steganographic transparency while maintaining relatively large embedding capacity, the authors present a (2n-1, 2n) covering code, which can hide 2n-1 bits of secret messages into 2n bits of cover messages with not more than n-bit changed. Specifically, each (2n-1)-bit secret message is first transformed into two 2n-bit candidate codewords. In embedding process, the cover message is replaced with the optimal codeword more similar with it. In this way, the embedding distortion can be largely reduced. The proposed method is evaluated by comparing with existing ones with a large number of ITU-T G.729a encoded speech samples. The experimental results show that the authors' scheme can provide good performance on both steganographic transparency and embedding capacity, and achieve better balance between the two objectives than the existing ones.

Codeword Metric Calculation Scheme for Outer Code in Overloaded MIMO-OFDM System

This paper presents a codeword metric calculation scheme in two step joint decoding of block coded signals in an overloaded multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) system. In the previous literature, the two step joint decoding scheme has been proposed for the complexity reduction of joint maximum likelihood decoding in the overloaded MIMO system. However, the two step decoding scheme has not been combined with an outer code. The selection of the candidate codewords in the inner block code may not always be able to provide the metric of a binary coded symbol for the outer code. The metric of the binary coded symbol calculated in the first stage is used in the proposed scheme. It is shown that the proposed two step decoding scheme shows better performance than a bit flipping based scheme and reduces the complexity by about 0.013 for 4 signal streams with the cost of bit error rate degradation within 0.5dB.

A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems

Due to high transmission rate requirement for optical communication systems, the growing uncertainty of received signals results in the limited transmission distance. In this paper, a decision-confined soft RS decoder chip is proposed to enhance the error correcting performance with area-efficient architectures. Instead of generating numerous possible candidate codewords and determining the most likely one as output codeword, our approach produces only one codeword by confining the degree of error location polynomial. Therefore, hardware complexity is significantly reduced by eliminating decision making unit. Moreover, an iteration-reduced RiBM algorithm is provided to enlarge the coding gain by using more least reliable positions (LRPs) in the limited operation latency. According to simulation results, our proposed soft RS (255, 239; 8) decoder with 5 LRPs outperforms 0.4 dB at 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> codeword error rate (CER) as compared to hard RS decoders. Implemented in standard CMOS 90 nm technology, the soft decoder chip can achieve 2.56 Gb/s throughput with similar complexity as a hard decoder. It can fit well for 10-40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.