CAMAC Dataway Research Articles

Multi-agent CAMAC crate controller with Trident 32-bit transputers

A CAMAC crate controller is developed where three T425-25S 32-bit transputers are installed. The crate controller (CC) conforms to the specifications of the EUR 6500e CAMAC standard. It can be used as a stand-alone CC and also as an auxiliary crate controller (ACC). The transputers on the CC are enabled to execute CAMAC dataway operations independently under the supervision of an arbitration logic. Each transputer is provided with an independent register set. Owing to the transputer, the CC's can be easily networked through the connection of serial links. The CC's in the network make accesses to front-end CAMAC modules in the individual crates in parallel, communicating with each other. Data are read from front-end CAMAC modules, stored into large memory, processed and then submitted to the network concurrently and autonomously.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The first level energy trigger of the L3 experiment. Description of the hardware

This paper describes the design and the performance of the first level energy trigger, as used in the L3 experiment at LEP. The trigger is based on energy measurements in the electromagnetic and the hadronic calorimeters and the luminosity monitors. The bunch crossing time at LEP is 22.2 μs; the information from these detectors is digitized and analyzed in 20 μs. The trigger is a fast processor, which makes use of about 350 CAMAC modules. Each of them performs a dedicated function and is connected with the other modules via front-panel buses. The CAMAC dataway is used only for initialization and checking purposes. The whole processor operates synchronously with a clock period of 60 ns. The trigger decision is mainly based on the total and electromagnetic energy in the event, on the cluster finding algorithm, which searches localized energy deposits in the calorimeters, and on the presence of a single photon, where the most of the electromagnetic energy is confined to a few crystals in the electromagnetic calorimeter. The system also includes the luminosity trigger, to detect small angle Bhabha events for the measurements of the luminosity.

High speed acquisition of multiparameter data using a Macintosh IIcx

Accelerator mass spectrometry systems based on > 3 MV tandem accelerators often use multianode ionization detectors and/or time-of-flight detectors to identify individual isotopes through multiparameter analysis. A Macintosh IIcx has been programmed to collect AMS data from a CAMAC-implemented analyzer and to display the histogrammed individual parameters and a doubleparameter array. The computer-CAMAC connection is through a NuBus to CAMAC dataway interface which allows direct addressing to all functions and registers in the crate. Asynchronous data from the rare isotope are sorted into a CAMAC memory module by a list sequence controller. Isotope switching is controlled by a one-cycle timing generator. A rate-dependent amount of time is used to transfer the data from the memory module at the end of each timing cycle. The present configuration uses 10–75 ms for rates of 500–10000 cps. Parameter analysis occurs during the rest of the 520 ms data collection cycle. Completed measurements of the isotope concentrations of each sample are written to files which are compatible with standard Macintosh databases or other processing programs. The system is inexpensive and operates at speeds comparable to those obtainable using larger computers.

The L3 energy trigger

The L3 first-level energy trigger is based on energy measurements in electromagnetic and hadronic calorimeters and in luminosity monitors. The information from these detectors is evaluated and a decision is taken in about 20 μs (the time between two bunch crossings in LEP is 22 μs). This trigger makes use of 300 CAMAC modules: an arithmetic logic unit (ALU), a BUS multiplexer (BS), a memory lookup table (MLU), a data stack (DS) and a fast encoding and readout ADC (FERA), each of them performing dedicated functions. The data are transmitted via front-panel ECL buses. The CAMAC data-way is used only for initialization and checking purposes. The system operates synchronously with a period of 60 ns.

A fast intelligent data acquisition system

A fast intelligent multiprocessor data acquisition system is described here. The system based on the MC68010 using the VME bus can acquire data via the CAMAC dataway at transfer rates up to 800 Kbytes/s. The system has a user friendly interface which builds the required assembly code needing only the CAMAC FNAs used in the experiment. In addition the system can be easily modified using the standard MC68010 assembly language to handle most preprocessing requirements. The system design will also allow for future expansion to the 32 bit word and faster instruction time of the MC68020. This expansion will allow for transfer rates well over a Mbyte/s.

Simple routing interface connecting four 12-bit analog-to-digital converters to a 16k CAMAC memory module

A simple routing unit is described which allows the simultaneous and independent storage of the output data of four 12-bit ADCs in the quarters of a 16k CAMAC memory module. During accumulation of data, the CAMAC dataway is not used. If desired, part or all of the memory may be read at any time via the CAMAC dataway for display or analysis of data.

Software System for the Operation of the TRISTAN-AR Power Supply

Many power supplies ranging from 1 KVA to 4 MVA are controlled remotely through the serial CAMAC data way. The programs for their operation have been combined to form a software system which includes functions such as current monitoring, interlock and status surveillance, current pattern data generation, current fine adjustment, data transfer and so on.

TRAQ I, a CAMAC System for Muiltichannel Data Acquisition, Storage &amp; Processing

Multichannel, high speed, signal sources generate large amounts of data which cannot be handled realtime on the camac dataway. TRAQ I is a modular CAMAC system designed to buffer and process data of this type. The system can acquire data from up to 256 sources (ADCs etc.) and store in local memory (4 Mbytes). Many different signal sources can be controlled, working in either a histogramming or sequential mode. The system's data transfer bus is designed to accommodate other modules which can pre- or postprocess the data. Pre-processors can either intercept the data flow to memory for data compaction or passively monitor, looking for signal excursions, etc. Post-processors access memory to process and rewrite the data or transmit to other devices.

A large capacity, high-speed multiparameter multichannel analysis system

A data acquisition system for recording multiparameter digital data into a large memory array at over 2.5 MHz is described. The system consists of a MOSTEK MK8600 2048K × 24-bit memory system. I/O ports to various external devices including the CAMAC dataway, a memory incrementer/adder and a daisy-chain of experiment-specific modules which calculate the memory address which is to be incremented. The design of the daisy-chain permits multiple modules and provides for easy modification as experimental needs change. The system has been designed for use in multiparameter, multichannel analysis of high-speed data gathered by position-sensitive detectors at conventional and synchrotron X-ray sources as well as for fixed energy and time-of-flight diffraction at continuous and pulsed neutron sources. Modules which have been developed to date include a buffer for two-dimensional position-sensitive detectors, a mapper for high-speed coordinate transformations, a buffered time-of-flight clock, a time-correlator for synchronized diffraction experiments, and a display unit for data bus diagnostics.

A large capacity, high-speed multiparameter multichannel analysis system

A data acquisition system for recording multiparameter digital data into a large memory array at over 2.5 MHz is described. The system consists of a MOSTEK MK8600 2048×24-bit memory system, I/O ports to various external devices including the CAMAC dataway, a memory incrementer/adder and a daisy-chain of experiment-specific modules which calculate the memory address which is to be incremented. The design of the daisy-chain permits multiple modules and provides for easy modification as experimental needs change. The system has been designed for use in multiparameter, multichannel analysis of high-speed data gathered by position-sensitive detectors at conventional and synchrotron X-ray sources as well as for fixed energy and time-of-flight diffraction at continuous and pulsed neutron sources. Modules which have been developed to date include a buffer for two-dimensional position-sensitive detectors, a mapper for high-speed coordinate transformations, a buffered time-of-flight clock, a time-correlator for synchronized diffraction experiments and a display unit for data bus diagnostics.

Compatible Extended Use of the CAMAC Dataway

A study Group of the ESONE Cmmittee has prepared proposals for extensions to the CAMAC Dataway. These extensions allow modules and controllers to exploit microprocessor technology by providing a greatly extended addressing range, logical addressing and handshake timing in a manner that is compatible with existing CAMAC equipment. This paper describes the specifications that have been prepared by the COMPEX Study Group and relates the potential application areas to those of "standard" CAMAC.

The high-speed alu for wire chambers

The high-speed ALU described can perform up to eight arithmetic/logic operations on two pairs of 8-bit wire chamber coordinates in a sequence, the instruction execution time being of 200 ns. The instruction memory is programmed from the CAMAC dataway (sixteen 16-bit words), and the instruction format is given. The card includes necessary control circuity and a standard handshaking logic for connection to the computer data channel and programmed I/O interface. The work was performed at the High Energy Laboratory, JINR, Dubna, USSR.

A fast readout and encoding system for real-time processors

A fast system of data preparation for event selection hardware processors is described in this paper. The system enables input pulses to be registered, the serial numbers and the number of triggered channels to be converted to binary code. The system consists of several 16-channel input register and priority encoder modules and of one serial-to-parallel converter or buffer. The input register and encoder modules are connected by a fast dataway to cascade then in order to increase the number of inputs to 1024 and to transmit information to the serial-to-parallel converter which has a capacity of eight 12-bit words. The binary codes of the serial numbers of the triggered channels are transferred from the serial-to-parallel converter to an arithmetic part of the processor. The time required for the selection and encoding of the serial number of each triggered channel is 25 ns. It is possible to transfer data via the CAMAC dataway as well.

An intelligent CAMAC I/O module based on the Signetics 8X300 microcontroller

An intelligent CAMAC I/O module based on the Signetics 8X300 microcontroller has been developed. Sixteen 8-bit I/O ports have been utilized; eight are dedicated to data transfer with external devices and/or processes and eight are dedicated to communication with the CAMAC dataway. Separate status and data registers are provided. The input status port (SIN) can receive up to seven individual signals from external devices or the host computer while the output status port (SOUT) can be used to provide up to seven internally graded LAMs and one bit can be used to generate a Q-response for termination of block transfers. Diagnostic software has been developed to operate on the host computer which fully tests all implemented instructions. In our application the device is used in a high-speed memory mapping scheme for data acquisition with a two-dimensional position-sensitive detector system.

Extended Use of the CAMAC Dataway

A study Group of the ESONE Committee has been exploring possible ways to extend the use of the CAMAC Dataway (1) in a manner that will maintain compatibility with existing CAMAC hardware. Major areas having attention are greatly increased addressing within a module, handshake timing on the dataway and a mechanism to allow Auxiliary Controllers to address modules in other crates. These extensions will allow those users and. manufacturers who already have a commitment to CAMAC to better exploit new devices, such as large RAMs, that are now available. This paper describes the objectives and the present progress that has been made.

A Multi-Channel Analyzer Using a Dedicated CAMAC Memory

A multi-channel analyzer composed of a dedicated CAMAC memory system has been developed. The feature is combined with flexibility of the computer utilized multi-channel analyzer and high performances of the hard-wired multi-channel analyzer. The data accumulation of the CAMAC type multichannel analyzer is performed by dedicated CAMAC modules of a MCA TIMER, a MEMORY CONTROLLER, some 4KW MEMORY's and a CRT DRIVER, which are directly connected each other as to get high data acquisition rate. The accumulated data are transfered to various kinds of read-out modules through the standard CAMAC dataway for free choice of peripheral devices. Circuit configurations and functions of the CAMAC modules and an actual multi-channel analyzer system using these CAMAC modules are described.

Interface magnetic tape station to Camac for on-line data acquisition and reduction system

A magnetic tape station (Kennedy 8107/8230) interface to a Camac dataway is described. It allows writing and reading data and also searching tape in forward and reverse directions under total computer control. The complete logic diagram and its description are presented.

Fast digital coder connected with the CAMAC dataway for hodoscope systems

A digital 32-channel BCD coder for the cases when one and only one wire in a proportional chamber was fired is described. The unit has the possibility to transfer input data via a CAMAC dataway. The maximum number of coded channels is up to 28−1 and the minimum coding time is about 160 ns.

CAMAC Dataway and Branch Highway Signal Standards

CAMAC Dataway and Branch Highway Signal Standards

Operational Characteristics of the Camac Dataway

The basic purpose of CAMAC is to provide a standardized method for transferring data and control information between instrurrentation modules and a digital controller. CAMAC encompasses both a hardware standard for housing the modular components of a system and an electrical and logical standard for the control used to effect the information transfer. The CAMAC specification contains the formally stated rules for hoth of these aspects of CAMAC. This paper concentrates on the control language and describes some of its features and uses in a less formal way than in the specification, and therefore may be useful as an introduction to the subject. Other papers in this series consider other aspects of CAMAC, including its place in the context of instrumentation systems, hardware aspects, signal standards, the Branch Highway, and coupling to computers and control systems. Here, the scope is limited to the process of information interchange within the CAMAC crate. This is a revised version of a paper previously publishled. Since the first version was published, a revised version of the CAMAC specification has been issued. This present paper is based only on the revised specification. Information on the differences between the original and revised CAMAC specifications is available.