Cadence IC Research Articles

Current-mode current-tunable four-phase quadrature oscillator

A current-mode current-tunable four-phase quadrature oscillator (QO) using current differencing transconductance amplifiers (CDTA) is presented in this paper. The proposed QO consists of three CDTAs and two grounded capacitors, which can provide four quadrature current outputs at high impedance nodes. The proposed QO has the advantages of electronically and independently control of oscillation condition and oscillation frequency. Moreover, the active and passive sensitivities of the QO are low. Cadence IC Design Tools 5.1.41 post-layout simulation results are included to confirm the theory.

Exploring the use of Cadence IC in Education

Microelectronics technologies and structures iselectronics subfield, related to the study of integrated circuitdesign and fabrication. To familiarize with this widely applicablearea, engineering students should gain practical experience, inaddition to the theoretical knowledge attained on differentmicroelectronics courses. Cadence IC is a world standard tool inthis area, applicable not only in industry, but also in academicinstitutions. The academic environment of Republic of Macedoniahas the ability to use this package through cooperation withforeign partners. Assuming that the access to the provided designkits is limited, the freely available NCSU CDK library from theNorth Carolina State University is integrated within the CadenceIC environment, and later used for educational purposes. Thebasic contribution of this paper is the systematization of themethodology for NCSU CDK library application by the studentsat FEEIT - Skopje, at both third cycle, and other levels of studies.Our general opinion is that the Cadence IC tool suite providesnovel opportunities to academia and students in many educationaland research activities.

CDTA-based electronically tunable current-mode quadrature oscillator

This paper presents two new current differencing transconductance amplifiers (CDTAs)-based electronically tunable current-mode four-phase quadrature oscillators (QO). The proposed QOs consist of two CDTAs, one resistor and two grounded capacitors, respectively, which are suitable for monolithic integration. The condition of oscillation (CO) and frequency of oscillation (FO) can be independently controlled, and the FO can be electronically tunable by adjusting the bias current of the CDTA. Moreover, the QOs can provide four quadrature output currents at high-output-impedance nodes, which enable the QOs can be connected directly to the next stage without any impedance matching requirements. Cadence IC Design Tools 5.1.41 (Cadence Design Systems Inc., San Jose, CA) post-layout simulation results and experimental evidence are included to confirm the theory.

The Design and Simulation of a CMOS Digital PLL

In this paper, the charge-pump PLL structure is well analyzed. By using top-down method, the digital PLL is designed from frequency phase detector, charge pump, loop filter, VCO to frequency divider. Based on 0.5μm CMOS mixed signal process, the schematic and layout design is finished on Cadence IC 5.1.4.1, and Hspice is used for the simulation. The layout verification and parasitic extraction is completed on industry mainstream Calibre software. Simulation results show that the digital PLL is with a 100MHz center frequency, the locking range is between 20MHz~60MHz, the locking time is less than 1.5μs, and phase noise is -105dBc/Hz. The design has implemented the digital signal lock function and it can be used as an IP hard core in the clock recovery of communication systems and frequency synthesis of digital systems.

Analogue to digital converter design for software defined radio – an optimised approach

Software defined radio (SDR) is a potential low cost future-proofed solution to the growing number of incompatible wireless standards operating in different frequency bands and different geographical zones. This paper is aimed at designing an 8 bit analogue to digital converter. An analogue-to-digital converter is an electronic integrated circuit, which converts an input analogue voltage to a digital number. The digital output may be obtained using different coding schemes. Based on the response, ADC is classified into linear and non-linear ADCs. Among the various types of ADC our contribution towards this project is the design of direct conversion ADC (flash ADC). The above mentioned ADC type has been implemented using CMOS logic style in Cadence IC 5.1.41 tool and the results have been compared with SAR ADC type in terms of speed and area efficiency. The individual modules are designed using 1.2 micron and 0.25 micron TSMC process technologies.

A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter

A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18μm and 90nm CMOS process technologies. The proposed full-adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively.

Insights and Advances on the Design of CMOS Sinh Companding Filters

The scope of this paper is to present certain insights and advances towards the synthesis and transistor-level implementation of high dynamic range (> 120 dB), micropower, CMOS Sinh companding filters. In particular, we present detailed technical insights on a recently proposed Sinh integrator which may serve as the basic building block for higher-order filter structures. The particular integrator exhibits a promising simulated linearity performance mainly because it does not rely on the complementarity of both N- and P-type MOS transistors to achieve its Class-AB operation. Rather, it is designed with single-type devices in its signal processing path. The integrator is evaluated through detailed simulation results obtained by performing both large-signal transient and periodic steady-state (PSS) analyses in Cadence IC Design Framework <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">reg</sup> with the parameters of the commercially available AMS 0.35-mum CMOS process. SNR, SNDR, IP3 and mismatch are some of the performance figures reported in this work. A detailed head-to-head comparison with a typical pseudo-differential Class-AB Log-domain integrator, designed in the same technology and with identical specifications, is also performed in order to reveal any potential benefits of the Sinh circuit paradigm.