Cache Size Research Articles

Coded Caching With Asymmetric Cache Sizes and Link Qualities: The Two-User Case

The centralized coded caching problem is studied for the two-user scenario, considering heterogeneous cache capacities at the users and private channels from the server to the users, in addition to a shared channel. Optimal caching and delivery strategies that minimize the worst-case delivery latency are presented for an arbitrary number of files. The converse proof follows from the sufficiency of file-index-symmetric caching and delivery codes, while the achievability is obtained through memory-sharing among a number of special memory-capacity pairs. The optimal scheme is shown to exploit the private link capacities by transmitting part of the corresponding user`s request in an uncoded fashion. When there are no private links, the results presented here improve upon the two known results in the literature, namely: 1) equal cache capacities and arbitrary number of files and 2) unequal cache capacities and two files. The results are then extended to the caching problem with heterogeneous distortion requirements.

Coded Caching for Heterogeneous Systems: An Optimization Perspective

In cache-aided networks, the server populates the cache memories at the users during low-traffic periods in order to reduce the delivery load during peak-traffic hours. In turn, there exists a fundamental tradeoff between the delivery load on the server and the cache sizes at the users. In this paper, we study this tradeoff in a multicast network, where the server is connected to users with unequal cache sizes and the number of users is less than or equal to the number of library files. We propose centralized uncoded placement and linear delivery schemes which are optimized by solving a linear program. Additionally, we derive a lower bound on the delivery memory tradeoff with uncoded placement that accounts for the heterogeneity in cache sizes. We explicitly characterize this tradeoff for the case of three end-users, as well as an arbitrary number of end-users when the total memory size at the users is small, and when it is large. Next, we consider a system where the server is connected to the users via rate-limited links of different capacities and the server assigns the users’ cache sizes subject to a total cache budget. We characterize the optimal cache sizes that minimize the delivery completion time with uncoded placement and linear delivery. In particular, the optimal memory allocation balances between assigning larger cache sizes to users with low capacity links and uniform memory allocation.

Secrecy Capacity-Memory Tradeoff of Erasure Broadcast Channels

This paper derives upper and lower bounds on the secrecy capacity-memory tradeoff of a wiretap erasure broadcast channel (BC) with ${\mathsf{K}}_{w} $ weak receivers and ${\mathsf {K}}_{s} $ strong receivers, where weak receivers and strong receivers have the same erasure probabilities and cache sizes, respectively. The lower bounds are achieved by the schemes that meticulously combine joint cache-channel coding with wiretap coding and key-aided one-time pads. The presented upper bound holds more generally for arbitrary degraded BCs and arbitrary cache sizes. When only weak receivers have cache memories, upper and lower bounds coincide for small and large cache memories, thus providing the exact secrecy capacity-memory tradeoff for this setup. The derived bounds further allow us to conclude that the secrecy capacity is positive even when the eavesdropper is stronger than all the legitimate receivers with cache memories. Moreover, they show that the secrecy capacity-memory tradeoff can be significantly smaller than its non-secure counterpart, but it grows much faster when cache memories are small. This paper also presents a lower bound on the global secrecy capacity-memory tradeoff where one is allowed to optimize the cache assignment subject to a total cache budget. It is close to the best known lower bound without secrecy constraint. For small total cache budget, the global secrecy capacity-memory tradeoff is achieved by assigning all the available cache memory uniformly over all the receivers if the eavesdropper is stronger than all the legitimate receivers, and it is achieved by assigning the cache memory uniformly only over the weak receivers if the eavesdropper is weaker than the strong receivers.

Cache-aware algorithm for multidimensional correlations

In the paper discusses a speed of a convolution or correlation functions in case of a big size of input data. When a data volume exceeds a cache size, a significant part of an execution time is spent on a loading data into the cache. A performance of correlation is explored an example of receiving a long radio signal by the use of comparison with a big number of patterns. To decrease this spending a method of reordering calculation and memory operations and is proposed. The method uses cache aware approach to construct cache friendly algorithms. A decreasing of execution time (in some case) achieves up to 44%

Caching mechanism for mobile edge computing in V2I networks

AbstractThe caching‐enabled mobile edge computing (MEC) system becomes increasingly crucial to the future long‐term evolution vehicle‐to‐infrastructure (LTE‐V2I) network, especially for fast delivery of popular content of delay‐sensitive applications in the backhaul capacity–limited vehicular networks. Most related studies mainly focus on computation offloading strategy design and coding caching, while the deployment strategy design of caching capacities for high‐speed vehicles has been overlooked. In this paper, we investigate the deployment problem in LTE‐V2I networks with particular consideration on high‐speed vehicles. First, in a one‐way scenario, a joint optimization framework is formulated to minimize the cache size of the MEC system, meanwhile maximizing the average downloading percentage, where the MEC system's backhaul capacities, vehicle speeds, content popularity distributions, and sides of the highway are taken into account. The impacts of LTE‐V2I system parameters, eg, vehicle speed, on the objective function are revealed through the one‐way optimization. Then, the two‐way optimization is formulated and solved by developing an iterative optimization approach based on the aforementioned one‐way scenario. Particularly, the optimal caching allocation between two ways is derived. Simulation results validate the effectiveness of the proposed approaches even with low backhaul capacities and high vehicle speed.

Economical Caching for Scalable Videos in Cache-Enabled Heterogeneous Networks

We develop the optimal economical caching schemes in cache-enabled heterogeneous networks, while delivering multimedia video services with personalized viewing qualities to mobile users. By applying scalable video coding (SVC), each video file to be requested is divided into one base layer (BL) and several enhancement layers (ELs). In order to assign different transmission tasks, the serving small-cell base stations (SBSs) are grouped into $K$ clusters. The SBSs are able to cache and cooperatively transmit BL and EL contents to the user. We analytically derive expressions for successful transmission probability and ergodic service rate, and then the closed-form expression for EConomical Efficiency (ECE) is obtained. In order to enhance the ECE performance, we formulate the ECE optimization problems for two cases. In the first case, with equal cache size equipped at each SBS, the layer caching indicator is determined. Since this problem is NP-hard, after the l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> -norm approximation, the discrete optimization variables are relaxed to be continuous, and this relaxed problem is convex. Next, based on the optimal solution derived from the relaxed problem, we devise a greedy-strategy based heuristic algorithm to achieve the near-optimal layer caching indicators. In the second case, the cache size for each SBS, the layer size, and the layer caching indicator are jointly optimized. This problem is a mixed integer programming problem, which is more challenging. To effectively solve this problem, the original ECE maximization problem is divided into two subproblems. These two subproblems are iteratively solved until the original optimization problem is convergent. Numerical results verify the correctness of the theoretical derivations. Additionally, compared to the most popular layer placement strategy, the performance superiority of the proposed SVC-based caching schemes is testified.

Synergy: A Hypervisor Managed Holistic Caching System

Efficient system-wide memory management is an important challenge for over-commitment based hosting in virtualized systems. Due to the limitation of memory domains considered for sharing, current deduplication solutions simply cannot achieve system-wide deduplication. Popular memory management techniques like sharing and ballooning enable important memory usage optimizations individually. However, they do not complement each other and, in fact, may degrade individual benefits when combined. We propose $\mathsf{Synergy}$Synergy, a hypervisor managed caching system to improve memory efficiency in over-commitment scenarios. $\mathsf{Synergy}$Synergy builds on an exclusive caching framework to achieve, for the first time, system-wide memory deduplication. $\mathsf{Synergy}$Synergy also enables the co-existence of the mutually agnostic ballooning and sharing techniques within hypervisor managed systems. Finally, $\mathsf{Synergy}$Synergy implements a novel file-level eviction policy that prevents hypervisor caching benefits from being squandered away due to partial cache hits. $\mathsf{Synergy}$Synergy's cache is flexible with configuration knobs for cache sizing and data storage options, and a utility-based cache partitioning scheme. Our evaluation shows that $\mathsf{Synergy}$Synergy consistently uses 10 to 75 percent lesser memory by exploiting system-wide deduplication as compared to inclusive caching techniques and achieves application speedup of 2x to 23x. We also demonstrate the capabilities of $\mathsf{Synergy}$Synergy to increase VM packing density and support for dynamic reconfiguration of cache partitioning policies.

Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design

In the era of short channel length, Dynamic Thermal Management (DTM) has become a challenging task for the architects and designers engineering modern Chip Multi-Processors (CMPs). Ever-increasing demand of processing power along with the developed integration technology produces CMPs with high power density, which in turn increases effective chip temperature. This increased temperature leads to increase in the reliability issues for the chip-circuitry with significant increment in leakage power consumption. Recent DTM techniques apply DVFS or Task Migration to reduce temperature at the cores, the hottest on-chip components, but often ignore the on-chip hot caches. To commensurate the high data demand of these cores, most of the modern CMPs are equipped with large multi-level on-chip caches, out of which on-chip Last Level Caches (LLCs) occupy the largest on-chip area. These LLCs are accounted for their significantly high leakage power consumption that can also potentially generate on-chip hotspots at the LLCs similar to the cores. As power consumption constructs the backbone of heat dissipation, hence, this work dynamically shrinks cache size while maintaining performance constraint to reduce LLC leakage, primarily. These turned-off cache portions further work as on-chip thermal buffers for reducing average and peak temperature of the CMP without affecting the computation. Simulation results claim that, at a minimal penalty on the performance, proposed cache-based thermal management having 8MB centralised multi-banked shared LLC gives around 5°C reduction in peak and average chip temperature, which are comparable with a Greedy DVFS policy.

The Adaptive sampling revisited

The problem of estimating the number n of distinct keys of a large collection of N data is well known in computer science. A classical algorithm is the adaptive sampling (AS). n can be estimated by R2 J , where R is the final bucket size and J is the final depth at the end of the process. Several new interesting questions can be asked about AS (some of them were suggested by P.Flajolet and popularized by J.Lumbroso). The distribution of W = log(R2 J /n) is known, we rederive this distribution in a simpler way. We provide new results on the moments of J and W. We also analyze the final cache size R distribution. We consider colored keys: assume also that among the n distinct keys, m do have color K We show how to estimate p = m n. We study keys with some multiplicity : we provide a way to estimate the total number M of some color K keys among the total number N of keys. We consider the case where we know a priori the multiplicities but not the colors. There we want to estimate the total number of keys N. An appendix is devoted to the case where the hashing function provides bits with probability different from 1/2.

Enabling On-the-Fly Hardware Tracing of Data Reads in Multicores

Software debugging is one of the most challenging aspects of embedded system development due to growing hardware and software complexity, limited visibility of system components, and tightening time-to-market. To find software bugs faster, developers often rely on on-chip trace modules with large buffers to capture program execution traces with minimum interference with program execution. However, the high volumes of trace data and the high cost of trace modules limit the visibility into the system operation to short program segments. This article introduces a new hardware/software technique for capturing and filtering read data value traces in multicores that enables a complete reconstruction of parallel program execution. The proposed technique exploits tracking of data reads in data caches and cache coherence protocol states to minimize the number of trace messages streamed out of the target platform to the software debugger. The effectiveness of the proposed technique is determined by analyzing the required trace port bandwidth and trace buffer sizes as a function of the data cache size and the number of processor cores. The results show that the proposed technique significantly reduces the required trace port bandwidth, from 12.2 to 73.9 times, when compared to the Nexus-like read data value tracing, thus enabling continuous on-the-fly data tracing at modest hardware cost.

A $Q$ -Learning-Based Proactive Caching Strategy for Non-Safety Related Services in Vehicular Networks

Content caching has brought huge potential for the provisioning of non-safety related infotainment services in future vehicular networks. Assisted by multiaccess edge computing, roadside units (RSUs) could become cache-capable and offer fast caching services to moving vehicles for content providers. On the other hand, deep learning makes it possible to accurately estimate the behavior of vehicles, which enables effective proactive caching strategies. However, caching services considering both the mobility of vehicles and storage could incur increased latency and considerable cost due to the cache size needed in RSUs. In this paper, we model such a problem using Markov decision processes, and propose a heuristic ${Q}$ -learning solution together with vehicle movement predictions based on a long short-term memory network. The optimal caching strategy which minimizes the latency of caching services can be derived by our heuristic ${\varepsilon }_{{n}}$ -greedy training processes. Numerical results demonstrate that our proposed strategy can achieve better performance compared with several baselines under different prediction accuracies.

English

Multicore processors have proved to be the right choice for both desktop and server systems because it can support high performance with an acceptable budget expenditure. In this work, we have compared several works in cache contention and found that such works have identified several techniques for cache contention other than cache size including FSB, Memory Controller and prefetching hardware. We found that Distributed Intensity Online (DIO) is a very promising cache contention algorithm since it can achieve up to 2% from the optimal technique. Moreover, we propose a new framework for cache contention based on resource ontologies. In which ontologies instances will be used for communication between diverse processes instead of grasping schedules based on hardware.

A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

The advent of data proliferation and electronic devices gets low execution time and energy consumption software in the spotlight. The key to optimizing software is the correct choice, order as well as parameters of optimization transformations that has remained an open problem in compilation research for decades for various reasons. First, most of the transformations are interdependent and thus addressing them separately is not effective. Second, it is very hard to couple the transformation parameters to the processor architecture (e.g., cache size) and algorithm characteristics (e.g., data reuse); therefore, compiler designers and researchers either do not take them into account at all or do it partly. Third, the exploration space, i.e., the set of all optimization configurations that have to be explored, is huge and thus searching is impractical. In this paper, the above problems are addressed for data-dominant affine loop kernels, delivering significant contributions. A novel methodology is presented reducing the exploration space of six code optimizations by many orders of magnitude. The objective can be execution time (ET), energy consumption (E) or the number of L1, L2 and main memory accesses. The exploration space is reduced in two phases: firstly, by applying a novel register blocking algorithm and a novel loop tiling algorithm and secondly, by computing the maximum and minimum ET/E values for each optimization set. The proposed methodology has been evaluated for both embedded and general-purpose CPUs and for seven well-known algorithms, achieving high memory access, speedup and energy consumption gain values (from 1.17 up to 40) over gcc compiler, hand-written optimized code and Polly. The exploration space from which the near-optimum parameters are selected is reduced from 17 up to 30 orders of magnitude.

Distributed Caching Mechanism for Popular Services Distribution in Converged Overlay Networks

With the proliferation of portable devices, the exponential growth of the global mobile traffic brings great challenges to the traditional communication networks and the traditional wireless communication technologies. In this context, converged networks and cache-based data offloading have drawn more and more attention based on the strong correlation of services. This paper proposes a novel popular services pushing and caching scheme by using converged overlay networks. The most popular services are pushed by terrestrial broadcasting networks. And they are cached in ${n}$ router-nodes with limited cache sizes. Each router-node only interconnects with its neighbor nodes. Users are served through the router’s WiFi link. If the services requested are cached in the routers, the user can be immediately responded; otherwise, the requests can be responded through the link from cellular stations to the router. In the proposed scheme, the cache size of the router, the maximum number of requests each router can serve, and the whole-time delay are limited. Three node-selecting and dynamic programming algorithms are adopted to maximize the equivalent throughput. Analytical and numerical results demonstrate that the proposed scheme is very effective.

Cache Space Efficient Caching Scheme for Content-Centric Mobile Ad Hoc Networks

Content-centric mobile ad hoc networks (CCMAN) have been demonstrated as a potential complementary to multimedia content dissemination in future wireless networks. In-network caching is one of the key techniques in CCMAN, which can significantly reduce the network traffic load and improve the content retrieval performance. However, the challenges for caching in CCMAN are that all the wireless nodes can act as users and routers simultaneously, and the caching capability of each wireless node is limited by the cache size. So caching strategies should improve not only the caching performance but also the cache space efficiency. In this paper, we study the cache space efficient caching (CSEC) in CCMAN. First, the theoretical performance of caching in CCMAN is analyzed, the cache utility is defined and derived. Then, a CSEC scheme is proposed to improve the efficiency of cache space utilization in CCMAN. Accordingly, the analytical performance of the proposed CSEC in terms of the cache utility of CCMAN is given. The network performance of the proposed CSEC is evaluated by simulation. Simulation results show that the proposed CSEC can achieve optimal performance on cache utility, which can provide a tradeoff between the cache hit ratio performance and occupied cache space.

Integrating Fog Computing with VANETs: A Consumer Perspective

Emerging vehicular ad hoc network (VANET) applications are requiring a lot more communication and computation capabilities. Today's cloud infrastructures are not specifically designed to cope with the requirements presented by promising VANET applications. In this regard, fog computing focuses on moving computational resources toward the edge of the network to cater for these increasing processing and storage requirements. Thus, vehicular fog extends the fog computing paradigm to traditional vehicular networks that consist of several IoT devices. This overcomes the shortcomings of vehicular clouds by enabling ubiquitous vehicles, efficient communication, location-aware service provision, improved response time, and lower latency. This article presents fog-computing-based VANET architecture along with an infotainment application scenario. In the experiments, the cache size of fog nodes has been used as a parameter to evaluate its impact on different performance metrics in the fog-enabled VANET environment. We conclude the article by presenting various benefits of a fog-enabled VANET while investigating future challenges and their potential solutions.

NUCA-2A: A New Adaptive and Behavior Aware Block Placement Process

Background: The last three decades were marked by a spectacular evolution of CPUs. Both cores number on chip and shared Low Level Cache (LLC) size are increasing what makes LLC the bottleneck's system. One major weakness of future cache memory hierarchies will be to carry out memory blocks availability for vertical requests, with no consideration to horizontal proximity to cores. Simulations show that some LLC accesses cost more latency cycles than off-chip accesses. Objective: This paper presents a new adaptive and blocks behavior aware process, called NUCA-2A. It manages blocks in LLC in a purpose of reducing it's latency, and it's inner bandwidth, by studying each block's behavior, and by placing it in the most suitable location among LLC banks. Methods: LLC accesses are classified basing on each one's specific behavior. Authors establish also a two levels horizontal hierarchy in LLC. This work consists to place blocks in the zones that matches the best their behaviors. Results: In contrast to the classic S-NUCA scheme, NUCA-2A makes a reduction of up to 60,39% of global LLC latency as well as 40,74% of average inner traffic. It makes also an average speedup of 17,89 % in term of number of instructions executed by cycle. Conclusion: Behaviors study gives encouraging results. Several methods are in use in different fields to forecast a behavior basing on previous observations. We are working on a prefetching model that permits blocks migration to and from privileged banks.

PPCS: A Progressive Popularity-Aware Caching Scheme for Edge-Based Cache Redundancy Avoidance in Information-Centric Networks

This article proposes a novel chunk-based caching scheme known as the Progressive Popularity-Aware Caching Scheme (PPCS) to improve content availability and eliminate the cache redundancy issue of Information-Centric Networking (ICN). Particularly, the proposal considers both entire-object caching and partial-progressive caching for popular and non-popular content objects, respectively. In the case that the content is not popular enough, PPCS first caches initial chunks of the content at the edge node and then progressively continues caching subsequent chunks at upstream Content Nodes (CNs) along the delivery path over time, according to the content popularity and each CN position. Therefore, PPCS efficiently avoids wasting cache space for storing on-path content duplicates and improves cache diversity by allowing no more than one replica of a specified content to be cached. To enable a complete ICN caching solution for communication networks, we also propose an autonomous replacement policy to optimize the cache utilization by maximizing the utility of each CN from caching content items. By simulation, we show that PPCS, utilizing edge-computing for the joint optimization of caching decision and replacement policies, considerably outperforms relevant existing ICN caching strategies in terms of latency (number of hops), cache redundancy, and content availability (hit rate), especially when the CN’s cache size is small.

An Analysis on Caching Placement for Millimeter–Micro-Wave Hybrid Networks

In this paper, we investigate the feasibility of wireless edge caching in a hybrid millimeter-wave (mmWave)- micro-wave (μWave) network. Considering the average success probability (ASP) of file delivery as the performance metric, we derive expressions for the association probability of the typical user to the mmWave and μWave networks using stochastic geometric tools. Accordingly, we provide an upper bound on the ASP of file delivery and formulate the content caching placement scheme as an optimization problem with respect to caching probabilities, which jointly optimizes the ASP of file delivery considering both content placement and delivery phases. To simplify the non-convex problem and obtain design insights, we split it into two scenarios: 1) noise-limited and 2) interference-limited, and then propose optimal caching placement algorithms for both. We numerically evaluate the performance of the proposed schemes under several essential factors, such as content popularity, cache size, target data rate, blockages in the mmWave network, BS density, and path loss and also compare it with other common proactive caching schemes, namely uniform caching, caching M most popular files, and random caching. Numerical results demonstrate the superiority of the proposed caching scheme over others, albeit certain trade-offs.

Modelling the unsaturated hydraulic conductivity of a sandy loam soil using Gaussian process regression

Unsaturated soil hydraulic conductivity is a main parameter in agricultural and environmental studies, necessary for predicting and managing water and solute transport in soils. This parameter is difficult to measure in agricultural fields; thus, a simple and practical estimation method would be preferable, and quantitative methods (analytical and numerical) to predict the field parameters should be developed. Field experiments were conducted to collect water quality data to model the unsaturated hydraulic conductivity of a sandy loam soil. A mini disk infiltrometer (MDI) was used to measure soil infiltration rate. Input variables included electrical conductivity and the sodium adsorption ratio of irrigation water. Suction rate (pressure head), soil bulk density, and soil moisture content acted as inputs, with unsaturated soil hydraulic conductivity as output. The performance of Gaussian process regression (GPR) was analysed, with multiple linear regression (LR) and multi-layer perceptron (MLP) models used for comparison. Three performance criteria were compared: correlation coefficient (r), root mean square error (RMSE), and mean absolute error (MAE). The simulations employed the Waikato environment for knowledge analysis (WEKA) open source tool. The results indicate that the GPR with Pearson VII function-based universal kernel (PUK kernel), cache size 250007, Omega 1.0 and Sigma 1.0 performs better than other kernels when evaluating test split data, with a correlation coefficient of 0.9646. The RMSEs for GPR (PUK kernel), MLP, and LR were 1.16 × 10−04, 1.87 × 10−04, and 2.22 × 10−04 cm·s−1, respectively. Predictive data mining algorithms (DMA) enable an estimate of unknown values based on patterns in a database. Therefore, the present methodology can be put to use in predictive tools to manage water and solute transport in soils, as the GPR model provides much greater accuracy than the LR and MLP models in predicting the unsaturated hydraulic conductivity of a sandy loam soil.