Cache Memory Research Articles

The Capacity of Private Information Retrieval With Partially Known Private Side Information

We consider the problem of private information retrieval (PIR) of a single message out of $K$ messages from $N$ replicated and non-colluding databases where a cache-enabled user (retriever) of cache-size $M$ possesses side information in the form of full messages that are partially known to the databases. In this model, the user and the databases engage in a two-phase scheme, namely, the prefetching phase where the user acquires side information and the retrieval phase where the user downloads desired information. In the prefetching phase, the user receives $m_{n}$ full messages from the $n$ th database, under the cache memory size constraint $\sum _{n=1}^{N} m_{n} \leq M$ . In the retrieval phase, the user wishes to retrieve a message (which is not present in its memory) such that no individual database learns anything about the identity of the desired message. In addition, the identities of the side information messages that the user did not prefetch from a database must remain private against that database. Since the side information provided by each database in the prefetching phase is known by the providing database and the side information must be kept private against the remaining databases, we coin this model as partially known private side information . We characterize the capacity of the PIR with partially known private side information to be $C=\left ({1+\frac {1}{N}+\cdots +\frac {1}{N^{K-M-1}}}\right)^{-1}=\frac {1-\frac {1}{N}}{1-\left({\frac {1}{N}}\right)^{K-M}}$ . Interestingly, this result is the same if none of the databases knows any of the prefetched side information, i.e., when the side information is obtained externally, a problem posed by Kadhe et al. and settled by Chen-Wang-Jafar recently. Thus, our result implies that there is no loss in using the same databases for both prefetching and retrieval phases.

On the Optimality of D2D Coded Caching With Uncoded Cache Placement and One-Shot Delivery

We consider a cache-aided wireless device-to-device (D2D) network of the type introduced by Ji et al. , where the placement phase is orchestrated by a central server. We assume that the devices’ caches are filled with uncoded data, and the whole content database is contained in the collection of caches. After the cache placement phase, the files requested by the users are serviced by inter-device multicast communication. For such a system setting, we provide the exact characterization of the optimal load-memory trade-off under the assumptions of uncoded placement and one-shot delivery . In particular, we derive both the minimum average (under uniformly distributed demands) and the minimum worst-case sum-load of the D2D transmissions, for given individual cache memory size at disposal of each user. Furthermore, we show that the performance of the proposed scheme is within factor 4 of the information-theoretic optimum. Capitalizing on the one-shot delivery property, we also propose an extension of the presented scheme that provides robustness against random user inactivity.

CAPre: Code-Analysis based Prefetching for Persistent Object Stores

Data prefetching aims to improve access times to data storage systems by predicting data records that are likely to be accessed by subsequent requests and retrieving them into a memory cache before they are needed. In the case of Persistent Object Stores, previous approaches to prefetching have been based on predictions made through analysis of the store’s schema, which generates rigid predictions, or monitoring access patterns to the store while applications are executed, which introduces memory and/or computation overhead.In this paper, we present CAPre, a novel prefetching system for Persistent Object Stores based on static code analysis of object-oriented applications. CAPre generates the predictions at compile-time and does not introduce any overhead to the application execution. Moreover, CAPre is able to predict large amounts of objects that will be accessed in the near future, thus enabling the object store to perform parallel prefetching if the objects are distributed, in a much more aggressive way than in schema-based prediction algorithms. We integrate CAPre into a distributed Persistent Object Store and run a series of experiments that show that it can reduce the execution time of applications from 9% to over 50%, depending on the nature of the application and its persistent data model.

On the Complexity of Cache Analysis for Different Replacement Policies

Modern processors use cache memory, a memory access that “hits” the cache returns early, while a “miss” takes more time. Given a memory access in a program, cache analysis consists in deciding whether this access is always a hit, always a miss, or is a hit or a miss depending on execution. Such an analysis is of high importance for bounding the worst-case execution time of safety-critical real-time programs. There exist multiple possible policies for evicting old data from the cache when new data are brought in, and different policies, though apparently similar in goals and performance, may be very different from the analysis point of view. In this article, we explore these differences from a complexity-theoretical point of view. Specifically, we show that, among the common replacement policies, Least Recently Used is the only one whose analysis is NP-complete, whereas the analysis problems for the other policies are PSPACE-complete.

Aging-mitigation of cache memories by Intra-Word Bit Swapping

Aging is one of the most crucial reliability issues in recent chip fabrication technologies. Among different causes for aging, ``Bias Temperature Instability'' (BTI) imposes the highest semiconductor degradation rate to processors. Studies show that the stored values in the processors’ cache memories follow specific bit-patterns. The pattern in the data cache is due to the stored narrow-width values, however, in the instruction cache, it goes after the predefined instructions’ opcodes patterns. Hence, data and instruction cache memory cells experience different aging rates due to different stress conditions, which can lead to a decrease in ``Mean Time To Failure'' (MTTF) of the cache structures. This work proposes a new scheme that balances the stress condition over all cache memory cells by swapping bit values within each word of the cache memory. By utilizing this scheme, the aging rate of data and instruction cache memories is mitigated by up to 69% and 83%, respectively, with negligible area and performance overheads.

Trident Technology Usage in Query Search time by using Cache Memory

Big data is technology which has the users increasing day-by-day. This technology is now using in all the fields for storing the large dataset. Large datasets cannot be handled by normal database. So we are using this big data. Here in this paper we are using trident technology to avoid the issues searching query in hadoop like time. So by using cache memory is used with trident technology to perform the search operation faster than the hadoop. Here we are using the SHA algorithm while clustering the dataset.

Split Ways : An Efficient Replacement Policy for Larger Sized Cache Memory

As the data requirement of today’s application is increasing the size of the cache memory in a multicore processor is also increasing. A multicore processor has many levels of cache memory. The Last Level Cache (LLC) is normally shared by all the cores and its size must be large enough to handle today’s data intensive applications. Such larger sized set-associative LLC facing major challenges to efficiently implement the replacement policy of its sets. As the number of ways are increasing in the LLC, the replacement policy becomes a bottleneck of the system. To improve the performance of the system and to reduce the hardware overhead, in this paper we propose a simple but hardware efficient replacement policy for the larger sized LLCs. We call the techniques as SplitWays as it divides (splits) the ways of a set into multiple groups called wayGroups. Each wayGroup maintains its own replacement policy. Experimental analysis using full-system simulator found that the proposed technique reduces the hardware overhead by up to 66% without any performance degradation..

Leakage Current Analysis of 6T & 7T-SRAM using FINFETs at 22nm Technology

Persistent scaling of planar MOSFET results in increase in transistor package density and performance of chip. However at nanometer regime , it has become a very challenging issue due to the increase in the short channel effects. In nanoscaled MOSFETs, the channel loses control from gate terminal due to potential at drain. Due to this, it is difficult to turn off MOSFET completely which inturn leads to leakage currents. Since cache memory occupies more area of processors, it is difficult to reduce leakage power in microprocessors. Double gate transistors have become replacement for MOS transistors at nano level. Since FINFETs have double gates, the leakage currents can be controlled effectively than planar MOSFET. In this paper, leakage currents of 6T & 7T-SRAM memory cell are analyzed using FINFETs at 22nm technology in hspice software

Design and Implementation of 6-Stage 64-bit MIPS Pipelined Architecture

Pipelining is the concept of overlapping of multiple instructions to perform their operations to optimize the time and ability of hardware units. This paper presents the design and implementation of 6 stage pipelined architecture for High performance 64-bit Microprocessor without Interlocked Pipeline Stages (MIPS) based Reduced Instruction set computing (RISC) processor. In this work, combining efforts of pre-fetching unit, forwarding unit, Branch and Jump predicting unit, Hazard unit are used to reduce the hazards. Low power unit is used to minimize the power. Cache Memories, other devices and especially balancing pipeline stages optimize the Speed in this work. DDR4 SDRAM (Double Data Rate type4 Synchronous Dynamic Random Access Memory) controller is employed in this pipeline to achieve high-speed data transfers and to manage the entire system efficiently. Low power, Low delay Flip flops are used in pipeline registers that implicitly enhance the performance of the system. The proposed method provides better results compared to the existing models. The simulation and synthesis results of the proposed Architecture are evaluated by Xilinx 14.7 software and supporting graphs are plotted through MATLAB tool

Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS

Avionic software is the subject of stringent real time, determinism and safety constraints. Software designers face several challenges, one of them being the interferences that appear in common situations, such as resource sharing. The interferences introduce non-determinism and delays in execution time. One of the main interference prone resources are cache memories. In single-core processors, caches comprise multiple private levels. This breaks the isolation principle imposed by avionic standards, such as the ARINC-653. This standard defines partitioned architectures where one partition should never directly interfere with another one. In cache-based architectures, one partition can modify the cache content of another partition. In this paper, we propose a method based on cache locking to reduce the non-determinism and the contention on lower level memories while improving the time performances.

Hierarchical Hybrid Memory Management in OS for Tiered Memory Systems

The emerging hybrid DRAM-NVM architecture is challenging the existing memory management mechanism at the level of the architecture and operating system. In this paper, we introduce Memos, a memory management framework which can hierarchically schedule memory resources over the entire memory hierarchy including cache, channels, and main memory comprising DRAM and NVM simultaneously. Powered by our newly designed kernel-level monitoring module that samples the memory patterns by combining TLB monitoring with page walks, and page migration engine, Memos can dynamically optimize the data placement in the memory hierarchy in response to the memory access pattern, current resource utilization, and memory medium features. Our experimental results show that Memos can achieve high memory utilization, improving system throughput by around 20.0 percent; reduce the memory energy consumption by up to 82.5 percent; and improve the NVM lifetime by up to 34X.

Enhanced Methods of Mobile Cache Sharing and Pre-fetching for Required Web Contents

Availability of content over the web is increasing exponentially. The demand for content by users is also increasing rapidly. The problem of making the right content available to user at the right time will continue to be a crucial issue. As variety of contents are available and variety of users are involved, there is no single way of matching the availability versus need and deliver content instantly especially in a limited mobile environment. Hence a hybrid method is proposed in this paper by combining the different techniques such as caching, pre-fetching and cache sharing with noise reduction to improve the overall performance of mobile for optimal cache memory utilisation, efficient bandwidth utilization, network traffic reduction and latency reduction. Efficiency of mobile caching and pre-fetching is improved using Enhanced Bloom Filter technique and data is shared among cooperative users by establishing a voluntary hub. The unwanted contents in the web page can be considered as noise which is removed when storing the web pages in cache or pre-fetch area. The success of the proposed method greatly depends on the hit ratio of contents rendered locally rather than getting it from server. In order to reduce server hits, sharing the contents of cache and pre-fetch area amongst mobile users is effective. Whenever any user requires new content, even if it is not available in browser cache or local cache of that user, the content can be rendered from the cache or pre-fetch area of collaborative mobile users rather than hitting the server. This hybrid cooperative cache sharing and pre-fetching for accessing the required contents improve the overall performance and hit ratio than the existing methods.

Secure and Efficient Location-Aided Routing Against DDOS Attack in Manet

A wireless LAN is one in which a mobile user can connect to a local area network (LAN) through a wireless (radio) connection. There are many routing protocols used in wireless networks for transmission of message, among which, Location-Aided Routing (LAR) protocol is used to find the location of destination. This may be possible using Global Positioning System (GPS) in mobile. We concentrate on other malicious attacks that would have caused tremendous loss by impairing the functionalities of the computer networks. Denial of Service (DoS) and Distributed DoS (DDoS) attacks are two of the most harmful threats to the MANET functionality. From this point of view, LAR provides a solution against DoS and DDoS attacks. LAR does not have any security mechanism, so we propose a SE_LAR technique which includes traffic analysis methods and extended OEDA method. It is helpful to analyze the traffic, to detect an overwhelming traffic, legitimate nodes, congestion on network, and snooping attacks. Mobile Ad Hoc Network (MANET) is even more vulnerable to such attacks. So, in this paper, we propose Secure Location-Aided Routing (SE_LAR). Its results are compared with existing secure routing protocols like ISE_DREAM, SE_DREAM protocols. Using the existing SE_DREAM routing protocol malicious nodes are detected by traffic analysis process which is to monitor flooding impact on MANET. The OEDA method discriminates the attacker nodes from reputable nodes by evaluating the addresses in the response signal. But, it cannot be used for dense network, and cannot detect indirect Sybil attack. So, we introduce extended OEDA method with two schemes such as by refering cache memory of neighbor node scheme, and passive Sybil node identity detection, which is incorporated with SE_LAR routing protocol. OEDA method is currently incorporated with the SE_DREAM protocol, generally better known as ISE_DREAM, to produce the route to destination substantially more robust against DDOS attack. Finally we decide using the performance parameters to find out the best alternative among the three different routing protocols. Calculation of the performance of the computation compares SE_DREAM, ISE-DREAM and SE-LAR standards, the overall performance measurements by the NS2 simulator and using the parameters. To determine the effect of network size on the total performance of these protocols, we have three different phenomena.

SIMD programming using Intel vector extensions

Single instruction multiple data (SIMD) extensions are one of the most significant capabilities of recent General Purpose Processors (GPPs) which improves the performance of applications with less hardware modification. Each GPP vendor such as HP, Sun, Intel, and AMD has its particular Instruction Set Architecture (ISA) and SIMD micro-architecture with different perspectives. Intel expanded SIMD technologies from hardware and software point of view. It has introduced SIMD technologies such as MultiMedia eXtensions (MMX), Streaming SIMD Extensions (SSE), Advanced Vector eXtensions (AVX), Fused Multiply Add (FMA) and AVX-512 sets. During micro-processors developments path, register width has been extended from 64 bits to 512 bits and number of vector registers has been increased from 8 to 32. Wider registers provide more parallelism ways and more registers reduce extra data movement to the cache memory. In order to gain the advantages of SIMD extensions, many programming approaches have been developed. Compiler Automatic Vectorization (CAV) as an implicit vectorization approach, provides simple and easy SIMDization tools. While, performance improvement of CAV is not always granted, most compilers auto-vectorize simple loops. On the other hand, for explicit vectorization, Intrinsic Programming Model (IPM) provides low-level access to vector registers for SIMDizing. However, programming with IPM requires great amount of expertise especially in low-level architecture feature, thus, choosing the suitable instructions and vectorization methodology for mapping to a certain algorithm is important. Moreover, portability, compatibility, scalability and compiler optimization might limit the advantage of IPM. Our goal in this paper is as follows. First, we provide a review of SIMD technology in general and Intel’s SIMD extensions in particular. Second, some SIMD features of Intel SIMD technologies, MMX, SSEs, AVX, and FMA in terms of ISA, vector width, and SIMD programming tools are comparatively discussed. Third, in order to compare the performance of different auto-vectorizers and IPM approaches using Intel C++ compiler (ICC), GNU Compiler Collection (GCC) and Low Level Virtual Machine (LLVM), we map and implement some representative multimedia kernels on AVX and AVX2 extensions. Finally, our experimental results show that although the performance improvement using IPM approach is higher than CAVs, programmer needs more programming efforts and knows different mapping strategists. Therefore, extending auto-vectorizers abilities to generate more efficient vectorized codes is an important issue in different compilers.

Assessment of Cache Coherence and Memory Bus by Using NESE

Assessment of Cache Coherence and Memory Bus by Using NESE

Comparing the Memory Bus and Cache Coherence with NESE

Comparing the Memory Bus and Cache Coherence with NESE

Device-to-Device Secure Coded Caching

This paper studies device to device (D2D) coded-caching with information theoretic security guarantees. A broadcast network consisting of a server, which has a library of files, and end users equipped with cache memories, is considered. Information theoretic security guarantees for confidentiality are imposed upon the files. The server populates the end user caches, after which D2D communications enable the delivery of the requested files. Accordingly, we require that a user must not have access to files it did not request, i.e., secure caching. First, a centralized coded caching scheme is provided by jointly optimizing the cache placement and delivery policies. Next, a decentralized coded caching scheme is developed that does not require the knowledge of the number of active users during the caching phase. Both schemes utilize non-perfect secret sharing and one-time pad keying, to guarantee secure caching. Furthermore, the proposed schemes provide secure delivery as a side benefit, i.e., any external entity which overhears the transmitted signals during the delivery phase cannot obtain any information about the database files. The proposed schemes provide the achievable upper bound on the minimum delivery sum rate. Lower bounds on the required transmission sum rate are also derived using cut-set arguments indicating the multiplicative gap between the lower and upper bounds. Numerical results indicate that the gap vanishes with increasing memory size. Overall, the work demonstrates the effectiveness of D2D communications in cache-aided systems even when confidentiality constraints are imposed at the participating nodes and against external eavesdroppers.

Benefits of Cache Assignment on Degraded Broadcast Channels

Degraded K-user broadcast channels (BCs) are studied when the receivers are facilitated with cache memories. Lower and upper bounds are derived on the capacity-memory tradeoff, i.e., on the largest rate of reliable communication over the BC as a function of the receivers’ cache sizes, and the bounds are shown to match for interesting special cases. The lower bounds are achieved by two new coding schemes that benefit from nonuniform cache assignments . Lower and upper bounds are also established on the global capacity-memory tradeoff, i.e., on the largest capacity-memory tradeoff that can be attained by optimizing the receivers’ cache sizes subject to a total cache memory budget. The bounds coincide when the total cache memory budget is sufficiently small or sufficiently large, where the thresholds depend on the BC statistics. For small cache memories, it is optimal to assign all the cache memory to the weakest receiver. In this regime, the global capacity-memory tradeoff grows by the total cache memory budget divided by the number of files in the system. In other words, a perfect global caching gain is achievable in this regime and the performance corresponds to a system where all the cache contents in the network are available to all receivers. For large cache memories, it is optimal to assign a positive cache memory to every receiver, such that the weaker receivers are assigned larger cache memories compared to the stronger receivers. In this regime, the growth rate of the global capacity-memory tradeoff is further divided by the number of users, which corresponds to a local caching gain. It is observed numerically that a uniform assignment of the total cache memory is suboptimal in all regimes, unless the BC is completely symmetric. For erasure BCs, this claim is proved analytically in the regime of small cache sizes.

Hadoop distributed file system mechanism for processing of large datasets across computers cluster using programming techniques

In this paper, we have proved that the HDFS I/O operations performance is getting increased by integrating the set associativity in the cache design and changing the pipeline topology using fully connected digraph network topology. In read operation, since there is huge number of locations (words) at cache compared to direct mapping the chances of miss ratio is very low, hence reducing the swapping of the data between main memory and cache memory. This is increasing the memory I/O operations performance. In Write operation instead of using the sequential pipeline we need to construct the fully connected graph using the data blocks listed from the NameNode metadata. In sequential pipeline, the data is getting copied to source node in the pipeline. Source node will copy the data to next data block in the pipeline. The same copy process will continue until the last data block in the pipeline. The acknowledgment process has to follow the same process from last block to source block. The time required to transfer the data to all the data blocks in the pipeline and the acknowledgment process is almost 2n times to data copy time from one data block to another data block (if the replication factor is n).

Generalized Degrees of Freedom of the Symmetric Cache-Aided MISO Broadcast Channel With Partial CSIT

We consider the cache-aided MISO broadcast channel (BC) in which a multi-antenna transmitter serves $K$ single-antenna receivers, each equipped with a cache memory. The transmitter has access to partial knowledge of the channel state information. For a symmetric setting, in terms of channel strength levels, partial channel knowledge levels and cache sizes, we characterize the generalized degrees of freedom (GDoF) up to a constant multiplicative factor. The achievability scheme exploits the interplay between spatial multiplexing gains and coded-multicasting gain. On the other hand, a cut-set-based argument in conjunction with a GDoF outer bound for a parallel MISO BC under channel uncertainty is used for the converse. We further show that the characterized order-optimal GDoF is also attained in a decentralized setting, where no coordination is required for content placement in the caches.