Cache Management Research Articles

Identification of WSN Compromised Nodes and Performance Degradation Prevention using Cooperative Cache

Wireless Sensor Networks (WSNs) are critical in a variety of applications such as environmental monitoring, surveillance, and healthcare. WSNs, on the other hand, are vulnerable to assaults due to their dispersed and resource-constrained nature, resulting in compromised nodes and performance deterioration. Using network characteristics analysis and cooperative cache management with data and process affinity, this study provides a unique way to identifying compromised WSN nodes and mitigating performance deterioration. The initial portion of our suggested technique focuses on finding compromised nodes using in-depth network characteristics research. This suggested system can precisely locate probable hacked nodes by monitoring metrics such as traffic patterns, node activity, and communication abnormalities. Machine learning algorithms improve the identification process by learning and evolving adaptively to identify new assault patterns. Once affected nodes have been discovered, the second component of this suggested solution leverages cooperative cache management to prevent performance deterioration. Data and process affinity is presented, in which nearby nodes share caches to effectively store and retrieve data relevant to their processing activities. This affinity-based cache collaboration increases data availability, decreases communication costs, and improves overall network performance.

Pengelolaan Cache pada Aplikasi Pencatatan Penjualan Menggunakan Fuzzy Page Replacement Algorithm

The challenges faced in website development are becoming increasingly diverse, particularly in delivering a responsive website that aligns with user preferences. Progressive Web App (PWA) is an advanced web technology that combines the advantages of mobile applications with the ease of access provided by browsers. With features such as offline access and responsiveness across various devices through the utilization of web caching, PWA can offer a better and more interactive user experience. This study aims to develop a sales recording application based on PWA, optimized using an algorithm with a fuzzy approach, namely the Fuzzy Page Replacement Algorithm (FPRA) in cache management. FPRA is applied to enhance cache efficiency through the clustering of pages based on recency, access frequency, and page reference levels using the Fuzzy C-Means algorithm. The research was conducted with a case study on the sales recording application for a fried chicken business, employing the Rapid Application Development (RAD) method for the design and construction of the application. The results indicate that FPRA successfully reduced page load time significantly, achieving up to 37% faster performance based on the average results of five tested scenarios. The implementation of FPRA in the service worker also increased the average performance score of the application by 15 points, from 56 to 71, as evaluated using the Lighthouse testing tool. Thus, the utilization of caching and the application of FPRA in cache management have been proven to enhance application performance.

Adaptive Caching Strategies for IoV Based on LTE Signal Quality Analysis

The Internet of Vehicles (IoV) enhances vehicular communication, promising better connectivity and user experiences. However, maintaining stable data delivery in dynamic vehicular environments is challenging. This paper introduces Mob-Cach, a novel mobility-aware cache management strategy that leverages real-time vehicular mobility information. Our preliminary study on LTE signal quality shows that mobility patterns significantly impact signal degradation. Based on these findings, we developed a dynamic caching framework that adapts to real-time mobility data, optimizing content delivery and network performance. Simulations demonstrate significant improvements in cache hit rates, reduced latency, and overall network efficiency. This research lays a foundation for future advancements in IoV networks, addressing the challenges of mobile and dynamic network topologies.

Program context-assisted address translation for high-capacity SSDs

As the capacity of NAND flash-based SSDs keeps increasing, it becomes crucial to design a memory-efficient address translation algorithm that offers high performance when a translation table cannot be entirely loaded in a controller DRAM. Existing flash translation layers (FTL) employ demand-based address translation which caches popular mapping information in DRAM by leveraging locality of I/O references. Owing to the lack of information about detailed behaviors of applications, however, existing demand-based FTLs often suffer from many translation-table misses and thus result in sub-optimal performance. In this paper, we propose a new Program context-AssisteDFlash Translation Layer, called PADFTL. Unlike existing FTLs which are implemented as the form of firmware, PADFTL is vertically integrated with a host-level I/O classifier which provides useful hints for an FTL in an SSD to make a better decision in managing a translation table. The host-level I/O classifier monitors unique behaviors of applications by analyzing their program contexts and categorizes I/O patterns into four types, (1) Loop, (2) Hot, (3) Sequential, and (4) Random, which are then delivered to an SSD through extended interfaces. The SSD-side module of PADFTL partitions a controller DRAM into four zones and isolates mapping information associated with different I/O patterns into separate zones. By employing cache management strategies optimized for individual zones, PADFTL can lower the overall translation-table miss ratio. To evaluate the effectiveness of PADFTL, we implement the host-level classifier in the Linux kernel and PADFTL’s FTL in a trace-driven FTL simulator. In our experimental results, compared to the state-of-the-art FTL, PADFTL increases the overall table hit ratio by 16% while reducing the address translation time by up to 20% on average.

A Machine Learning-Empowered Cache Management Scheme for High-Performance SSDs

A Machine Learning-Empowered Cache Management Scheme for High-Performance SSDs

Agile-Ant: Self-Managing Distributed Cache Management for Cost Optimization of Big Data Applications

Distributed in-memory processing frameworks accelerate application runs by caching important datasets in memory. Allocating a suitable cluster configuration for caching these datasets plays a crucial role in achieving minimal cost. We present Agile-ant, a self-managing framework that identifies important datasets and scales out the cluster memory to cache them on the fly without any human interaction, without any prior knowledge of the application, the characteristics of the input data, the specification of the computing resources and their utilization by multiple-tenants. We evaluate Agile-ant on various real-world applications. Compared with our baseline, Agile-ant reduces execution cost by 78.3% on average and provides better performance than the related work.

Dynamic task offloading and service caching based on game theory in vehicular edge computing networks

Vehicular edge computing (VEC) enables task offloading from vehicle to edge servers deployed on Road Side Units (RSUs) and to vehicle with idle resources, which is considered as a promising vehicle network architecture. However, efficient task offloading and task resource cache management in the VEC network is challenging. In this work, we formulate a joint task offloading and service caching problem (JTOSCP) for VEC with edge-vehicle cooperation, aiming to minimize the total task delay-energy value and cost value of all vehicles while guaranteeing task processing delay tolerance. The formulated JTOSCP is proven as NP-hard problem. Due to the complexity of JTOSCP, we propose a cooperative task service caching and task offloading algorithm named CO-MATCH. In this algorithm, we design the dynamic programming-based service caching (DPSC) Algorithm to incentivize edge services and volunteer vehicles to cache, which takes into account both service caching preferences and social similarity. The Many-to-One Matching Game (MOMG) Algorithm is proposed to stimulate edge device games and achieve the optimal task offloading. Then, the CO-MATCH method is proven to be stable. Simulation results demonstrate that our proposed approach can significantly improve the quality of service of user vehicles compared to the other methods.

QWLCPM: A Method for QoS-Aware Forwarding and Caching Using Simple Weighted Linear Combination and Proximity for Named Data Vehicular Sensor Network

The named data vehicular sensor network (NDVSN) has become an increasingly important area of research because of the increasing demand for data transmission in vehicular networks. In such networks, ensuring the quality of service (QoS) of data transmission is essential. The NDVSN is a mobile ad hoc network that uses vehicles equipped with sensors to collect and disseminate data. QoS is critical in vehicular networks, as the data transmission must be reliable, efficient, and timely to support various applications. This paper proposes a QoS-aware forwarding and caching algorithm for NDVSNs, called QWLCPM (QoS-aware Forwarding and Caching using Weighted Linear Combination and Proximity Method). QWLCPM utilizes a weighted linear combination and proximity method to determine stable nodes and the best next-hop forwarding path based on various metrics, including priority, signal strength, vehicle speed, global positioning system data, and vehicle ID. Additionally, it incorporates a weighted linear combination method for the caching mechanism to store frequently accessed data based on zone ID, stability, and priority. The performance of QWLCPM is evaluated through simulations and compared with other forwarding and caching algorithms. QWLCPM’s efficacy stems from its holistic decision-making process, incorporating spatial and temporal elements for efficient cache management. Zone-based caching, showcased in different scenarios, enhances content delivery by utilizing stable nodes. QWLCPM’s proximity considerations significantly improve cache hits, reduce delay, and optimize hop count, especially in scenarios with sparse traffic. Additionally, its priority-based caching mechanism enhances hit ratios and content diversity, emphasizing QWLCPM’s substantial network-improvement potential in vehicular environments. These findings suggest that QWLCPM has the potential to greatly enhance QoS in NDVSNs and serve as a promising solution for future vehicular sensor networks. Future research could focus on refining the details of its implementation, scalability in larger networks, and conducting real-world trials to validate its performance under dynamic conditions.

Optimizing CNN Hardware Acceleration with Configurable Vector Units and Feature Layout Strategies

Convolutional neural network (CNN) hardware acceleration is critical to improve the performance and facilitate the deployment of CNNs in edge applications. Due to its efficiency and simplicity, channel group parallelism has become a popular method for CNN hardware acceleration. However, when processing data involving small channels, there will be a mismatch between feature data and computing units, resulting in a low utilization of the computing units. When processing the middle layer of the convolutional neural network, the mismatch between the feature-usage order and the feature-loading order leads to a low input feature cache hit rate. To address these challenges, this paper proposes an innovative method inspired by data reordering technology, aiming to achieve CNN hardware acceleration that reuses the same multiplier resources. This method focuses on transforming the hardware acceleration process into feature organization, feature block scheduling and allocation, and feature calculation subtasks to ensure the efficient mapping of continuous loading and the calculation of feature data. Specifically, this paper introduces a convolutional algorithm mapping strategy and a configurable vector operation unit to enhance multiplier utilization for different feature map sizes and channel numbers. In addition, an off-chip address mapping and on-chip cache management mechanism is proposed to effectively improve the feature access efficiency and on-chip feature cache hit rate. Furthermore, a configurable feature block scheduling policy is proposed to strike a balance between weight reuse and feature writeback pressure. Experimental results demonstrate the effectiveness of this method. When using 512 multipliers and accelerating VGG16 at 100 MHz, the actual computing performance reaches 102.3 giga operations per second (GOPS). Compared with other CNN hardware acceleration methods, the average computing array utilization is as high as 99.88% and the computing density is higher.

Enhancing security in Software-Defined Networks: An approach to efficient ARP spoofing attacks detection and mitigation

The proliferation of Software-Defined Networks (SDNs) has introduced unparalleled flexibility and efficiency to network management, but at the same time, it has introduced new challenges in securing network infrastructures. Among these challenges, Address Resolution Protocol (ARP) spoofing attacks remain a pervasive threat, compromising network integrity and data confidentiality. In this manuscript, we present an approach to ARP spoofing mitigation within SDNs, addressing the limitations of existing methodologies. Our proposed solution employs a multifaceted strategy that combines dynamic ARP cache management, real-time traffic analysis, and adaptive flow rule orchestration. Central to our approach is a dedicated device that continuously monitors the network topology and detects any deviations from established norms. Notably, our solution adapts seamlessly to networks of varying sizes, ensuring scalability and efficacy across diverse infrastructures. One of our key contributions is the integration of a deep learning-based Deep Neural Network (DNN) model to detect and mitigate ARP spoofing attacks. Leveraging a self-generated ARP spoofing dataset from SDN environments, our model demonstrates exceptional accuracy and adaptability, enhancing the network’s capability to identify and counter such threats effectively. Our approach showcases exceptional reliability, achieving 100% accuracy rate in detection of ARP spoofing, which is crucial for sustaining network responsiveness.

Leveraging Replacement Algorithm for Improved Cache Management System

Leveraging Replacement Algorithm for Improved Cache Management System

COBRRA: COntention-aware cache Bypass with Request-Response Arbitration

In modern multi-processor systems-on-chip (MPSoCs), requests from different processor cores, accelerators, and their responses from the lower-level memory contend for the shared cache bandwidth, making it a critical performance bottleneck. Prior research on shared cache management has considered requests from cores but has ignored crucial contributions from their responses. Prior cache bypass techniques focused on data reuse and neglected the system-level implications of shared cache contention. We propose COBRRA, a novel shared cache controller policy that mitigates the contention by aggressively bypassing selected responses from the lower-level memory and scheduling the remaining requests and responses to the cache efficiently. COBRRA is able to improve the average performance of a set of 15 SPEC workloads by 49% and 33% compared to the no-bypass baseline and the best-performing state-of-the-art bypass solution, respectively. Furthermore, COBRRA reduces the overall cache energy consumption by 38% and 31% compared to the no-bypass baseline and the most energy-efficient state-of-the-art bypass solution, respectively.

DRL-Based Federated Learning for Efficient Vehicular Caching Management

DRL-Based Federated Learning for Efficient Vehicular Caching Management

모바일 저장장치 성능 향상을 위한 통합 호스트-저장장치 주소변환 테이블 캐시 관리기법

모바일 저장장치 성능 향상을 위한 통합 호스트-저장장치 주소변환 테이블 캐시 관리기법

Network Traffic Analysis as a Strategy for Cache Management

Network Traffic Analysis as a Strategy for Cache Management

CABARRE: Request Response Arbitration for Shared Cache Management

Modern multi-processor systems-on-chip (MPSoCs) are characterized by caches shared by multiple cores. These shared caches receive requests issued by the processor cores. Requests that are subject to cache misses may result in the generation of responses . These responses are received from the lower level of the memory hierarchy and written to the cache. The outstanding requests and responses contend for the shared cache bandwidth. To mitigate the impact of the cache bandwidth contention on the overall system performance, an efficient request and response arbitration policy is needed. Research on shared cache management has neglected the additional cache contention caused by responses, which are written to the cache. We propose CABARRE , a novel request and response arbitration policy at shared caches, so as to improve the overall system performance. CABARRE shows a performance improvement of 23% on average across a set of SPEC workloads compared to straightforward adaptations of state-of-the-art solutions.

Proactive Stripe Reconstruction to Improve Cache Use Efficiency of SSD-Based RAID Systems

Solid-State Drives (SSDs) exhibit different failure characteristics compared to conventional hard disk drives. In particular, the Bit Error Rate (BER) of an SSD increases as it bears more writes. Then, Parity-based Redundant Array of Inexpensive Disks (RAID) arrays composed from SSDs are introduced to address correlated failures. In the RAID-5 implementation, specifically, the process of parity generation (or update) associating with a data stripe, consists of read and write operations to the SSDs. Whenever a new update request comes to the RAID system, the related parity must be also updated and flushed onto the RAID component of SSD. Such frequent parity updates result in poor RAID performance and shorten the life-time of the SSDs. Consequently, a DRAM cache is commonly equipped accompanying with the RAID controller, called the parity cache, and used to buffer the parity chunks that are most frequently updated data, for boosting I/O performance. To better improve the use efficiency of the parity cache, this paper proposes a stripe reconstruction approach to minimize the number of parity updates on SSDs, thus boosting I/O performance of the SSD RAID system. When the currently updated stripe has both cold and hot updated data chunks, it will proactively carry out stripe reconstruction if we can find another matched stripe that also includes cold and hot update data chunks on the complementary RAID components. In the reconstruction process, we first group the cold data chunks of two matched stripes, to build a new stripe and flush the parity chunk on the RAID component. After that, the hot data chunks are organized as a new stripe as well, and its parity chunk is buffered in the parity cache. This results in better cache use efficiency, as it can reduce the number of parity updates on RAID components of SSDs, as well as proactively free up cache space for quickly absorbing subsequent write requests. In addition, the proposed method adjusts the target SSD of write requests based on stripe reconstructions through considering the I/O workload balance of all SSDs. Experimental results show that our proposal can reduce the number of parity chunk updates in SSDs by 2.3% and overall I/O latency by 12.2% on average, compared to state-of-the-art parity cache management techniques.

Catalyst: Optimizing Cache Management for Large In-memory Key-value Systems

In-memory key-value cache systems, such as Memcached and Redis, are essential in today's data centers. A key mission of such cache systems is to identify the most valuable data for caching. To achieve this, the current system design keeps track of each key-value item's access and attempts to make accurate estimation on its temporal locality. All it aims is to achieve the highest cache hit ratio. However, as cache capacity quickly increases, the overhead of managing metadata for a massive amount of small key-value items rises to an unbearable level. Put it simply, the current fine-grained, heavy-cost approach cannot continue to scale. In this paper, we have performed an experimental study on the scalability challenge of the current key-value cache system design and quantitatively analyzed the inherent issues related to the metadata operations for cache management. We further propose a key-value cache management scheme, called Catalyst , based on a highly efficient metadata structure, which allows us to make effective caching decisions in a scalable way. By offloading non-essential metadata operations to GPU, we can further dedicate the limited CPU and memory resources to the main service operations for improved throughput and latency. We have developed a prototype based on Memcached. Our experimental results show that our scheme can significantly enhance the scalability and improve the cache system performance by a factor of up to 4.3.

Adaptive Management With Request Granularity for DRAM Cache Inside nand-Based SSDs

Most flash-based solid-state drives (SSDs) adopt an on-board Dynamic Random Access Memory (DRAM) to buffer hot write data. Then, the write or overwrite operations can be absorbed by the DRAM cache, given that there is sufficient locality in the applications’ I/O access pattern, to consequently avoid flushing the write data onto underlying SSD cells. After analyzing typical real-world workloads over SSDs, we observed that the buffered data of small size requests are more likely to be re-accessed than those of large write requests. To efficiently utilize the limited space of DRAM cache, this paper proposes an adaptive request granularity-based cache management scheme for SSDs. First, we introduce a request block corresponding to a write request, as the cache management granularity, and propose a dynamic manner for classifying small and large request blocks. Next, we design three-level linked lists for supporting different routines of upgradation for small and large request blocks, once their data have been hit in the cache. At last, we present a scheme of evicting the request blocks having the minimum cost in cache replacement, by taking both factors of access hotness and time discounting into account. Experimental results show that our proposal can yield improvements on cache hits and the overall I/O latency by 21.8% and 14.7% on average, compared to state-of-the-art cache management schemes inside SSDs.

Cache Programming for Scientific Loops Using Leases

Cache management is important in exploiting locality and reducing data movement. This article studies a new type of programmable cache called the lease cache. By assigning leases, software exerts the primary control on when and how long data stays in the cache. Previous work has shown an optimal solution for an ideal lease cache. This article develops and evaluates a set of practical solutions for a physical lease cache emulated in FPGA with the full suite of PolyBench benchmarks. Compared to automatic caching, lease programming can further reduce data movement by 10% to over 60% when the data size is 16 times to 3,000 times the cache size, and the techniques in this article realize over 80% of this potential. Moreover, lease programming can reduce data movement by another 0.8% to 20% after polyhedral locality optimization.