Cache Locking Research Articles

WCET Aware Cache Locking and Task Scheduling in Single Core Embedded Systems

Task scheduling in embedded system needs the WCET (Worst-Case Execution Time) of the task to ensure that tasks can be completed before their deadline. The application of cache reduces the average case execution time of tasks but increases the difficulty of scheduling because WCET becomes difficult to determine. Cache locking is a technique to help determine the WCET of a task. In addition, applying suitable cache locking selection can reduce the WCET of a task, bring easier task scheduling and further reduce the total WCET of all tasks. In this paper, we propose an approach integrated dynamic cache locking and task scheduling in a single core embedded system. We choose the most valuable locking content for each task in limited cache capacity to determine the WCET, schedule the tasks so that all the tasks can be finished before the deadline and make the total WCET minimized. We have implemented this approach and compared it to no-cache task scheduling and non-preemption task scheduling model with LRU cache by using a set of tasks. The experimental results show that our approach achieves successfully task scheduling for all test data. Compared to no-cache task scheduling, our approach achieves the average improvements of 3.22%, 12.68%,18.96% and 19.12% for the 256B, 512B, 1KB and 2KB caches, respectively. Compared to the non-preemption task scheduling model, our approach achieves the average improvements of 1.32%, 7.27%, 10.2% and 9.13% for the 256B, 512B, 1KB and 2KB caches, respectively.

Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS

Avionic software is the subject of stringent real time, determinism and safety constraints. Software designers face several challenges, one of them being the interferences that appear in common situations, such as resource sharing. The interferences introduce non-determinism and delays in execution time. One of the main interference prone resources are cache memories. In single-core processors, caches comprise multiple private levels. This breaks the isolation principle imposed by avionic standards, such as the ARINC-653. This standard defines partitioned architectures where one partition should never directly interfere with another one. In cache-based architectures, one partition can modify the cache content of another partition. In this paper, we propose a method based on cache locking to reduce the non-determinism and the contention on lower level memories while improving the time performances.

A Survey of Techniques for Cache Locking

Cache memory, although important for boosting application performance, is also a source of execution time variability, and this makes its use difficult in systems requiring worst-case execution time (WCET) guarantees. Cache locking is a promising approach for simplifying WCET estimation and providing predictability, and hence, several commercial processors provide ability for locking cache. However, cache locking also has several disadvantages (e.g., extra misses for unlocked blocks, complex algorithms required for selection of locking contents) and hence, a careful management is required to realize the full potential of cache locking. In this article, we present a survey of techniques proposed for cache locking. We categorize the techniques into several groups to underscore their similarities and differences. We also discuss the opportunities and obstacles in using cache locking. We hope that this article will help researchers gain insight into cache locking schemes and will also stimulate further work in this area.

Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems

Cache locking is a cache management technique to preclude the replacement of locked cache contents. Cache locking is often adopted to improve cache access predictability in Worst-Case Execution Time (WCET) analysis. Static cache locking methods have been proposed recently to improve Average-Case Execution Time (ACET) performance. This article presents an approach, Branch Prediction-directed Dynamic Cache Locking (BPDCL), to improve system performance through cache conflict miss reduction. In the proposed approach, the control flow graph of a program is first partitioned into disjoint execution regions, then memory blocks worth locking are determined by calculating the locking profit for each region. These two steps are conducted during compilation time. At runtime, directed by branch predictions, locking routines are prefetched into a small high-speed buffer. The predetermined cache locking contents are loaded and locked at specific execution points during program execution. Experimental results show that the proposed BPDCL method exhibits an average improvement of 25.9%, 13.8%, and 8.0% on cache miss rate reduction in comparison to cases with no cache locking, the static locking method, and the dynamic locking method, respectively.

Combining Instruction Prefetching with Partial Cache Locking to Improve WCET in Real-Time Systems

Caches play an important role in embedded systems to bridge the performance gap between fast processor and slow memory. And prefetching mechanisms are proposed to further improve the cache performance. While in real-time systems, the application of caches complicates the Worst-Case Execution Time (WCET) analysis due to its unpredictable behavior. Modern embedded processors often equip locking mechanism to improve timing predictability of the instruction cache. However, locking the whole cache may degrade the cache performance and increase the WCET of the real-time application. In this paper, we proposed an instruction-prefetching combined partial cache locking mechanism, which combines an instruction prefetching mechanism (termed as BBIP) with partial cache locking to improve the WCET estimates of real-time applications. BBIP is an instruction prefetching mechanism we have already proposed to improve the worst-case cache performance and in turn the worst-case execution time. The estimations on typical real-time applications show that the partial cache locking mechanism shows remarkable WCET improvement over static analysis and full cache locking.

A Way Cache Locking Scheme Supported by Knowledge Based Smart Preload Effective for Low-Power Multicore Electronics

A Way Cache Locking Scheme Supported by Knowledge Based Smart Preload Effective for Low-Power Multicore Electronics

Functional-Level Energy Characterization of µC/OS-II and Cache Locking for Energy Saving

We show how to characterize the energy consumption of individual operating system (OS) functions in the μC/OS-II real time kernel running on an ARM7TDMI-based embedded system. We then derive a strategy for saving energy based on locking more energy-consuming kernel routines of μC/OS-II into the cache and reassigning cache locations to reduce cache contention between frequently invoked kernel functions. The proposed method saves about 37 percent of the energy otherwise consumed by the μC/OS-II kernel, leading to reductions of up to 5.9 percent in the total energy consumption, which includes the energy consumed by the application. © 2012 Alcatel-Lucent.