Cache Coherence Research Articles

Hybrid Shared-Buffer for Multi-Master Databases

Distributed shared buffer (DSB) is a well-known solution to support multi-master database systems. DSB involves controlling access to shared data among different nodes through a distributed shared buffer and lock-based cache coherence protocols. Existing DSB implementations resolve conflicts at the page level and lack the flexibility required by modern cloud database systems. Authors present HyBuffer which mixes rows and pages in the distributed shared buffer. It enables multiple masters to independently modify different rows on the same page, thereby enhancing concurrency and performance. HyBuffer adopts the hybrid design to track the location information of cached data. A centralized node maintains page locations indicating which masters have cached which pages, and the record locations of a cached page are maintained by the master which has cached this page. This design eliminates the need to redistribute metadata when dynamically adding or removing masters. Experimental results demonstrate that HyBuffer achieves better scalability and performance compared to existing approaches.

Upscaling Current Data Caching and Prefetching Strategies for Online Databases in Nigeria

This study investigated upscaling current data caching and prefetching strategies for online databases in Nigeria, with a focus on practical implications. The research design adopted for this study was the descriptive survey. The population comprised of all undergraduate’s library students in public tertiary institutions in Ekiti State. A simple random sampling technique was adopted to select 200 library students from Ekiti State University in the study area. The instrument used for data collection was a structured 4 Likert type questionnaire. The questionnaire was distributed to the respondents to find out the effectiveness of caching and prefetching techniques on online databases. The instrument was both face and content validated by two experts from the department of Library studies in Ekiti State University, Ado-Ekiti State. The reliability of the instrument was ensured using Pearson Product Moment Correlation formula which yielded a coefficient of 0.99. The data collected were analyzed using descriptive statistics such as mean and standard deviation. The result showed that the current caching and prefetching techniques employed in online databases are highly effective; the different access patterns have effect on the effectiveness of caching and prefetching techniques in online databases and there are impacts of cache coherence mechanisms on the efficiency of caching and prefetching techniques in online databases. It was therefore recommended that the inclusion of caching and prefetching in curriculum is important across all educational level in Nigeria, with a clear emphasis on the practical implications. In addition, caching and perfecting have come under fire for focusing mostly on computer science.

Application of Cache Coherence Protocols in Enhancing Pharmacy Management Systems

The complexity of modern pharmacy management systems mirrors challenges faced in distributed computing, particularly in ensuring data consistency across multiple locations and systems. Cache coherence protocols, widely used in computer science to manage data consistency in multiprocessor systems, offer a valuable framework for addressing similar issues in pharmacy management. This paper explores the application of cache coherence protocols to pharmacy systems, proposing a model that enhances the accuracy, reliability, and efficiency of pharmacy operations, particularly in multi-location and online pharmacy environments

Mechanizing the CMP Abstraction for Parameterized Verification

Parameterized verification is a challenging problem that is known to be undecidable in the general case. ‍is a widely-used method for parameterized verification, originally proposed by Chou, Mannava and Park in 2004. It involves abstracting the protocol to a small fixed number of nodes, and strengthening by auxiliary invariants to refine the abstraction. In most of the existing applications of CMP, the abstraction and strengthening procedures are carried out manually, which can be tedious and error-prone. Existing theoretical justification of the ‍method is also done at a high level, without detailed descriptions of abstraction and strengthening rules. In this paper, we present a formally verified theory of ‍in Isabelle/HOL, with detailed, syntax-directed procedure for abstraction and strengthening that is proven correct. The formalization also includes correctness of symmetry reduction and assume-guarantee reasoning. We also describe a tool AutoCMP for automatically carrying out abstraction and strengthening in , as well as generating Isabelle proof scripts showing their correctness. We applied the tool to a number of parameterized protocols, and discovered some inaccuracies in previous manual applications of ‍to the FLASH cache coherence protocol.

Advanced hybrid MRAM based novel GPU cache system for graphic processing with high efficiency

With the rapid development of portable computing devices and users’ demand for high-quality graphics rendering, embedded Graphics Processing Units (GPU) systems for graphics processing are increasingly turning into a key component of computer architecture to enhance computability. The cache system based on traditional static random access memory (SRAM) plays a crucial role in GPUs. But high leakage, low lifetime and poor integration problems deeply plague the science and engineering field. In the paper, a novel magnetic random access memory (MRAM) based cache architecture of GPU systems is proposed for highly efficient graphics processing and computing accelerating, with the merits of high speed, long endurance, strong interference resistance, and ultra-low power consumption. Spin transfer torque-MRAM and spin orbit torque-MRAM are utilized in off-chip and on-chip caches, respectively. A controller design scheme with prefetching modules and optimized cache coherency protocols are adopted. After testing and evaluating with multiple loads, neural network models and datasets, the simulation results show that the proposed system can achieve up to 28%, 56%, and 66.45% optimizations mostly in terms of speed, energy and leakage power, respectively.

A THREE-STEP TEACHING MODEL FOR MANY-CORE CACHE MEMORY DESIGN

The shift in processor design towards manycore architectures necessitates effective management of data in cache memories, posing challenges related to cache coherence and parallel computing. This paper proposes a three-step teaching model to meet the demand for designing cache memory for many-core systems. The steps include: 1) acquiring a comprehension of an open-source simulator like FM-SIM (Flexible Multicore Cache Simulator), 2) learning the process of collecting trace files using Pin Tools, and 3) designing and integrating a new cache memory and/or cache coherence protocol into FM-SIM to assess their efficacy. The proposed model has demonstrated its capability to enable students to make significant progress in exploring and researching modern cache memory design, particularly in the context of manycore architectures.

WrBench: Comparing Cache Architectures and Coherency Protocols on ARMv8 Many-Core Systems

wrBench: Comparing Cache Architectures and Coherency Protocols on ARMv8 Many-Core Systems

Research on Cache Coherence Protocol Verification Method Based on Model Checking

This paper analyzes the underlying logic of the processor’s behavior level code. It proposes an automatic model construction and formal verification method for the cache consistency protocol with the aim of ensuring data consistency in the processor and the correctness of the cache function. The main idea of this method is to analyze the register transfer level (RTL) code directly at the module level and variable level, and extract the key modules and key variables according to the code information. Then, based on key variables, conditional behavior statements are retrieved from the code, and unnecessary statements are deleted. The model construction and simplification of related core states are completed automatically, while also simultaneously generating the attribute library to be verified, using “white list” as the construction strategy. Finally, complete cache consistency protocol verification is implemented in the model detector UPPAAL. Ultimately, this mechanism reduces the 142 state-transition path-guided global states of the cache module to be verified into 4 core functional states driven by consistency protocol implementation, effectively reducing the complexity of the formal model, and extracting 32 verification attributes into 6 verification attributes, reducing the verification time cost by 76.19%.

SoC Protocol Implementation Verification Using Instruction-Level Abstraction (ILA) Specifications

In modern systems-on-chips (SoCs) several hardware protocols are used for communication and interaction among different modules. These protocols are complex and need to be implemented correctly for correct operation of the SoC. Therefore, protocol verification has received significant attention. However, this verification is often limited to checking high-level properties on a protocol specification or an implementation. Verifying these properties directly on an implementation faces scalability challenges due to its size and design complexity. Further, even after some high-level properties are verified, there is no guarantee that an implementation fully complies with a given specification, even if the same properties have also been checked on the specification. We address these challenges and gaps by adding a layer of component specifications, one for each component in the protocol implementation, and specifying and verifying the interactions at the interfaces between each pair of communicating components. We use the recently proposed formal model termed the Instruction-Level-Abstraction (ILA) as a component specification, which includes an interface specification for the interactions in composing different components. The use of ILA models as component specifications allows us to decompose the complete verification task into two sub-tasks – checking that the composition of ILAs is sequentially equivalent to a verified formal protocol specification, and checking that the protocol implementation is a refinement of the ILA composition. This check requires that each component implementation is a refinement of its ILA specification, and includes interface checks guaranteeing that components interact with each other as specified. We have applied the proposed ILA-based methodology for protocol verification to several third-party design case studies. These include an AXI on-chip communication protocol, an off-chip communication protocol, and a cache coherence protocol. For each system, we successfully detected bugs in the implementation, and show that the full formal verification can be completed in reasonable time and effort.

Using Local Cache Coherence for Disaggregated Memory Systems

Disaggregated memory provides many cost savings and resource provisioning benefits for current datacenters, but software systems enabling disaggregated memory access result in high performance penalties. These systems require intrusive code changes to port applications for disaggregated memory or employ slow virtual memory mechanisms to avoid code changes. Such mechanisms result in high overhead page faults to access remote data and high dirty data amplification when tracking changes to cached data at page-granularity. In this paper, we propose a fundamentally new approach for disaggregated memory systems, based on the observation that we can use local cache coherence to track applications' memory accesses transparently, without code changes, at cache-line granularity. This simple idea (1) eliminates page faults from the application critical path when accessing remote data, and (2) decouples the application memory access tracking from the virtual memory page size, enabling cache-line granularity dirty data tracking and eviction. Using this observation, we implemented a new software runtime for disaggregated memory that improves average memory access time and reduces dirty data amplification1.

Distributed Shared Memory : A Page-Based Approach

In 1986, Kai Li's PhD thesis, "Shared Virtual Memory on Loosely Coupled Microprocessors," introduced the concept of Distributed Shared Memory (DSM) systems, which has since facilitated further research in this field. One approach to implementing DSM in distributed systems is the page-based method, which utilizes virtual memory techniques to map pages of a process' address space onto the physical memory of multiple nodes. The system automatically moves pages between nodes as needed, ensuring coherence and consistency for shared page updates. Page-based DSM offers several advantages, including improved performance due to reduced communication overhead and better data locality, simplified programming models that resemble centralized systems, and improved scalability by allowing additional nodes to join the system and expand memory capacity. However, its suitability for certain distributed systems depends on their specific requirements and characteristics. Page-based DSM has been applied in various distributed systems, including high- performance computing, cloud computing, and distributed databases. Nonetheless, remote memory access overheads, cache coherence issues, and the necessity of a well-connected network remain potential limitations of this approach. Key words: Distributed memory, Shared memory, Paging, Virtual memory, memory coherence, memory consistency

DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems

Tasks in modern embedded systems share data and communicate among each other. Nonetheless, the majority of research in real-time systems either assumes that tasks do not share data or prohibits data sharing by design. Only recently, some works investigated solutions to address this limitation and enable data sharing. However, we find these works to suffer from severe limitations. In particular, proposed predictable cache coherence protocols increase the worst-case memory latency (WCL) quadratically due to coherence interference and breaks compositionality by coupling the design and timing analysis of the coherence with the underlying bus arbitration policy. In this paper, we argue that a protocol that distinguishes between non-modifying (read) and modifying (write) memory accesses is key towards reducing the effects of coherence interference on WCL. Accordingly, we propose DISCO, a discriminative coherence solution that capitalizes on this observation to 1) balance average-case performance and WCL, and 2) more importantly, achieves compositionality in the existing of coherence by enabling the decomposition of the effects from coherence and arbitration components. DISCO achieves 7.2× lower latency bounds compared to the state-of-the-art predictable coherence protocol. DISCO also achieves up to 11.4× (5.3× on average) better performance than private cache bypassing for the SPLASH-3 benchmarks.

Enhanced Multicore Performance Using Novel Thread-Aware Cache Coherence and Prefetch-Control Mechanism

We propose a hardware technique for cache coherence over the existing approaches that ensure that shared and less frequently used cache blocks bypass private caches of multiple cores. Furthermore, this manuscript proposes a mechanism to tune the aggressiveness of a data prefetcher. Increased cache hit rate and improved performance have been observed since coherence management and prefetching delays are avoided using the proposed bypassing and thread progress-aware prefetch controlling mechanism. Our approach shows around 19% improvement in cache hit rate and 29% average performance improvement over existing state-of-the-art techniques for Parsec & Splash-2 multithreaded benchmarks.

EveCheck: An Event-Driven, Scalable Algorithm for Coherent Shared Memory Verification

Cache coherence and relaxed memory consistency challenge the design verification of multicore chips. The well-known self-checking approach based on litmus tests has been successful in uncovering design errors, but it leads to limited coverage. That is why random or directed test generation approaches are used for proper coverage control, but they require a specialized checker to verify shared memory behavior. Unfortunately, the inference-based checkers that provide guarantees against false positives and false negatives are not scalable with core count (unless some memory orderings are known beforehand). On the other hand, scoreboard-based checkers are scalable, but do not offer guarantees against false diagnosis. This article proposes an event-driven algorithm that is scalable without renouncing verification quality, because it relies on direct partial order verification, on-the-fly detection of improper memory orderings, exploitation of extended observability not hampered by design optimizations, and agnostic handling of store atomicity at the implementation level. We compared the new algorithm with two scoreboard-based and one inference-based checker reported in the literature. EveCheck often reaches full error detection with half the test size required by the other checkers, has superior verification quality, and less sensitivity to test generation parameters. Its effort to detect errors was one order of magnitude inferior as compared to the inference-based checker. It did not raise false positives in correct designs, and it was able to discover all the errors studied in faulty designs.

MRCN: Throughput-Oriented Multicast Routing for Customized Network-on-Chips

The relentless proliferation of Big Data and artificial intelligence has compelled computing platform architectures to evolve into heterogeneous multicores for greater energy efficiency. A customized network-on-chip (NoC) supporting interconnection diversity is pivotal for the asymmetric data-access traffic requirements of modern heterogeneous multicore system-on-chip (SoC). A significant portion of on-chip data access comprises single-source multi-destination (SSMD) traffic, which supports barrier synchronization, multi-threading, cache coherency protocols, and deep neural network (DNN) acceleration. By amortizing SSMD traffic, multicast routing is essential for effectively utilizing communication bandwidth. One of the primary concerns in supporting multicast routing in NoCs is to circumvent the additional deadlock conditions caused by branch operations among the active routers. However, it is challenging to implement the throughput-optimized multicast routing in irregular topology-based NoCs because the deadlock conditions become highly complicated, and the Hamiltonian path required to apply the labeling rule may not exist. Two important observations were identified regarding multicast routing in customized NoCs: 1) Even if the NoC lacks a Hamiltonian path, deadlock-freedom can be guaranteed by restricting branch operations to a specific destination. 2) A variable path diversity in a custom topology can be leveraged in routing path allocation and branch. Based on these properties, this study proposes a deadlock-free and throughput-enhanced multicast routing for customized NoC (MRCN). MRCN ensures deadlock freedom by utilizing extended routing and router labeling rules. Furthermore, destination router partitioning and traffic-aware adaptive branching are incorporated to reduce packet routing hops and disperse channel traffic. The effectiveness of MRCN was verified using Noxim, a well-known cycle-accurate NoC simulator, under various topologies and traffic patterns. The simulation revealed that MRCN improved the average latency by 13.98 % and the throughput by 12.16 % under the saturated traffic conditions over the previous multicast routings in customized NoCs.

MSI-A: An Energy Efficient Approximated Cache Coherence Protocol

Energy consumption has become an essential factor in designing modern computer system architecture. Because of physical limits, the termination of Moore’s law and Dennard’s scaling has forced the computer design community to investigate new approaches to meet the requirements for computing resources. Approximate computing has emerged as a promising method for reducing energy consumption while trading a controllable quality loss. This paper asserts that an approximated cache coherence protocol preserves overall energy for computation. We can approximate the cache coherence protocol by adding approximated cache lines to a certain level without hindering the output. This paper introduces an enhanced approximated version of the MSI (Modified Shared Invalid) cache coherence protocol MSI-A (Modified Shared Invalid-Approx). We have verified MSI-A and MSI by employing LTL specifications in the NuSMV model checker. To illustrate the benefits of MSI-A, we have added DTMC (Discrete-Time Markov Chain) with PCTL (Probabilistic Computational Tree Logic). Although the PCTL proves the theory of approximation, we have also simulated the MSI-A in the TEJAS hardware simulator on PARSEC 3.0 to investigate the energy gains and cycle gains of MSI-A in varied applications. The cache lines considered to be approx are between 10 and 30 percent. Each application benefited from approximation according to its nature, and VIPS has indicated a total energy gain of 30.18 percent.

D-wash – A dynamic workload aware adaptive cache coherance protocol for multi-core processor system

In today's world, multi-processor plays the vital role in designing supercomputer, mobile phones and other wearable embedded systems. To handle power and latency issues in multicore processors, this paper proposes the workload aware adaptive cache coherence protocol in which works on the principle of the workload characterization that ranges from snooping to directory based mechanism. In this protocol, workload is characterized as low workloads and heavy workloads in which the snooping is adopted for heavy types whereas low workloads employs the directory protocol. The proposed protocol adapts dynamically cache coherence and its interconnection in the multi-processor adopting low latency and energy. For the evaluation different benchmarks such as IoMT (Internet of Medical Things) are utilized and implemented in Zync-SoC using hardware-software codesign methodology. Various parameters such as energy, latency and throughput are calculated and analyzed. Experimental results shows that the proposed protocol has achieved the 50% reduction in latency, 40% reduction in energy when compared with the other existing protocols.

Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators

Embedded systems are becoming increasingly complex and heterogeneous, featuring multiple processor cores (which might themselves be heterogeneous) as well as specialized hardware accelerators, all accessing shared memory. Many accelerators are non-coherent (i.e., do not support hardware cache coherence) because it reduces hardware complexity, cost, and power consumption, while potentially offering superior performance. However, the disadvantage of non-coherence is that the software must explicitly synchronize between accelerators and processors, and this synchronization is notoriously error-prone. We propose an analysis technique to find data races in software for heterogeneous systems that include non-coherent accelerators. Our approach builds on classical results for data race detection, but the challenge turns out to be analyzing cache behavior rather than the behavior of the non-coherent accelerators. Accordingly, our central contribution is a novel, sound (data-race-preserving) abstraction of cache behavior. We prove our abstraction sound, and then to demonstrate the precision of our abstraction, we implement it in a simple dynamic race detector for a system with a processor and a massively parallel accelerator provided by a commercial FPGA-based accelerator vendor. On eleven software examples provided by the vendor, the tool had zero false positives and was able to detect previously unknown data races in two of the 11 examples.

CoVerPlan: A Co mprehensive Ver ification Plan ning Framework Leveraging PSS Specifications

With increasing design complexity, the portability of tests across different designs and platforms becomes a key criterion for accelerating verification closure. The Portable Test and Stimulus Standard (PSS) is an emerging industry standard prepared by Accellera for system-on-chip verification and testing. It provides language constructs to create a target-agnostic representation of stimulus and test scenarios reused by various users across many levels of integration. In this article, we present CoVerPlan , a comprehensive verification framework built to explore the power of action inferencing on test models written in PSS. The proposed verification framework leverages a Boolean satisfiability problem planner to unwind the actual verification flow from the PSS specifications and automatically synthesizes target-specific constraint-random testbenches and formal assertions. CoVerPlan also carries out assertion-based verification of the synthesized properties. We demonstrate the efficacy of our proposed framework over several case studies, like the Advanced Microcontroller Bus Architecture advanced peripheral bus protocol, a simple Reduced Instruction Set Computer processor, and a cache coherence protocol.

Massively parallel computation of globally optimal shortest paths with curvature penalization

AbstractWe address the computation of paths globally minimizing an energy involving their curvature, with given endpoints and tangents at these endpoints, according to models known as the Reeds‐Shepp car (reversible and forward variants), the Euler‐Mumford elasticae, and the Dubins car. For that purpose, we numerically solve degenerate variants of the eikonal equation, on a three‐dimensional domain, in a massively parallel manner on a graphical processing unit. Due to the high anisotropy and nonlinearity of the addressed Partial Differential Equation, the discretization stencil is rather wide, has numerous elements, and is costly to generate, which leads to subtle compromises between computational cost, memory usage, and cache coherency. Accelerations by a factor 30 to 120 are obtained w.r.t a sequential implementation. The efficiency and the robustness of the method is illustrated in various contexts, ranging from motion planning to vessel segmentation and radar configuration.