Loop Tiling Research Articles

Structure discrimination in block-oriented models using linear approximations: A theoretic framework

In this paper we show that it is possible to retrieve structural information about complex block-oriented nonlinear systems, starting from linear approximations of the nonlinear system around different setpoints. The key idea is to monitor the movements of the poles and zeros of the linearized models and to reduce the number of candidate models on the basis of these observations. Besides the well known open loop single branch Wiener-, Hammerstein-, and Wiener–Hammerstein systems, we also cover a number of more general structures like parallel (multi branch) Wiener–Hammerstein models, and closed loop block oriented models, including linear fractional representation (LFR) models.

Optimal Parallelogram Selection for Hierarchical Tiling

Loop tiling is an effective optimization to improve performance of multiply nested loops, which are the most time-consuming parts in many programs. Most massively parallel systems today are organized hierarchically, and different levels of the hierarchy differ in the organization of parallelism and the memory models they adopt. To make better use of these machines, it is clear that loop nests should be tiled hierarchically to fit the hierarchical organization of the machine; however, it is not so clear what should be the exact form of these hierarchical tiles. In particular, tile shape selection is of critical importance to expose parallelism of the tiled loop nests. Although loop tiling is a well-known optimization, not much is known about tile shape selection. In this article, we study tile shape selection when the shapes are any type of parallelograms and introduce a model to relate the tile shape of the hierarchy to the execution time. Using this model, we implement a system that automatically finds the tile shapes that minimize the execution time in a hierarchical system. Our experimental results show that in several cases, the tiles automatically selected by our system outperform the most intuitive tiling schemes usually adopted by programmers because of their simplicity.

Tuning the cache memory usage in tomographic reconstruction on standard computers with Advanced Vector eXtensions (AVX).

Cache blocking is a technique widely used in scientific computing to minimize the exchange of information with main memory by reusing the data kept in cache memory. In tomographic reconstruction on standard computers using vector instructions, cache blocking turns out to be central to optimize performance. To this end, sinograms of the tilt-series and slices of the volumes to be reconstructed have to be divided into small blocks that fit into the different levels of cache memory. The code is then reorganized so as to operate with a block as much as possible before proceeding with another one. This data article is related to the research article titled Tomo3D 2.0 – Exploitation of Advanced Vector eXtensions (AVX) for 3D reconstruction (Agulleiro and Fernandez, 2015) [1]. Here we present data of a thorough study of the performance of tomographic reconstruction by varying cache block sizes, which allows derivation of expressions for their automatic quasi-optimal tuning.

Adaptation of MPDATA Heterogeneous Stencil Computation to Intel Xeon Phi Coprocessor

The multidimensional positive definite advection transport algorithm (MPDATA) belongs to the group of nonoscillatory forward-in-time algorithms and performs a sequence of stencil computations. MPDATA is one of the major parts of the dynamic core of the EULAG geophysical model. In this work, we outline an approach to adaptation of the 3D MPDATA algorithm to the Intel MIC architecture. In order to utilize available computing resources, we propose the (3 + 1)D decomposition of MPDATA heterogeneous stencil computations. This approach is based on combination of the loop tiling and fusion techniques. It allows us to ease memory/communication bounds and better exploit the theoretical floating point efficiency of target computing platforms. An important method of improving the efficiency of the (3 + 1)D decomposition is partitioning of available cores/threads into work teams. It permits for reducing inter-cache communication overheads. This method also increases opportunities for the efficient distribution of MPDATA computation onto available resources of the Intel MIC architecture, as well as Intel CPUs. We discuss preliminary performance results obtained on two hybrid platforms, containing two CPUs and Intel Xeon Phi. The top-of-the-line Intel Xeon Phi 7120P gives the best performance results, and executes MPDATA almost 2 times faster than two Intel Xeon E5-2697v2 CPUs.

Memory bandwidth optimization of SpMV on GPGPUs

It is an important task to improve performance for sparse matrix vector multiplication (SpMV), and it is a difficult task because of its irregular memory access. General purpose GPU (GPGPU) provides high computing ability and substantial bandwidth that cannot be fully exploited by SpMV due to its irregularity. In this paper, we propose two novel methods to optimize the memory bandwidth for SpMV on GPGPU. First, a new storage format is proposed to exploit memory bandwidth of GPU architecture more efficiently. The new storage format can ensure that there are as many non-zeros as possible in the format which is suitable to exploit the memory bandwidth of the GPU. Second, we propose a cache blocking method to improve the performance of SpMV on GPU architecture. The sparse matrix is partitioned into sub-blocks that are stored in CSR format.With the blocking method, the corresponding part of vector x can be reused in the GPU cache, so the time to access the global memory for vector x is reduced heavily. Experiments are carried out on three GPU platforms, GeForce 9800 GX2, GeForce GTX 480, and Tesla K40. Experimental results show that both new methods can efficiently improve the utilization of GPU memory bandwidth and the performance of the GPU.

Application-aware deduplication for performance improvement of flash memory

Deduplication in flash memory improves performance as well as reliability thanks to mitigating drawbacks of flash memory, which is done by eliminating duplicate data from flash memory. However, existing works mainly focus on efficiency of runtime data management without considering program flows. We propose a new application-aware deduplication method called unmodified region detection (URD) for flash memory. URD reconstructs loop blocks of an application program to avoid duplicate update operations, which aims to reduce the size of in-place updated data. This entails information gathering, loop reconstruction and code instrumentation phases. From experiments, we found that, in our URD scheme, block-based deduplication always improves performance regardless of the duplication degree of write traffic, while page-based deduplication obtains performance enhancement or performance degradation, depending on the duplication degree of write traffic.

Exploration of automatic optimisation for CUDA programming

Writing optimised compute unified device architecture (CUDA) program for graphic processing units (GPUs) is complex even for experts. We present a design methodology for a restructuring tool that converts C-loops into optimised CUDA kernels based on a three-step algorithm which are loop tiling, coalesced memory access and resource optimisation. A method for finding possible loop tiling solutions with coalesced memory access is developed and a simplified algorithm for restructuring C-loops into an efficient CUDA kernel is presented. In the evaluation, we implement matrix multiply (MM), matrix transpose (M-transpose), matrix scaling (M-scaling) and matrix vector multiply (MV) using the proposed algorithm. We present the analysis of the execution time and GPU throughput for the above applications, which favourably compare to other proposals. Evaluation is carried out while scaling the problem size and running under a variety of kernel configurations. The obtained speedup is about 28–35% for M-transpose compared to NVIDIA Software Development Kit, 33% speedup for MV compared to general purpose computation on graphics processing unit compiler, and more than 80% speedup for MM and M-scaling compared to CUDA-lite.

Online auto-tuning for the time-step-based parallel solution of ODEs on shared-memory systems

This article considers automatic performance tuning of time-step-based parallel solution methods for initial value problems (IVPs) of systems of ordinary differential equations (ODEs). We apply auto-tuning to the parallel execution of a class of explicit predictor–corrector (PC) methods of Runge–Kutta (RK) type on shared-memory architectures. The performance of parallel multi-threaded implementation variants of these methods depends on various factors only known at runtime, for example, the coupling structure of the ODE system to be solved, the memory access pattern resulting from this coupling structure, and the number of threads executing the program.We propose an online auto-tuning approach that exploits the time-stepping nature of ODE methods by selecting the best parallel implementation variant from a set of candidate implementations at runtime during the first time steps. Thus, the auto-tuning process is not isolated from the computation, but rather contributes to the progress of the solution process. The search space of candidate implementations is a priori reduced by estimating the synchronization overhead of each implementation variant. For implementation variants containing tiled loops, suitable tile sizes are selected using a heuristic empirical search guided by an analytical model. Runtime experiments with two different test problems show the efficiency of the online auto-tuning approach on two different shared-memory systems equipped with 48 and 1040 cores.

Modeling and Simulation of Current Source Inverter Fed Synchronous Motor in Complex Frequency Domain Taking the Transition Zone From Induction Motor to Synchronous Motor Mode into Account

Modeling of synchronous motor plays a dominant role in designing complicated drive system for different applications, especially large blower fans etc for steel industries. As synchronous motor has no inherent starting torque generally it is started as an induction motor with the help of a damper winding and it pulls into synchronism under certain conditions. The present paper exactly concentrates on this particular zone of transition from induction motor to synchronous motor mode for a current source inverter fed synchronous motor drive system. Due to complexity of synchronous motor in terms of number of windings and finite amount of air gap saliency, direct modeling of such transition zone in time domain becomes cumbersome at the first instance of modeling. That is why the modeling in complex frequency domain (s-domain) has been taken up using small perturbation model. Such a model clearly shows role of induction motor as noise function or disturbance function with respect to the open loop block diagram of synchronous motor. Such finding can be quantized in terms of important results and that is done in the present paper such that the results can help the designer for the successful design of a synchronous motor drive system.

Designing and auto-tuning parallel 3-D FFT for computation-communication overlap

This paper presents a method to design and auto-tune a new parallel 3-D FFT code using the non-blocking MPI all-to-all operation. We achieve high performance by optimizing computation-communication overlap. Our code performs fully asynchronous communication without any support from special hardware. We also improve cache performance through loop tiling. To cope with the complex trade-off regarding our optimization techniques, we parameterize our code and auto-tune the parameters efficiently in a large parameter space. Experimental results from two systems confirm that our code achieves a speedup of up to 1.76x over the FFTW library.

A new code transformation technique for nested loops

For good performance of every computer program, good cache utilization is crucial. In numerical linear algebra libraries, good cache utilization is achieved by explicit loop restructuring (mainly loop blocking), but it requires a complicated memory pattern behavior analysis. In this paper, we describe a new source code transformation called dynamic loop reversal that can increase temporal and spatial locality. We also describe a formal method for predicting cache behavior and evaluate results of the model accuracy by the measurements on a cache monitor. The comparisons of the numbers of measured cache misses and the numbers of cache misses estimated by the model indicate that the model is relatively accurate and can be used in practice.

Tile size selection revisited

Loop tiling is a widely used loop transformation to enhance data locality and allow data reuse. In the tiled code, however, tiles of different sizes can lead to significant variation in performance. Thus, selection of an optimal tile size is critical to performance of tiled codes. In the past, tile size selection has been attempted using both static analytical and dynamic empirical (auto-tuning) models. Past work using static models assumed a direct-mapped cache for the purpose of analysis and thus proved to be less robust. On the other hand, the auto-tuning models involve an exhaustive search in a large space of tiled codes. In this article, we propose a new analytical model for tile size selection that leverages the high set associativity in modern caches to minimize conflict misses. Our tile size selection model targets data reuse in multiple levels of cache. In addition, it considers the interaction of tiling with the SIMD unit in modern processors in estimating the optimal tile size. We find that these factors, not considered in previous models, are critical in developing a robust model for tile size selection. We implement our tile size selection model in a polyhedral compiler and test it on 12 benchmark kernels using two different problem sizes. Our model outperforms the previous analytical models that are based on reusing data in a single level of cache and achieves an average performance improvement of 9.7% and 20.4%, respectively, over the best square (cubic) tiles for the two problem sizes. In addition, the tile size chosen by our tile size selection algorithm is similar to the best performing size obtained through an extensive search, validating the analytical model underlying the algorithm.

Tile size selection revisited

Loop tiling is a widely used loop transformation to enhance data locality and allow data reuse. In the tiled code, however, tiles of different sizes can lead to significant variation in performance. Thus, selection of an optimal tile size is critical to performance of tiled codes.

Pipelining granularity optimization algorithm based on loop tiling

When the pipelining loop has a great number of iterations,or the size of its body is large,but the number of available threads is small,the workload between two synchronizations of a thread is so heavy,which produces pretty low degree of parallelism.The traditional trade-off approach based on loop tiling cannot handle the above situation.To solve this problem,a pipelining granularity decreasing approach based on loop tiling was proposed.The optimal pipelining granularity was obtained by building the cost model for pipelining loop and a pipelining granularity optimizing algorithm was implemented.By measuring the wavefront loops of Finite Difference Relaxation(FDR) and the representative loops of Finite Difference Time Domain(FDTD),the loops show better performance improvement by using the proposed algorithm than the traditional one.

Validation of a Faulted Rotor Induction Machine Model With an Insightful Geometrical Interpretation of Physical Quantities

Many proposals about induction-machine broken-bar detection can be found in the literature. Disturbances that affect phase currents, current space vector, power, fluxes, torque, and speed have been utilized to diagnose mains-supplied machines. Nevertheless, there is still disagreement about how the fault signatures of the different variables correlate with the actual fault and how they depend on the operating conditions. This paper presents a simple but effective analytical representation of induction machines with rotor faults, based on a synchronous reference frame and on Steinmetz's phasors. The developed relationships can be visualized through equivalent circuits, feedback loop block diagrams, or geometrical loci, allowing a deep understanding of the underlying physical phenomena, particularly as functions of inertia and of the machine parameters. The insight thus gained helps to enhance the quantification of fault severity with respect to the usual diagnostic technique based on the sum of the sidebands, clearly defining for the first time the field of validity of such technique. The analytical results are verified through simulations and experiments.

High-performance optimizations on tiled many-core embedded systems: a matrix multiplication case study

Technological advancements in the silicon industry, as predicted by Moore's law, have resulted in an increasing number of processor cores on a single chip, giving rise to multicore, and subsequently many-core architectures. This work focuses on identifying key architecture and software optimizations to attain high performance from tiled many-core architectures (TMAs)--an architectural innovation in the multicore technology. Although embedded systems design is traditionally power-centric, there has been a recent shift toward high-performance embedded computing due to the proliferation of compute-intensive embedded applications. The TMAs are suitable for these embedded applications due to low-power design features in many of these TMAs. We discuss the performance optimizations on a single tile (processor core) as well as parallel performance optimizations, such as application decomposition, cache locality, tile locality, memory balancing, and horizontal communication for TMAs. We elaborate compiler-based optimizations that are applicable to TMAs, such as function inlining, loop unrolling, and feedback-based optimizations. We present a case study with optimized dense matrix multiplication algorithms for Tilera's TILEPro64 to experimentally demonstrate the performance and performance per watt optimizations on TMAs. Our results quantify the effectiveness of algorithmic choices, cache blocking, compiler optimizations, and horizontal communication in attaining high performance and performance per watt on TMAs.

Improved loop tiling based on the removal of spurious false dependences

To preserve the validity of loop nest transformations and parallelization, data dependences need to be analyzed. Memory dependences come in two varieties: true dependences or false dependences. While true dependences must be satisfied in order to preserve the correct order of computations, false dependences are induced by the reuse of a single memory location to store multiple values. False dependences reduce the degrees of freedom for loop transformations. In particular, loop tiling is severely limited in the presence of these dependences. While array expansion removes all false dependences, the overhead on memory and the detrimental impact on register-level reuse can be catastrophic. We propose and evaluate a compilation technique to safely ignore a large number of false dependences in order to enable loop nest tiling in the polyhedral model. It is based on the precise characterization of interferences between live range intervals, and it does not incur any scalar or array expansion. Our algorithms have been implemented in the Pluto polyhedral compiler, and evaluated on the PolyBench suite.

HIGH PERFORMANCES LOCAL OSCILLATOR SIGNAL DRIVER FOR 60 GHZ I\Q SYSTEMS IN 65NM CMOS TECHNOLOGY

This paper shows the design of a reduced size system that drives local oscillator (LO) signal generated by a voltage controlled oscillator (VCO) in the transceiver system, which is based on I and Q architecture. The aim of this work is to obtain a small system capable to drive two difierential mixers and one phase locked loop block with high power e-ciency. The entire system drives two difierential outputs to their respective mixers with a minimum difierential LO power of i1dBm and a maximum of 0dBm between 56.5 and 60GHz. The system furnishes i7dBm to the PLL, allowing the control of the carrier. The output ports are matched at 50› and they achieve a re∞ection loss under 10dB in the whole band of interest. The power consumption of the entire system is 58mW. The size including RF and DC pads is 0:6 £ 0:7mm 2 .

Automatically enhancing locality for tree traversals with traversal splicing

Generally applicable techniques for improving temporal locality in irregular programs, which operate over pointer-based data structures such as trees and graphs, are scarce. Focusing on a subset of irregular programs, namely, tree traversal algorithms like Barnes-Hut and nearest neighbor, previous work has proposed point blocking, a technique analogous to loop tiling in regular programs, to improve locality. However point blocking is highly dependent on point sorting, a technique to reorder points so that consecutive points will have similar traversals. Performing this a priori sort requires an understanding of the semantics of the algorithm and hence highly application specific techniques. In this work, we propose traversal splicing, a new, general, automatic locality optimization for irregular tree traversal codes, that is less sensitive to point order, and hence can deliver substantially better performance, even in the absence of semantic information. For six benchmark algorithms, we show that traversal splicing can deliver single-thread speedups of up to 9.147 (geometric mean: 3.095) over baseline implementations, and up to 4.752 (geometric mean: 2.079) over point-blocked implementations. Further, we show that in many cases, automatically applying traversal splicing to a baseline implementation yields performance that is better than carefully hand-optimized implementations.

Optimizing matrix transposes using a POWER7 cache model and explicit prefetching

We consider the problem of efficiently computing matrix transposes on the POWER7 architecture. We develop a matrix transpose algorithm that uses cache blocking, cache prefetching and data alignment. We model the POWER7 data cache and memory concurrency and use the model to predict the memory throughput of the proposed matrix transpose algorithm. The performance of our matrix transpose algorithm is up to five times higher than that of the dgetmo routine of the Engineering and Scientific Subroutine Library and is 2.5 times higher than that of the code generated by compiler-inserted prefetching. Numerical experiments indicate a good agreement between the predicted and the measured memory throughput.