Cache-based Architecture Research Articles

Hardware designs for convolutional neural networks: Memoryful, memoryless and cached

This work presents three hardware architectures for convolutional neural networks with high degree of parallelism and component reuse implemented in a programmable device. The first design, which is termed memoryful architecture, uses as much memory as necessary to store the input data and intermediate results. The second design, which is termed memoryless architecture, defines and explores a specific input sequencing pattern to completely avoid the use of memory. The third design, which is termed cache memory-based architecture, is an intermediate solution, where the input sequence is further explored. In this case, a cache memory is used to store some intermediate results and, consequently, to improve processing performance. We compare the three designs in terms of power, area, and processing time. Allowing memory usage in the memoryful architecture increases the overall hardware cost, but reduces processing time. Preventing all memory usage in memoryless architecture increases operation parallelism, but compromises processing time. A trade-off between memory usage and processing performance is achieved in cache memory-based architecture. It provides a processing time 3× shorter than memoryful architecture, running at a clock frequency about 20% higher. When compared to the memoryless design, the cache-based architecture achieves about 13× less processing time even running at a clock frequency about 1.5% smaller. The improvement in clock frequency and processing performance comes at a cost in terms of hardware resources for the cached memory architecture. Its design, depending on the cache size, may require up to 25% more logic elements than the memoryful and memoryless architectures.

A microbenchmark characterization of the Emu chick

The Emu Chick is a prototype system designed around the concept of migratory memory-side processing. Rather than transferring large amounts of data across power-hungry, high-latency interconnects, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each memory read. The current prototype hardware uses FPGAs to implement cache-less “Gossamer” cores for computational work and rely on a typical stationary core (PowerPC) to run basic operating system functions and migrate threads between nodes. In this multi-node characterization of the Emu Chick, we extend an earlier single-node investigation [1] of the memory bandwidth characteristics of the system through benchmarks like STREAM, pointer chasing, and sparse matrix-vector multiplication. We compare the Emu Chick hardware to architectural simulation and an Intel Xeon-based platform. Our results demonstrate that for many basic operations the Emu Chick can use available memory bandwidth more efficiently than a more traditional, cache-based architecture although bandwidth usage suffers for computationally intensive workloads like SpMV. Moreover, the Emu Chick provides stable, predictable performance with up to 65% of the peak bandwidth utilization on a random-access pointer chasing benchmark with weak locality.

GeoCache

GML is a promising model for integrating geodata within data warehouses. The resulting databases are generally large and require spatial operators to be handled. Depending on the size of the target geographical data and the number and complexity of operators in a query, the processing time may quickly become prohibitive. To optimize spatial queries over GML encoded data, this chapter introduces a novel cache-based architecture. A new cache replacement policy is then proposed. It takes into account the containment properties of geographical data and predicates, and allows evicting the most irrelevant values from the cache. Experiences with the GeoCache prototype show the effectiveness of the proposed architecture with the associated replacement policy, compared to existing works.

Algorithm 841: BHESS: Gaussian reduction to a similar banded Hessenberg form

BHESS uses Gaussian similarity transformations to reduce a general real square matrix to similar upper Hessenberg form. Multipliers are bounded in root mean square by a user-supplied parameter. If the input matrix is not highly nonnormal and the user-supplied tolerance on multipliers is of a size greater than ten, the returned matrix usually has small upper bandwidth. In such a case, eigenvalues of the returned matrix can be determined by the bulge-chasing BR iteration or by Rayleigh quotient iteration. BHESS followed by BR iteration determines a complete spectrum in about one-fifth the time required for orthogonal reduction to Hessenberg form followed by QR iterations. The FORTRAN 77 code provided for BHESS runs efficiently on a cache-based architecture.

A simple and efficient parallel FFT algorithm using the BSP model

We present a new parallel radix-4 FFT algorithm based on the BSP model. Our parallel algorithm uses the group-cyclic distribution family, which makes it simple to understand and easy to implement. We show how to reduce the communication cost of the algorithm by a factor of 3, in the case that the input/output vector is in the cyclic distribution. We also show how to reduce computation time on computers with a cache-based architecture. We present performance results on a Cray T3E with up to 64 processors, obtaining reasonable efficiency levels for local problem sizes as small as 256 and very good efficiency levels for local sizes larger than 2048.

An innovative, high quality and search window independent motion estimation algorithm and architecture for MPEG-2 encoding

This paper describes an innovative, pipelined, cache-based architecture for a motion estimation coprocessor. The coprocessor is based on a predictive/recursive algorithm whose computational complexity is low and not dependent on the search window. The synergies between the architecture and algorithm's features allow a high quality, low-area, low-bandwidth, search window implementation for standard resolution (PAL/NTSC), low resolution (CIF/QCIF) or high resolution (ATSC) sequences.

Cashing in on Caching: An Architecture for Time-BoundedKnowledge-Based Problem Solving

Knowledge-based computing, in general, suffers from an inherent open-endedness that precludes its application in time-bounded domains where an answer must be computed within a stipulated time limit. We examine a two-way improvement of the shortcomings: a knowledge representation scheme that provides easy access to relevant knowledge and thereby reduces search time, and a reasoning scheme that is algorithmic in nature and thus makes computational requirements meaningfully estimable. In this work, we offer a cache-based architecture that is capable of both storing knowledge in different formats (e.g. rules, cases), and invoking an appropriate reasoning scheme to fit the available computing time. The cache helps in retrieving the most relevant pieces of knowledge (not only exact matches) required for solving a given problem. This cache relies on a reasoning tactic, knowledge interpolation, that can generate a solution from two near-matches in an algorithmic way, to generate time-bounded solutions. We illustrate the design of such a cache for solving resource allocation problems in the domain of shortwave radio transmission and evaluate its performance in observing imposed temporal bounds.

Improving applications performance

This paper presents a memory model and architecture for synchronization of threads or tasks when accessing regions of virtual memory. Access control is defined on a memory region through a view that defines the size of access units and also the protocol in terms of a Finite State Machine (FSM). The size of access units, although fixed within a view, can vary across views and is thus customizable to applications. Variable-sized access units are obtained without altering the underlying fixed sized paging implementation. By defining access control through FSM definitions, any protocol that is decomposable into a set of states and can be expressed using an FSM can be supported.A cache-based architecture of the Protection Control Unit (PCU), which decides whether a read/write memory access to an access unit of a region/view can proceed or leads to a fault, is presented. The PCU is not invoked on each read/write memory access, but only on data cache misses and write access faults. The cache-based architecture forms flexible hardware support for access control in that by loading the caches with definitions of different FSM, different protocols can be supported. Furthermore, by providing for hardware supported changes in state of access through state transitions, frequency of context switching is reduced.Trace-driven simulation is used to examine the delay in the memory hierarchy due to inclusion of the caches in the PCU unit, and to examine delay in the memory hierarchy for a conventional software implementation of the same access control protocol. A TPC-C benchmark application under different transaction loads was traced and the results show that it is the number of TLB accesses (approximately 15 times more as compared to PCU accesses) for the modeled application that incurs the dominant delay, as compared to delay in the PCU memory hierarchy.