Bytes Of Memory Research Articles

Post-cinematic memory ecology and the remediation of Chinese Red Cinema

The transition from mnemonic aura to memory bytes has mobilized technical experts, archivists, scholars, and cinephiles to preserve film copies, record eyewitness accounts, reconstruct viewing conditions, and recreate audience sensations. The ensuing network of agents, technologies, and discourses may be described as an intersection of new media and memory ecosystems. This post-celluloid, post-theatrical environment, which I call the post-cinematic memory ecology, engages new modes of production, storage, promotion, consumption, and recall. This essay highlights the main characteristics post-cinematic memory ecology and outlines the synergy between the emerging technologies, media industry models, patterns of viewer involvement, and practices of commemoration. The essay examines post-cinematic memory ecology through Film Legends ( Dianying chuanqi), a made-for-TV mega-series that first aired in China in 2004.

Design of Part Request Form Application and Data Migration

Abstract: The migration of the data form legacy systems to modern enterprise solutions is critical for optimizing business processes and enhancing performance. This paper focuses on comparison of the data migration techniques LSMW and S/4 HANA migration cockpit. The main objective is to optimize the business process through the creation of Part Request Form application in fiori launchpad and performing data migration using S/4 High performance analytic appliance(HANA) migration cock- pit. Traditional methods of data migration has several problems, including performance bottlenecks. Addressing this limitation is essential to ensure seamless data transfer and accurate system integration. This report explores these issues and presents a methodology to address them by using advanced capabilities of the S/4 HANA Migration Cockpit over the conventional Legacy system migration workbench(LSMW) tool. The primary objective of this work is to optimize business process using part request form application. The data comes from the application will be saved in the database table in the user system. That data is extracted into a file and send it to the IT firm where that data will be migrated to the HANA database. The tool used for the data migration is s/4 HANA migration cockpit. The software used for this project is SAP-ERP software. The Results from the simulation shows that migration cockpit process is 48% faster than LSMW technique. The part request form application uses 12 kilo bytes of memory which is very less and the processing time is 0.1 seconds which is very less. These results highlight advantages of using an application in data warehouse and the effectiveness of the S/4 HANA Migration Cockpit in optimizing business processes within warehouse environment.

Optimizing Software-Defined Networks with Fuzzy Logic-Based Enhancement of Openflow Protocol

Today, humans have a strong need to control their devices from a distance so that they can control the world more than before and explore it for various purposes such as how the universe came into being, discovering the way of creation, observing the events in Global situation and so on. Communication with remote devices can be possible in various ways. SDN networks provide a possibility to exchange information between heterogeneous nodes. Considering that in SDN networks, the nodes are very expensive and these nodes themselves are performing many tasks and various vital tasks; Therefore, the cost of each byte of memory occupied on these nodes is very expensive and must be managed in such a way that they have the highest efficiency. Therefore, to solve this problem, it is very necessary and costly to carry out large projects. In the proposed method of this research, by improving the OpenFlow protocol in software-based networks, it is tried to avoid the cooperation of nodes in the directional distribution (not dissemination) of a small data, from the accumulation of extra information in the nodes' memories. Finally, after the simulation, it was observed that the improvement rate of the proposed method has improved by 0.38%, 0.05%, and 0.04%, respectively, compared to RD, FLCFP, and LEACH2013 methods. The improvement rate of the proposed method compared to RD, FLCFP, and LEACH2013 methods was 0.65%, 0.059%, and 0.331%, respectively.

Integrated Sensor Electronic Front-Ends with Self-X Capabilities

The ongoing vivid advance in integration technologies is giving leverage both to computing systems as well as to sensors and sensor systems. Both conventional computing systems as well as innovative computing systems, e.g., following bio-inspiration from nervous systems or neural networks, require efficient interfacing to an increasing diversity of sensors under the constraints of metrology. The realization of sufficiently accurate, robust, and flexible analog front-ends (AFE) is decisive for the overall application system and quality and requires substantial design expertise both for cells in System-on-Chip (SoC) or chips in System-in-Package (SiP) realizations. Adding robustness and flexibility to sensory systems, e.g., for Industry 4.0., by self-X or self-* features, e.g., self-monitoring, -trimming, or -healing (AFEX) approaches the capabilities met in living beings and is pursued in our research. This paper summarizes on two chips, denoted as Universal-Sensor-Interface-with-self-X-properties (USIX) based on amplitude representation and reports on recently identified challenges and corresponding advanced solutions, e.g., on circuit assessment as well as observer robustness for classic amplitude-based AFE, and transition activities to spike domain representation spiking-analog-front-ends with self-X properties (SAFEX) based on adaptive spiking electronics as the next evolutionary step in AFE development. Key cells for AFEX and SAFEX have been designed in XFAB xh035 CMOS technology and have been subject to extrinsic optimization and/or adaptation. The submitted chip features 62,921 transistors, a total area of 10.89 mm2 (74% analog, 26% digital), and 66 bytes of the configuration memory. The prepared demonstrator will allow intrinsic optimization and/or adaptation for the developed technology agnostic concepts and chip instances. In future work, confirmed cells will be moved to complete versatile and robust AFEs, which can serve both for conventional as well as innovative computing systems, e.g., spiking neurocomputers, as well as to leading-edge technologies to serve in SOCs.

Improved Single-Key Attacks on 2-GOST

GOST, known as GOST-28147-89, was standardized as the Russian encryption standard in 1989. It is a lightweight-friendly cipher and suitable for the resource-constrained environments. However, due to the simplicity of GOST’s key schedule, it encountered reflection attack and fixed point attack. In order to resist such attacks, the designers of GOST proposed a modification of GOST, namely, 2-GOST. This new version changes the order of subkeys in the key schedule and uses concrete S-boxes in round function. But regarding single-key attacks on full-round 2-GOST, Ashur et al. proposed a reflection attack with data of 2 32 on a weak-key class of size 2 224 , as well as the fixed point attack and impossible reflection attack with data of 2 64 for all possible keys. Note that the attacks applicable for all possible keys need the entire plaintext space. In other words, these are codebook attacks. In this paper, we propose single-key attacks on 2-GOST with only about 2 32 data instead of codebook. Firstly, we apply 2-dimensional meet-in-the-middle attack combined with splice-cut technique on full-round 2-GOST. This attack is applicable for all possible keys, and its data complexity reduces from previous 2 64 to 2 32 . Besides that, we apply splice-cut meet-in-the-middle attack on 31-round 2-GOST with only data of 2 32 . In this attack, we only need 8 bytes of memory, which is negligible.

Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic

Novel high-speed memory optimized distributed arithmetic (DA)-based architecture is developed and modeled for 3D discrete wavelet transform (DWT). The memory requirement for the proposed architecture is designed to [Formula: see text] pixel dynamic memory space and [Formula: see text] ROM. The proposed 3D-DWT architecture implements 9/7 Daubechies wavelet filters, synthesizes 7127 bytes of memory for temporary storage and uses 758 adders, 36 multiplexers of 16:1 and 36 up counter to realize the 3D-DWT hardware. The 3D-DWT engine is implemented and tested in a Xilinx FPGA Vertex5 XC5VLX155T with high area and power efficiency. The maximum delay in the timing path is 2.676[Formula: see text]ns and the 3D-DWT works at maximum frequency of 381[Formula: see text]MHz clock.

Calculating the divided differences of the exponential function by addition and removal of inputs

We introduce a method for calculating the divided differences of the exponential function by means of addition and removal of items from the input list to the function. Our technique exploits a new identity related to divided differences recently derived by Zivcovich (2019). We show that upon adding an item to or removing an item from the input list of an already evaluated exponential, the re-evaluation of the divided differences can be done with only O(sn) floating point operations and O(sn) bytes of memory, where [z0,…,zn] are the inputs and s∝maxi,j|zi−zj|. We demonstrate our algorithm’s ability to deal with input lists that are orders-of-magnitude longer than the maximal capacities of the current state-of-the-art. We discuss in detail one practical application of our method: the efficient calculation of weights in the off-diagonal series expansion quantum Monte Carlo algorithm.

Video Classification for Video Service Providers : A Survey

One of the very interesting data modalities is video. From a dimensionality and size perspective, videos are one of the most interesting and intuitive data types which enable fast and easy object recognition and learning. Video classification is an important task for archiving digital contents for various video service providers. Video uploading platforms such as YouTube are collecting enormous datasets, empowering Deep Learning research. Videos being an important source to recognize any activity by the humans, video classification becomes an important and critical job for video service providers. The survey paper studies various deep learning, transfer learning and hybrid model approaches. Video data normally occurs as continuous, analog signals In order for a computer to process this video data, the analog signals must be converted to a non-continuous, digital format. In a digital format, the video data can be stored as a series of bits on a hard disk or in computer memory. A video sequence is displayed as a series of frames. Each frame is a snapshot of a moment in time of the motion-video data, and is very similar to a still image. When the frames are played back in sequence on a display device, a rendering of the original video data is created. In real-time video the playback rate is 30 frames per second. This is the minimum rate necessary for the human eye to successfully blend each video frame together into a continuous, smoothly moving image. A single frame of video data can be quite large in size. A video frame with a resolution of 512 x 482 will contain 246,784 pixels. If each pixel contains 24 bits of color information, the frame will require 740,352 bytes of memory or disk space to store. Assuming there are 30 frames per second for real-time video, a 10-second video sequence would be more than 222 megabytes in size! It is clear there can be no computer video without at least one efficient method of video data compression.

IOT Based Omni Directional Robot Control by Using ARM-Series

On this research, controlling the omni directional mobile robot is divided by two controls, high level control which covers positioning and path tracking, also the low-level control which covers omnidirectional kinematic, speed control, heading lock and communication. This also covers thread management, priority fixation and stack memory fixation. Program is divided into several main threads, i.e., IMU, speed controller, communication and motion thread (kinematic). Stack memory configuration for the above threads can be allotted as IMU thread with 1024 bytes of stack memory, speed control with 512 bytes, motion management with 512 bytes, communication with 128 bytes. IMU execution time lapses for 5.6uS, speed control elapses for 19.7uS, whereas motion elapses for 11uS and communication elapses for 1.2mS. Robot’s low-level control which includes robot movement kinematic (e.g., heading lock, speed control etc) is required to support the predefined system and enhance the robot sensor’s response in navigation.

Dual-PISA: An index for aggregation operations on time series data

Aggregation operations play an essential role in time series database management. As the number of data increases, it is difficult for current solutions, such as summary table and MapReduce-based methods to respond to such queries with low latency. Other approaches, such as segment tree-based methods, have a poor insertion performance when the data size exceeds the available memory. This paper proposes a Persistent Index for Segmented Aggregations (PISA), which has fast insertion performance and low latency for aggregation queries. PISA uses a forest to overcome the performance disadvantage of insertion in traditional segment trees. By defining two kinds of tags, namely code number and serial number, we propose an algorithm to accelerate queries by avoiding unnecessary reading data on disk. Additionally, we extend it to Dual-PISA to tolerate a range of unordered data, which is very important in the real world. Dual-PISA is stored on disk and is hugely memory-efficient — only takes a few hundred bytes of memory for billions of data points. Dual-PISA can be easily implemented on both traditional databases and NoSQL systems. It handles aggregation queries within milliseconds on a commodity server, for a time range that contains tens of billions of data points.

High-performance architecture for flow-table lookup in SDN on FPGA

We propose range-based ternary search tree (RTST), a tree-based approach for flow-table lookup in SDN. RTST builds upon flow-tables in SDN switches to provide a fast lookup among flows. We present a parallel multi-pipeline architecture for implementing RTST that benefits from high throughput and low latency. The proposed RTST and architecture achieve a memory efficiency of 1 byte of memory for each byte of flow. We also present a set of techniques to support dynamic updates. Experimental results reveal that RTST can be used to improve the performance of flow-lookup. It achieves a throughput of 670 million packets per second (MPPS), for a 1K 15-tuple flow-table, on a state-of-the-art FPGA (Virtex 6 XC6VLX760).

GRASP2018—A Fortran 95 version of the General Relativistic Atomic Structure Package

The present Grasp2018 is an updated Fortran 95 version of the recommended block versions of programs from Grasp2K Version 1_1 for large-scale calculations Jönsson et al. (2013). MPI programs are included so that all major tasks can be executed using parallel computers. Tools have been added that simplify the generation of configuration state function expansions for the multireference single- and double computational model. Names of programs have been changed to accurately reflect the task performed by the code. Modifications to the relativistic self-consistent field program have been made that, in some instances, greatly reduce the number of iterations needed for determining the requested eigenvalues and the memory required. Changes have been made to the relativistic configuration interaction program to substantially cut down on the time for constructing the Hamiltonian matrix for configuration state function expansions based on large orbital sets. In the case of a finite nucleus the grid points have been changed so that the first non-zero point is Z-dependent as for the point nucleus. A number of tools have been developed to generate LaTeX tables of eigenvalue composition, energies, transition data and lifetimes. Tools for plotting and analyzing computed properties along an iso-electronic sequence have also been added. A number of minor errors have been corrected. A detailed manual is included that describes different aspects of the package as well as the steps needed in order to produce reliable results. Program summaryProgram Title:Grasp2018Program Files doi:http://dx.doi.org/10.17632/x574wpp2vg.1Licensing provisions: MIT licenseProgramming language: Fortran 95.Nature of problem: Prediction of atomic properties – atomic energy levels, isotope shifts, oscillator strengths, radiative decay rates, hyperfine structure parameters, specific mass shift parameters, Zeeman effects – using a multiconfiguration Dirac–Hartree–Fock approach.Solution method: The computational method is the same as in the previous Grasp2K [1,2] version except that only the latest recommended versions of certain routines are included.Restrictions: All calculations are for bound state solutions. Instead of relying on packing algorithms for specifying arguments of arrays of integrals, orbitals are designated by a “short integer” requiring one byte of memory for a maximum of 127 orbitals. The tables of reduced coefficients of fractional parentage used in this version are limited to sub-shells with j≤9∕2 [3]; occupied sub-shells with j>9∕2 are, therefore, restricted to a maximum of two electrons. Some other parameters, such as the maximum number of orbitals are determined in a parameter_def_M.f90 file that can be modified prior to compile time.Unusual features: Parallel versions are available for several applications.References•[[1]] P. Jönsson, X. He, C. Froese Fischer, and I. P. Grant, Comput. Phys. Commun. 176, 597 (2007).•[[2]] P. Jönsson, G. Gaigalas, J. Bieroń, C. Froese Fischer, and I. P. Grant, Comput. Phys. Commun. 184, 2197 (2013).•[[3]] G. Gaigalas, S. Fritzsche, Z. Rudzikas, Atomic Data and Nuclear Data Tables 76, 235 (2000).

Effective algorithm for routing integral structures with twolayer switching

The paper presents an algorithm for routing switching objects such as large-scale integrated circuits (LSICs) with two layers of metallization, embossed printed circuit boards, microboards with pairs of wiring layers on each side, and other similar constructs. The algorithm allows eliminating the effect of mutual blocking of routes in the classical wave algorithm by implementing a special circuit of digital wave motion in two layers of metallization, allowing direct intersections of all circuit conductors in a combined layer. However, information about the belonging of the topology elements to the circuits is sufficient for layering and minimizing the number of contact holes. In addition, the paper presents a specific example which shows that, in contrast to the known routing algorithms using a wave model, just one byte of memory per discrete of the work field is sufficient to implement the proposed algorithm.

Privacy-preserving Image Processing with Binocular Thermal Cameras

Today, cameras and digital image processing are transforming industries and the human environment with rich, informative sensing. However, image processing is not utilized nearly as much in homes where concerns about image privacy dominate. In a preliminary study with 200 participants, we found 21% would reject a camera based system even if the system was designed to not report images as they could still be collected if the camera system was hacked. In this paper, we demonstrate a hardware-based approach for privacy-preserving image processing: the ability to automatically extract information from imaging sensors without the risk of compromising image privacy, even if the system is hacked. The basic idea is to limit both the memory available on board the camera and the data rate of camera communication to prevent a full image from ever being extracted. As a proof of concept, we prototype a system, called Lethe, that tracks and identifies individuals by height with a thermal camera as they move from room to room. Our results show that Lethe can detect the presence of individuals with 96.9% accuracy and determine their direction of travel with 99.7% accuracy. Additionally, Lethe can identify individuals 96.0% of the time with a 5cm (~2in) or greater difference in walking height and 92.9% with a 2.5cm (~1in) or greater difference. Finally, Lethe performs this processing with only 33 bytes of memory (or 0.69% of the full thermal image).

Design and implementation of a digital thermometer with clock

In this paper, the design of a digital thermometer with clock is presented. The design was achieved using ATMEGA 328P PU Microcontroller Unit, MLX90614 Infrared Sensor for achieving contactless measurement (wireless) and the DS1307 Real Time Clock (RTC) for accurate time keeping during the measurement of this parameter.The MLX90614 is factory calibrated in wide temperature ranges from - 40 oC to 125oC for the ambient temperature and -70 oC to 382.19oC for object temperature, while the DS1307 is a low-power clock/calendar with 56 bytes of battery-backed serial random access memory (SRAM). Power is supplied using a regulated 9 V DC battery. The microcontrollers and RTC chip are powered by 5 V DC. The temperature sensor and liquid crystal display (LCD) require 3.3 V DC for operation and are supplied by passing the 5 V DC through a variable resistor. The sensors output values are both fed into the microcontroller. While monitoring temperature and telling time, the microcontroller sends the measurements in form of digital signal to the LCDs for display.This design was compared with a standard infrared thermometer by taking the body temperature measurements of two individuals at different times of the day. It was observed from the results that the difference between the temperature readings of the two thermometers ranges from 0 to 1 °C Keywords: Infrared sensor, digital thermometer, microcontroller, real time clock, temperature

Caching Online Video

Online video presents new challenges to traditional caching with over a thousand-fold increase in number of assets, rapidly changing popularity of assets and much higher throughput requirements. We propose a new hierarchical filtering algorithm for caching online video HiFi. Our algorithm is designed to optimize hit rate, replacement rate and cache throughput. It has an associated implementation complexity comparable to that of LRU. Our results show that, under typical operator conditions, HiFi can increase edge cache byte hit rate by 5%--24% over an LRU policy, but more importantly can increase the RAM or memory byte hit rate by 80% to 200% and reduce the replacement rate by more than 100 times! These two factors combined can dramatically increase throughput for most caches. If SSDs are used for storage, the much lower replacement rate may also allow substitution of lower-cost MLC-based SSDs instead of SLC-based SSDs. We extend previous multi-tier analytical models for LRU caches to caches with filtering. We analytically show how HiFi can approach the performance of an optimal caching policy and how to tune HiFi to reach as close to optimal performance as the traffic conditions allow. We develop a realistic simulation environment for online video using statistics from operator traces. We show that HiFi performs within a few percentage points from the optimal solution which was simulated by Belady's MIN algorithm under typical operator conditions

Statistical integral attack on CAST-256 and IDEA

Integral attack, as a powerful technique in the cryptanalysis field, has been widely utilized to evaluate the security of block ciphers. Integral distinguisher is based on balanced property on output with probability one. To obtain a distinguisher covering more rounds, an attacker will usually increase the data complexity by iterating through all values of more bits of plaintexts under the firm limitation that the data complexity should be less than the whole plaintext space. In order to release the limitation and reduce the data complexity, Wang et al. proposed a statistical integral distinguisher at FSE’16. In this paper, we exploit the statistical integral distinguisher to attack the IDEA and CAST-256 block ciphers. As a result, we manage to mount a key recovery attack on 29-round CAST-256 with 296.8 chosen plaintexts, 2219.4 encryptions and 273 bytes of memory. By making a trade-off between the time complexity and data complexity, the attack can be achieved by 283.9 chosen plaintexts, 2244.4 encryptions and 266 bytes of memory. As far as we know, these are the best attacks on CAST-256 in the single-key model without weak-key assumption so far. What’s more, we find an integral distinguisher of IDEA block cipher, which is the longest integral distinguisher known to now. By taking advantage of this distinguisher, we achieve a key recovery attack on 4.5-round IDEA with 258.5 known plaintexts, 2120.9 encryptions and 246.6 bytes of memory respectively. It is the best integral attack with respect to the number of rounds.

Design and Validation of a Breathing Detection System for Scuba Divers.

Drowning is the major cause of death in self-contained underwater breathing apparatus (SCUBA) diving. This study proposes an embedded system with a live and light-weight algorithm which detects the breathing of divers through the analysis of the intermediate pressure (IP) signal of the SCUBA regulator. A system composed mainly of two pressure sensors and a low-power microcontroller was designed and programmed to record the pressure sensors signals and provide alarms in absence of breathing. An algorithm was developed to analyze the signals and identify inhalation events of the diver. A waterproof case was built to accommodate the system and was tested up to a depth of 25 m in a pressure chamber. To validate the system in the real environment, a series of dives with two different types of workload requiring different ranges of breathing frequencies were planned. Eight professional SCUBA divers volunteered to dive with the system to collect their IP data in order to participate to validation trials. The subjects underwent two dives, each of 52 min on average and a maximum depth of 7 m. The algorithm was optimized for the collected dataset and proved a sensitivity of inhalation detection of 97.5% and a total number of 275 false positives (FP) over a total recording time of 13.9 h. The detection algorithm presents a maximum delay of 5.2 s and requires only 800 bytes of random-access memory (RAM). The results were compared against the analysis of video records of the dives by two blinded observers and proved a sensitivity of 97.6% on the data set. The design includes a buzzer to provide audible alarms to accompanying dive buddies which will be triggered in case of degraded health conditions such as near drowning (absence of breathing), hyperventilation (breathing frequency too high) and skip-breathing (breathing frequency too low) measured by the improper breathing frequency. The system also measures the IP at rest before the dive and indicates with flashing light-emitting diodes and audible alarm the regulator malfunctions due to high or low IP that may cause fatal accidents during the dive by preventing natural breathing. It is also planned to relay the alarm signal to underwater and surface rescue authorities by means of acoustic communication.

Hierarchical Parallel Evaluation of a Hamming Code

The Hamming code is a well-known error correction code and can correct a single error in an input vector of size n bits by adding logn parity checks. A new parallel implementation of the code is presented, using a hierarchical structure of n processors in logn layers. All the processors perform similar simple tasks, and need only a few bytes of internal memory.

Robotized semiautomatic motorcycle transmission development. Electronic and software design

In this paper, we propose an electrical design (implemented on a PCB board) and an accompanying software design for controlling the automatic gear change. The designs complement the mechanical solutions developed in Part 1. The paper also analyses the issues encountered during the intermediate steps of the development of the electronic module, which is expected to be small and adaptable enough to be installed on a motorcycle without changing its ergonomics. The control software runs on the Arduino Nano board and is built as a state machine with one idle state, five active states that cover different stages of the gear change and one error state for preventing malfunctions in case of an unexpected event. The sketch uses 5,760 bytes (or 18%) of program storage space and 706 bytes (or 34%) of the dynamic memory.