Butterfly Fat Tree Research Articles

Mesh of Trees FPGA Architecture: Exploration and Optimization

The design of large devices suggests fundamental and efficient innovation in the field programmable gate array (FPGA) interconnect structure to improve power consumption, density, and performance. Mesh-based FPGA architectures are generally designed to maximize logic utilization and to ensure layout scalability whereas tree-based FPGA architectures are designed to increase interconnect utilization. In this article, we propose a new mesh of trees (MoTs) FPGA architecture where we try to benefit from mesh of clusters (MoCs) FPGA layout scalability and tree-based FPGA efficient intracluster interconnect utilization, thanks to the butterfly fat-tree (BFT) topology. In order to attain the efficient use of the proposed routing interconnect resources, we develop computer-aided design (CAD) tools that respond to the target MoTs FPGA features. In addition, we define the power, area, and delay metric models according to the proposed architecture criteria. The experimentation results show that MoTs architecture with a cluster arity 32 offers the best tradeoff between power, area, and delay. Furthermore, we conduct a comparison between MoTs and MoCs FPGAs in general and the best MoTs and MoCs solutions, which ensure the best tradeoff between power, area, and delay in particular. The results show that the best MoTs architecture reduces power, area, delay, and energy by an average of 29%, 6%, 40%, and 47%, respectively, in comparison with the best MoCs architecture.

Power and performance analysis of 3D network-on-chip architectures

Emerging 3D integrated circuits(ICs) employ 3D network-on-chip(NoC) to improve power, performance, and scalability. The NoC Simulator uses the microarchitecture parameters to estimate the power and performance of the NoC. We explore the design space for 3D Mesh and Butterfly Fat Tree(BFT) NoC architecture using floorplan drive wire length and link delay estimation. The delay and power models are extended using Through Silicon Via (TSV) power and delay models. Serialization is employed to reduce the TSV area cost. Buffer space is equalised for a fair comparison between topologies. The Performance, Flits per Joules(FpJ) and Energy Delay Product(EDP) of six 2D and 3D variants of Mesh and BFT topologies (two and four layers) are analyzed by injecting synthetic traffic patterns. The 3D-4L Mesh exhibit better performance, energy efficiency (up to 4.5 × ), and EDP (up to 98 %) compared to other variants. This is because the overall length of the horizontal link is short and the number of TSVs is large (3 × ).

A low latency and low power indirect topology for on-chip communication.

This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by up-to33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.

Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures

With the increase in number and complexity of cores and components in Chip-Multiprocessors (CMP) and Systems-on-Chip (SoCs), a highly structured and efficient on-chip communication network is required to achieve high-performance and scalability. Network-on-Chip (NoC) has emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. Cycle accurate simulators model the functionality and behaviour of NoCs by considering micro-architectural parameters of the underlying components to estimate performance, power and energy characteristics. Employing NoCs in three-dimensional integrated circuits (3D-ICs) can further improve performance, energy efficiency, and scalability characteristics of 3D SoCs and CMPs. Minimal error estimation of energy and performance of NoC components is crucial in architecture trade-off studies. Accurate modeling of re:Horizontal and vertical links by considering micro-architectural and physical characteristics reduces the error in power and performance estimation of 3D NoCs. Additionally, mapping the temperature distribution in a 3D NoC reduces estimation error.This paper presents the 3D NoC modelling capabilities extended in two existing state-of-the-art simulators, viz., the 2D NoC Simulator - BookSim2.0 and the thermal behaviour simulator - HotSpot6.0. With the extended 3D NoC modules, the simulators can be used for power, performance and thermal measurements through micro-architectural and physical parameters. The major extensions incorporated in BookSim2.0 are: Through Silicon Via power and performance models, 3D topology construction modules, 3D Mesh topology construction using variable X, Y, Z radix, tailored routing modules for 3D NoCs. The major extensions incorporated in HotSpot6.0 are: parameterized 2D router floorplan, 3D router floorplan including Through Silicon Vias (TSVs), power and thermal distribution models of 2D and 3D routers.Using the extended 3D modules, performance (average network latency), and energy efficiency metrics (Energy-Delay Product) of variants of 3D Mesh and 3D Butterfly Fat Tree topologies have been evaluated using synthetic traffic patterns. Results show that the 4-layer 3D Mesh is 2.2 × better than 2-layer 3D Mesh and 4.5 × better than 3D BFT variants in terms of network latency. 3D Mesh variants have the lowest Energy Delay Product (EDP) compared to 3D BFT variants as there is an 80% reduction in link lengths and up to 3 × more TSVs. Another observation is that the EDP of the 4-layer 3D BFT (with transpose traffic) is 1.5 × the EDP of the 4-layer 3D Mesh (with transpose traffic). Further optimizations towards a tailored 3D BFT for transpose traffic could reduce this EDP gap with the 4-layer 3D Mesh. From the 3D NoC heat maps, it was found that the edge routers in the floorplan of the tested 3D Mesh and 3D BFT topologies have the least ambient temperature.

Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimisation

ABSTRACTAs the technology is scaling down more number of processing elements are integrated on to a single chip, namely system-on-chips (SoCs). Using traditional bus architecture in SoCs, communication among different processing elements is difficult. Hence, to overcome it, a new on-chip interconnection paradigm known as network-on-chip (NoC) has been proposed. The communication among different processing elements in NoCs is achieved using packet switching technique. In nano-scale era, NoCs are prone to vulnerable faults and designing an NoC to meet current application requirements is highly challenging. Hence, there is a need to develop reliable and efficient Fault-tolerant NoC designs. This paper presents a novel Fault-Tolerant NoC design for butterfly-fat-tree (BFT) topology with flexible spare core placement by taking different benchmark applications into consideration. The major challenge in fault-tolerant NoC is placement of spare core in the event of core failure in BFT network. Therefore, we have proposed an integer linear programming (ILP)-based exact method and particle swarm optimisation (PSO)-based meta-heuristic technique to place the spare core in a BFT network. Our major contribution is to place the spare core in BFT network such that system performance is improved in terms of communication cost, network latency, and router power consumption. Experimentations have been performed on several application benchmarks reported in the literature, (i) by varying the network size with fixed fault-percentage in the network, (ii) by varying the percentage of faults while fixing the network size and (iii) by taking multiple failed cores as a user input. We have compared overall communication cost obtained using our approaches with native fault-free approach. We have also compared overall communication cost and CPU runtime between ILP and PSO. The results show improvement in terms of overall communication cost, average network latency and network power consumption using our approaches compared to fault-free approach in BFT networks.

Performance centric design of subnetwork-based diagonal mesh NoC

ABSTRACTPerformance of NoC relies heavily on underlying interconnect network and related message forwarding technique. Here, Mesh is an obvious network choice by the designer due to its regular grid-based structure, making it easy to implement in chip surface. However, mesh suffers from degrading network performance issue in large-scale dimension due to the increasing hop count that leads to both congestion and link contention at the same time. Conventional topologies like Folded Torus, Butterfly-fat-tree (BFT) and recently proposed topologies like Flattened BFT, Sc-mesh and SD2D mesh topologies are mostly relying on express bypass links to mitigate this limitation in large-scale dimension. Proposed work presents a low latency oriented diagonally linked network that combines both 2 × 2 and a 1 × 1 diagonal links over the generic mesh connection to shorten the network diameter rendering chip designers more flexibility in regulating important performances centric design trade-offs such as packet delay, throughput and network energy while employing a low area overhead (~7%). Experimental results over 8 × 8 and 12 × 12 sized network show 8–11%, 18–66% and 60–66% lower packet delay while gain in throughput raises to 15–17%, 29–64% and 46–58% compared to 2-hop Dia-mesh (2x2 diagonal), Sc-mesh (1x1 diagonal) and conventional mesh topologies, respectively, under uniformly distributed traffic.

A high-level exploration tool for three-dimensional network-on-chip

The convergence of 3D technology and NoC, the so-called 3D NoC, that freedom of interconnects in the vertical dimension can create new architectures, and has already proved higher performance than traditional 2D NoCs. In this paper, we explore the architectural design of 3D NoC and introduce a compositive model of fabrication cost, network throughput and power consumption, supporting six 3D NoC architectures, 3D mesh, hyper octagon, ciliated mesh, separate mesh, generic fat tree (SPIN) and butterfly fat tree (BFT), to explore different 3D design options of 3D NoCs. The model allows partition of IPs across different dies in 3D stack. Based on the model an estimation tool, 3D-partition, is created and validated by comparing its results with those obtained from NIRGAM. Effects of various 3D NoC architectures under different 3D IC partition strategies on cost, throughput and power consumption are explored to demonstrate the utility of the tool. It provides economic and performance reference to designing 3D ICs for volume production in the future.

A high-level exploration tool for three-dimensional network-on-chip

The convergence of 3D technology and NoC, the so-called 3D NoC, that freedom of interconnects in the vertical dimension can create new architectures, and has already proved higher performance than traditional 2D NoCs. In this paper, we explore the architectural design of 3D NoC and introduce a compositive model of fabrication cost, network throughput and power consumption, supporting six 3D NoC architectures, 3D mesh, hyper octagon, ciliated mesh, separate mesh, generic fat tree (SPIN) and butterfly fat tree (BFT), to explore different 3D design options of 3D NoCs. The model allows partition of IPs across different dies in 3D stack. Based on the model an estimation tool, 3D-partition, is created and validated by comparing its results with those obtained from NIRGAM. Effects of various 3D NoC architectures under different 3D IC partition strategies on cost, throughput and power consumption are explored to demonstrate the utility of the tool. It provides economic and performance reference to designing 3D ICs for volume production in the future.

Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires

This paper presents an improved interconnect network for Mesh of Clusters (MoC) Field-Programmable Gate Array (FPGA) architecture. Proposed architecture has a depopulated intra-cluster interconnect with flexible Rent's parameter. It presents new multi-levels Switch Box (SB) interconnect which unifies a downward and an upward unidirectional networks based on the Butterfly-Fat-Tree (BFT) topology. To improve the routability of proposed MoC-based FPGA, long routing segments are introduced as a function of channel width with adjustable span. Compared to basic Versatile Place and Route (VPR) Mesh architecture, a saving of 32% of area and 30% of power was achieved with proposed MoC-based architecture. Based on analytical and experimental methods, we identified and explored architecture parameters that control the interconnect flexibility of the proposed MoC-based FPGA such as Rent's parameter, cluster size, Look-Up-Table (LUT) size, long wires span and percentage. Experimental results show that architecture with LUT size 4 and Cluster arity 8 is the best trade-off between power consumption and density. It can also be noted that in general long wires span equal to 4 and percentage between 20% and 30% produce most efficient results in terms of density and power.

Application Mapping onto Butterfly-Fat-Tree based Network-on-Chip using Discrete Particle Swarm Optimization

paper addresses the problem of application mapping onto Butterfly-Fat-Tree (BFT) based Network-on-Chip design. It proposes a new mapping technique based on discrete Particle Swarm Optimization (PSO) to map the cores of the core graph to the routers. The basic PSO has been augmented by running multiple PSO and deterministically generating a part of the initial population for PSO. The mapping results have been compared with well-known techniques reported in the literature for a number of benchmark applications. The reported strategy produces results superior to those obtained via existing approaches within a reasonable CPU time. Keywordsmapping, Network-on-Chip, System-on-Chip, Butterfly-Fat-Tree, Discrete Particle Swarm Optimization

A Systematic Design Methodology for Low-Power NoCs

Network-on-chip (NoC) communication architectures are emerging as the most scalable and efficient solution to handle on-chip communication challenges in the multicore era. In NoCs, power estimations in the early stages of the design help the designers to optimize the design for energy consumption and efficiently map applications to achieve low-power solutions. However, in 90-nm designs or below, the impact of parasitics not only influence timing closure, but also leads to variability in power and area budgets among different NoC architectures. There is a growing need for advanced design methodologies to overcome these issues in NoC designs. This paper presents a system-level design methodology based on layout and power models to achieve low-power and high-performance NoC designs. The impact of global interconnects with and without repeater insertion on the bandwidth and power is considered. Width and spacing of global interconnects and its effect on performance and power dissipation are analyzed. For architectural-level power analysis, different router designs for Chip-Level Integration of Communicating Heterogeneous Elements (CLICHE), Butterfly Fat Tree (BFT), Scalable, Programmable, Integrated Network (SPIN), and Octagon NoC architectures are implemented using ARMs 65-nm standard cell library in 65-nm Taiwan Semiconductor Manufacturing Corporation (TSMC) process. The router designs are synthesized in RVT process using a ${V}_{\rm dd}$ of 1.0 V and a temperature of 25$^{\circ}{\rm C}$ . Synopsys Prime Time-PX design tool is used for calculating average power dissipation of the router designs.

Extending Kernighan–Lin partitioning heuristic for application mapping onto Network-on-Chip

Abstract This paper extends the basic Kernighan–Lin graph bi-partitioning algorithm for partitioning core graphs of applications to be designed using Network-on-Chip (NoC) concept. Mapping techniques have been developed for three different types of NoC topologies – Mesh, Mesh-of-Tree (MoT), and Butterfly-Fat-Tree (BFT). Suitable post-processing schemes have been developed to improve upon the basic solution produced by the partitioning algorithm. Significant improvement in both static and dynamic performances could be observed, compared to many existing approaches reported in the literature.

An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture

This paper presents an Enhanced Clustered Mesh (EnMesh) topology for a Network-on-Chip architecture in order to reduce the communication delay between remote regions by considering the physical positions of remote nodes. EnMesh topology includes short paths between diagonal regions to ensure fast communication among remote nodes. The performance and silicon area overhead of EnMesh are analyzed and compared to those of state-of-the-art topologies such as Mesh, Torus, and Butterfly-Fat-Tree (BFT). Experimental results demonstrate that EnMesh outperforms other existing regular topologies in terms of throughput, latency, packet loss rate, and silicon area overhead.

Power analysis for asynchronous network‐on‐chip

AbstractAn asynchronous architecture is proposed to achieve a low‐power network‐on‐chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

Network-on-Chip (NoC) has emerged as a new paradigm to integrate large number of cores on a single silicon die. This paper presents a detailed study of Mesh-of-Tree (MoT) topology and explores its promise in communication infrastructure design for 2-D NoC. The performance and cost of MoT based NoC have been evaluated and compared with butterfly fat-tree (BFT) and two variants of mesh network for equal number of cores under same bisection width constraint. Simulation results under self-similar traffic show that MoT enjoys the advantage of having better performance than other topologies, whereas, it consumes lesser average packet energy than the mesh network that connects single core to each router. In the area front, MoT occupies almost similar area like mesh network connects single core to each router. The MoT network has also been evaluated under a set of real benchmark applications and compared with the above mentioned topologies. Simulation results under application specific traffic also show the competitive potential of MoT topology in NoC design. Moreover, due to lesser connectivity of the routers, synthesis result shows that MoT network can be operated at higher frequency than others. Taking all these facts into consideration, this paper establishes that like mesh and BFT, MoT can also be applied in designing NoC based systems. This paper also focuses on the limitations of MoT and other tree based topologies in NoC design in current technology and enumerates probable solutions to make them more acceptable.

Asynchronous switching for low-power networks-on-chip

Asynchronous switching is proposed to achieve low power Network on Chip. Asynchronous switching reduces the power dissipation of the network if the activity factor of the data transfer between two ports αdata is less than Aαc+Bαclk. Closed form expressions for power dissipation of different network topologies are provided for both synchronous and asynchronous switching. The expressions are technology independent and are used for power estimation. Asynchronous switching is compared with synchronous switching for different network densities N/LcXLc. The area of the asynchronous switch is 50% greater than the area of the synchronous switch. However, the power dissipation of asynchronous switching decreased by up to 70.8% as compared to the power dissipation of the conventional synchronous switching for Butter-Fly Fat Tree (BFT) topology. Asynchronous switching is more efficient in CLICHE topology than in both BFT and Octagon topologies achieving higher power reduction 75.7%. Asynchronous switching becomes more efficient as technology advances and network density increases. A reduction in power dissipation reaches 82.3% for 256 IPs with the same chip size. Even with clock gating, asynchronous switching achieves significant power reduction 77.7% for 75% clock activity factor.

Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

Sophisticated on-chip interconnects using packet and circuit switching techniques were recently proposed as a solution to non-scalable shared-bus schemes currently used in Systems-on-Chip (SoCs) implementation. Different interconnect architectures have been studied and adapted for SoCs to achieve high throughput, low latency and energy consumption, and efficient silicon area. Recently, a new on-chip interconnect architecture by adapting the WK-recursive network topology structure has been introduced for SoCs. This paper analyses and compares the energy consumption and the area requirements of Wk-recursive network with five common on-chip interconnects, 2D Mesh, Ring, Spidergon, Fat-Tree and Butterfly Fat-Tree. We investigated the effects of load and traffic models and the obtained results show that the traffic models and load that ends processing elements has a direct effect on the energy consumption and area requirements. In these results, WK-recursive interconnect generally has a higher energy consumption and silicon area requirements in heavy traffic load.