Abstract
AbstractAn asynchronous architecture is proposed to achieve a low‐power network‐on‐chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEJ Transactions on Electrical and Electronic Engineering
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
