Bus Switching Research Articles

A Coordinated Reclosing Strategy for Maintained Transformer in Offshore Wind Power Systems

Offshore wind power generation system needs to consider the maintained transformers to reclose. The close loop operation can meet the requirement for reclosing the maintained transformer and maximize the use of wind resources without disconnecting wind turbines. However, close loop operation will cause system damping which can easily cause system instability and protection maloperations. To suppress close loop current damping, a flexible reclosing strategy is proposed that coordinates control of the main bus switch and transformer-connected flexible switch which consists of a damping buffer branch and pass branch. The coordinated control of switches realizes the optimized reclosing state of the maintained transformer. Finally, case studies are established in PLECS simulation software to evaluate the effectiveness of the proposed flexible reclosing strategy to eliminate the reclose damping oscillation for maintained transformers in offshore wind power generation systems.

Computer Redundancy Management Technology Based on Non-Similar Platform

In order to study an efficient and reliable platform management computer, a non-similar platform management computer technology is designed. According to the structural characteristics of the computer management platform, a redundancy management strategy is developed. The redundancy management strategy of processor is studied. Then the priority order and voting strategy of four processors are determined, and several typical failure modes in practical work are discussed in detail. In order to verify the correctness of the synchronization strategy and redundancy management strategy, the principle prototype was tested, including the test of synchronization accuracy, typical debugging results and double redundant bus switching effect. The results show that the system runs stably and the four processor has good synchronization. It can achieve two fault works and three fault safeties, and it can realize bus switching.

Circuit implementation of power converter for high-speed switching operations

Recently, high di/dt and dv/dt switching operations of power converter circuits has been discussed for realizing a high-efficiency power converter circuit. In this case, parasitic inductances of the bus bar between a DC capacitor and power devices may cause issues of overshoot voltage and electromagnetic interference(EMI) noise. Therefore, it is necessary to design the bus bar geometry while considering the minimization and optimization of the parasitic inductance of bus bar. This paper discusses a relationship between bus bar geometry and switching characteristics. In addition, the bus bar analysis is based on the PEEC method, and the bus bar geometry is designed by considering the stray inductance with using an inductance-map method. Moreover, this paper also presents a design procedure of acceptable stray inductance based on a standardization method. It should be noted that the stray inductance is designed not for minimization, but optimization, and it is shown not as an absolute value(H), but as a percentage value(%). Finally, the oscillation waveforms under turn-off operation will be discussed depending on the bus bar geometry.

Design and characterization of Au/In4Se3/Ga2S3/C field effect transistors

Abstract In the current work, the structural and electrical properties of the In4Se3/Ga2S3 interfaces are investigated. The X-ray analysis which concern the structural evolutions that is associated with the substrate type has shown that the hexagonal κ-In2Se3 and the selenium (rhombohedral) rich orthorhombic In4Se3 phases of InSe are grown onto glass and gold substrates, respectively, at substrate of temperature of 300 °C in a vacuum media. The coating of the κ-In2Se3 and of In4Se3 with amorphous layer of Ga2S3 is accompanied with uniform strain. The In4Se3/Ga2S3 interface is found to be of attractive quantum confinement features as it exhibited a conduction and valence band offsets of 0.20 and 1.86 eV, respectively. When the Au/In4Se3/Ga2S3 interface was contacted with carbon metallic point contact, it reveals a back to back Schottky hybrid device that behaves typically as metal–oxidesemiconductor field effect transition (MOSFET). The depletion capacitance analysis of this device revealed built in voltage values of 1.91 and 1.64 V at the Au and C sides, respectively. The designed MOSFET which is characterized in the frequency domain of 0.01–1.80 GHz is observed to exhibit, resonance-anti-resonance phenomena associated with negative capacitance effect in a wide domain of frequency that nominate it for applications in electronic circuits as parasitic capacitance minimizer, bus switching speed enhancer and low pass/high pass filter at microwave frequencies.

Quasi‐resonant DC‐link H5 PV inverter

By removing transformer from PV inverters, they become more attractive for distributed power generation systems. Regardless of their some extra leakage currents, transformer-less inverters would be more advantageous regarding their higher efficiency. However, using traditionally hard-switching converters still causes to drastic switching losses, high di/dt and electromagnetic interference. Quasi-resonant DC-link techniques have promising features to provide zero-voltage switching (ZVS) condition for full bridge inverters, but they are not suitable for transformer-less PV inverters due to consequent high leakage current. In this study, a transformer-less PV inverter is proposed by adapting a proper quasi-resonant DC-link technique to the H5 topology. Using only two auxiliary switches, ZVS turn on and turn off for high-frequency bus switch and ZCS turn on and ZVS turn off for high-frequency switches of the bridge as well as ZVS turn on and turn off of the antiparallel diodes of main switches are realised. Zero current switching (ZCS) turn on and ZVS turn off for auxiliary switches and ZVS turn on and ZCS turn off for antiparallel diodes are also provided. To verify the proposed circuit operation, a 20 kHz 1 kW quasi-resonant DC-link H5 PV inverter prototype is implemented and operation characteristics, soft switching conditions and design rules are confirmed.

The Research and Implementation of Intelligent Judgment about Bus Switching Based on the Automation System

The design of the GIS (Gas Insulated Switchgear) equipment fully enclosed, when it reduces the problem of interference caused by the external environment and reduces the substation area, it also makes the operator cannot directly observe the status of the device. When the mechanism box cover of knife switch rust, or internal components of knife switch rust, or the actual switching contacts are not in place, but the knife switch position indicator indicating closing, it will easily cause charged prone to pull the knife switch accident happen, especially in the switching operation of the bus, the problem is more prominent. Aiming at the risk of status of the knife position can go wrong, and combined with the current status of the substation, this paper proposes a technology program of intelligent assist judgment about bus switching based on the automation system, which use bus power balance principle and the principle of the three-phase current balance to achieve GIS knife in the switching operation process to determine the location of the intelligent Assistant. This paper uses historical data of scheduling sequence database and historical data of substation automation system to verify the reliability of the algorithm. The intelligent auxiliary judgment module for bus switching based on this paper has been deployed in many substations and verified through switching operation many times, it has good promotional value.

Design and Fabrication of a DC Feeder System of New TF Magnet Power Supply for Accelerator-Based In-Situ Materials Surveillance in Alcator C-Mod

Advanced Plasma Material Interaction (PMI) science requires in-situ time and space-resolved measurements over a large area of Plasma Facing Component (PFC) surfaces to study fuel retention & recovery, erosion & redeposition, material mixing, etc. A novel PFC diagnostic technique Accelerator-based In-situ Materials Surveillance (AIMS) has been developed for Alcator C-Mod. At present, the AIMS covers a relatively small (35 cm) poloidal section of the inner wall PFCs at a single toroidal angle; an upgrade has been proposed which will enable nearly full poloidal (124 cm) and 40 degree toroidal PFC coverage. This paper introduces the design, analysis and fabrication of the new TF magnet power supply system for this upgrade. First, the design of the busbar system and its support structure is described, which are required to carry 15 kA current for long pulse operation of up to 25 minutes and fault condition of 400 kA for 1 second. Additional elements in the power supply system include a bidirectional crowbar, varistor protection assemblies, and a high current bus switch. Secondly, multi-physics analyses involved in the design are presented. Electro-magnetic analysis is performed to evaluate the spreading load of the two current-carrying busbars while Joule heating with thermal racheting analysis is to estimate the temperature rise in the components. Structural analysis taking into account dead weight, thermal expansion, spreading load and seismic load is performed. All analyses are completed using finite element analysis software COMSOL. Analytical calculations are included to validate the FEA results. The power supply system is ready for fabrication.

Asymmetry Three-Level Gird-Connected Current Hysteresis Control With Varying Bus Voltage and Virtual Oversample Method

Grid-connected current control plays an important role in the renewable grid-connected system. This paper investigates the grid-connected current hysteresis control of the asymmetry three-level inverter. In order to effectively utilize asymmetry three-level inverter and conquer the disadvantages of traditional hysteresis control, the multistage hysteresis control and current predict hysteresis control are developed. In the multistage hysteresis control method, the switching times of main switches can be declined by regularly adjusting the bus voltage without altering the inductor and bandwidth. In addition, the current predict hysteresis control is developed, which adapts to proper bus voltage without dividing bus switching time. In order to overcome the invalidation issue of the bandwidth in hysteresis control, virtual sample technology is used without increasing real sample frequency. Both simulation and experimental tests have been conducted to verify the efficacy of the proposed methods.

海洋能多能互补智能供电系统总体设计

为解决海洋能不稳定、难以实现独立或并网供电的问题，提出多能互补发电方案。本文所设计的海洋能多能互补智能供电系统综合利用波浪能、潮流能、海上风能和太阳能，填补了多能互补供电系统在海洋能利用领域的空白。该系统包括海洋能发电装置、并网控制柜、汇流开关柜、操控台和储能系统，可将多路海洋能发电装置的电力输入转为三相380 V/50 Hz交流输出，具有发电调度功能和可靠的系统安全保护功能，解决了海洋能多路输入、平稳输出的问题，实现了海洋能的并网供电，对海洋能的综合开发利用有着重要影响。 On account of its high instability, marine energy is difficult to generate electricity independently or realize electricity incorporation. To solve this problem, multi-energy complement electric scheme is proposed. The intelligent hybrid electricity system for marine energy in this paper utilizes wave energy, tidal energy, offshore wind energy and solar energy comprehensively, filling in gaps of pluripotent complementary power supply system in the use of marine energy. The intelligent electricity system is composed of marine energy power generation devices, gird-connected control cabinet, bus switch cabinet, console, and energy storage system. The power input of multipath marine energy power generation devices can be changed into three-phase AC output of 380 V/50 Hz. Power generation dispatching and system security function can be realized. The intelligent electricity system solves the stable output problem of marine energy, makes it possible to access the electric grid, and benefits the comprehensive development and utilization of marine energy.

Analog-Digital Power System State Estimation Based on Information Theory—Part I: Theory

This paper is the first of a two-part series on a novel method of power system state estimation that makes use of information theory to calculate an accurate real-time power system model from a set of analog and digital measurements. This proposed minimum-information-loss (MIL) method is distinguished in that it seamlessly unifies the maximum a-posteriori estimation of both analog and digital quantities such as bus voltages and switch statuses. Both analog and digital estimation residuals are obtained. MIL takes into account the a priori probabilities of the quantities to be measured and the losses incurred along the measurement's information channels with noise when minimizing the overall loss of information. For the identification of network topology errors and switch statuses, MIL processes digital data directly without using auxiliary analog pseudo-measurements. It is shown that the well-known weighted-least-square (WLS) estimation is obtained as a special case of the comprehensive MIL state estimation.

A Bus Switch Coding System with Minimal Hardware Demand

A Bus Switch Coding System with Minimal Hardware Demand

Bus-Invert 로직변환을 이용한 새로운 저전력 버스 인코딩 기법

UDSM(Ultra Deep SubMicron)기술을 이용한 시스템 온-칩 설계 시 가창 중요한 설계 요소는 버스 상에서의 전력소모와 지연시간을 최소화 하는 것이다. 인접한 선에서 발생되는 crosstalk는 전파 지연을 발생시키는데 지대한 영향을 미치며, 이를 제거하거나 최소화 시키는 일은 SoC(System on a Chip) 설계에서 시스템의 신뢰성 및 성능 향상과 직결된다. 기존의 방법들은 주로 crosstalk 지연이나 버스 스위칭 횟수 중 하나 만을 최소화하는 방법이 제안되었다. 본 논문에서는 인코딩 적용 4 비트 클러스터 상의 버스 스위칭 횟수에 따라 crosstalk과 스위칭 횟수를 동시에 최소화 할 수 있도록 "invert" 기능과 "logic-convert" 기능을 적응적으로 선택하는 새로운 인코딩 기법을 제안한다. 실험결과 제안한 버스 인코딩 기법은 완벽하게 crosstalk 지연를 제거한 반면, 기존의 다른 방법들에 비해 25% 이상 전력을 절약하였음을 보여준다. In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.

Exploring the IEEE C37.234 Guide for Protective Relay Application to Power System Buses

This paper summarizes the IEEE C37.234-2009 Guide for Protective Relay Applications to Power System Buses. In the Guide, concepts of power bus protection are discussed. Consideration is given to availability and location of breakers, current transformers, and disconnectors as well as bus switching scenarios, and their impact on the selection and application of bus protection. A number of bus protection schemes are presented; their adequacy, complexity, strengths and limitations with respect to a variety of bus arrangements are discussed; specific application guidelines are provided for a variety of situations. Breaker failure protection is discussed as pertaining to bus protection. Means of securing bus protection schemes against corrupted relay input signals are also included.

A Reflective NetGAP Design and its Session Mechanism Realization based on Agent

Adopting expert hardware to physical isolate the Trusted network from the Non-Trusted network can prevent all kinds of attack basing on network layer and operating system layer etc. This paper comes up with network isolation system model based on Reflective architecture. The Reflective GAP is hardware-based and its purpose is to rapidly mirror buffers between the Non-Trusted memory and the Trusted memory. We realize it by LVDS bus and high speed double switch technique. Its activities are achieved using store & forward of memory blocks. Its software system comprises with seven main basic modules. Its session strides over both sides of the network. Based on several kinds of agent component with file accumulation, content inspection, file transmittance, protocol stream control and so on, it can easily establish a new connection, dealt with protocol events and close a connection process in a session. According to practice it indicates the session mechanism basing on agent can effectively increase the security of the internal network and keep the adaptability of network security system.

Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems

Gray code bus encoding is a simple approach to reduce instruction address bus switching. It requires little encoding hardware and no additional bus lines. Our analytical study reveals that with Gray encoding the address bus switching can be reduced by nearly 50%, for long, sequentially accessed code. However, existing Gray bus encoding techniques involve decoding the Gray coded bus, which is expensive in terms of performance and area, and has stymied efforts to implement such a coding scheme in real systems. Furthermore, based on our experimental investigation on a set of benchmarks, the Gray bus encoding may be much less effective than expected - the switching reduction rate can be as low as under 30%. This paper presents a design approach to enable the use of Gray encoding by avoiding the bus decoding operation and to enhance the switching reduction efficiency by using a shifted Gray code for a given application. The experiment results show that our design approach can improve bus switching reduction rate by up to 22.55%, with little overhead on design logic and performance.

DC-bus power quality for aircraft power systems during generator fault conditions

Higher-voltage, 540 V, aircraft DC-bus power quality is examined experimentally and by computer simulation during a short-circuit fault across the phase terminals of a 70 kW, five-phase, permanent magnet fault-tolerant generator. The DC-bus transients caused by the short-circuiting of the generator phases are seen to exceed the limits in MIL-STD-704F and a control algorithm is proposed for a supercapacitor-based energy storage device that mitigates the transients. The controller performance is illustrated by computer simulations for a range of bus switching scenarios.

Energy-efficient encoding techniques for off-chip data buses

Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as they consume a significant amount of total power. Since the bus power consumption is proportional to the switching activity, reducing the bus switching is an effective way to reduce bus power. While numerous techniques exist for reducing bus power in address buses, only a handful of techniques have been proposed for data-bus power reduction, where frequent value encoding (FVE) is the best existing scheme to reduce the transition activity on the data buses. In this article, we propose improved frequent value data bus-encoding techniques aimed at reducing more switching activity and, hence, power consumption. We propose three new schemes and five new variations to exploit bit-wise temporal and spatial locality in the data-bus values. Our techniques just use one external control signal and capture bit-wise locality to efficiently encode data values. For all the embedded and SPEC applications we tested, the overall average switching reduction is 53% over unencoded data and 10% more than the conventional FVE scheme.

An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction

This paper presents a bus coding methodology for the instruction memory data bus switching reduction. Compared to the existing state-of-the-art multiway partial bus-invert (MPBI) coding which relies on data bit correlation, our approach is very effective in reducing the switching activity of the instruction data buses, since little bit correlation can be observed in the instruction data. Our experiments demonstrate that the proposed encoding can reduce up to 42% of switching activity, with an average of 30% reduction, while MPBI achieves just 17.6% reduction in switching activity.

Fuzzy Control of Coding Schemes for Reducing Energy Dissipation in Off-Chip Buses

In this paper, we proposed an high-speed and low-power off-chip data bus interface based on the best coding schemes in this hard operative condition. We analyzed the clustered bus invert method and the bus switch coding, a newly proposed approach based on bus lines logically re-ordered. We proposed an high speed and low-power bus interface based on the combined employment of these two approaches controlled by a 9-rules Takagi-Sugeno analog fuzzy controller. The controller analyzes the binary traffic statistical property changing on the fly the used coding scheme. The fuzzy controller has been designed taking care of total energy dissipation such to do not compromise the benefit of coding approaches. The controller is able also to re-configure the bus switch sub-section in an operative condition where original approach introduces strong power losses. We demonstrated the effectiveness of the approach designing at transistor level the analog fuzzy controller and the digital part of the bus interface. Simulation conducted with H-SPICE and NANOSIM confirmed the bus interface is the optimal trade-off for reducing dynamic energy in off-chip buses.

Simultaneous switching noise analysis: The relation between bus layout, coding and switching patterns

Simultaneous switching noise analysis: The relation between bus layout, coding and switching patterns