Abstract
Recently, high di/dt and dv/dt switching operations of power converter circuits has been discussed for realizing a high-efficiency power converter circuit. In this case, parasitic inductances of the bus bar between a DC capacitor and power devices may cause issues of overshoot voltage and electromagnetic interference(EMI) noise. Therefore, it is necessary to design the bus bar geometry while considering the minimization and optimization of the parasitic inductance of bus bar. This paper discusses a relationship between bus bar geometry and switching characteristics. In addition, the bus bar analysis is based on the PEEC method, and the bus bar geometry is designed by considering the stray inductance with using an inductance-map method. Moreover, this paper also presents a design procedure of acceptable stray inductance based on a standardization method. It should be noted that the stray inductance is designed not for minimization, but optimization, and it is shown not as an absolute value(H), but as a percentage value(%). Finally, the oscillation waveforms under turn-off operation will be discussed depending on the bus bar geometry.
Highlights
In recent years, a power semiconductor device capable of high-speed and high-frequency switching has been developed[1-5], and further higher power density of the power converter circuit has become possible
The influence on the parasitic inductance of the DC side wiring between DC capacitor and power devices may occur, and many papers have reviewed this through simulation and experimentally[6-11]
The parasitic inductance of the DC side wiring is determined by the wiring geometry connecting the DC capacitor and the semiconductor device
Summary
A power semiconductor device capable of high-speed and high-frequency switching has been developed[1-5], and further higher power density of the power converter circuit has become possible. By reducing the parasitic inductance, it is possible to suppress the overshoot voltage during the turn-off operation Both the switching loss and electromagneticon noise largely differs depending on driving conditions of power semiconductor. A bus bar geometry capable of low parasitic inductance and large current capacity has been adopted in the power conversion circuit. Generalpurpose electromagnetic field analysis software[17-18] using finite element method is applied It is very useful for analysis of the complicated wiring structure and influence of the current distribution inside the bus bar. This paper presents a design procedure of acceptable stray inductance based on a standardization method. By applying the proposed method, a maximum stray inductance can be designed for power electronics circuits, considering the voltage and the current ratings of semiconductor devices. The oscillation waveforms under turn-off operation will be discussed depending on the bus bar geometry
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