Bus Protocol Research Articles

Research and Development on Safety Monitoring Network System for Electric Locomotive Servicing Work

A safety network system is designed based on PROFIBUS-DP field bus, according to actual servicing work situation and control requirements for electric locomotive servicing work. The system realizes communication between first class master station and third equipment through using PROFIBUS-DP bus protocol. It also realizes interactive operation between slave station and non-contact IC card, meanwhile, slave station and MCU system. In addition, this article has analyzed the multi-task scheduling mechanism and data communication security on monitoring network system in detail as well. Results show that the system has higher application value through entire debugging and testing on network control system.

Design and Implementation of Hybrid Electric Vehicle Control System CAN Communication

Based on the vehicle CAN bus technology, with features of Hybrid Electric Vehicle (HEV) control network be concerned, CAN bus protocols of application layer suitable for HEV are developed in the paper. And control network is built based on multi-master CAN distributed control technology. Through CAN controller programming of DSP, supported by the corresponding external drive circuit, the motor controller nodes is connected with the vehicle CAN network. Finally the CAN Bus communication of HEV energy assembly control system is designed and realized. Experimental result indicates that the system works well with stable signal and strong anti-jamming ability, and the communication with HEV CAN bus is realized successfully.

Optimized System-on-Chip Integration of a Programmable ECC Coprocessor

Most hardware/software (HW/SW) codesigns of Elliptic Curve Cryptography have focused on the computational aspect of the ECC hardware, and not on the system integration into a System-on-Chip (SoC) architecture. We study the impact of the communication link between CPU and coprocessor hardware for a typical ECC design, and demonstrate that the SoC may become performance-limited due to coprocessor data- and instruction-transfers. A dual strategy is proposed to remove the bottleneck: introduction of control hierarchy as well as local storage. The performance of the ECC coprocessor can be almost independent of the selection of bus protocols. Besides performance, the proposed ECC coprocessor is also optimized for scalability. Using design space exploration of a large number of system configurations of different architectures, our proposed ECC coprocessor architecture enables trade-offs between area, speed, and security.

Implementing serial bus interfaces using general purpose digital instrumentation

While a dedicated test instrument can offer more targeted test capabilities for serial bus interfaces, a solution built around a general-purpose digital test instrument can offer flexibility that is unmatched in a dedicated bus test tool. This includes the flexibility to adapt to multiple bus environments, adapt to changing test conditions, support non-standard protocols (data rates, timing, or message sizes), provide synchronization for external equipment to time-specific bus events, as well as support other static and dynamic digital test needs. A general purpose solution can reduce the footprint of the test system and reduce the test equipment learning curve as the test engineer is working with one instrument or learning one programming language. Supporting multiple serial busses with one general-purpose instrument also means that the test engineer needs to interface with only one vendor should technical support be required. Finally, significant cost savings can be realized as the number of different bus protocols that need to be supported increases, while the hardware investment does not. Ultimately, the goal is to identify those instances where the clever or novel application of a general-purpose digital test tool is appropriate and provides tangible benefits in time, cost flexibility and effective utilization of resources.

Development and Research on Embedded Fieldbus Protocol Conversion Gateway

Profibus and CAN bus are two kinds of widely used field bus in the industrial control field. However, this two bus protocol conversion devices are not introduced on the market, it can not meet the needs of users. Therefore, the design of a Profibus and CAN protocol translation ngateway is very important. By comparing the OSI reference model, the same points of Profibus and CAN bus can be found, their communication model structure is streamlined by the OSI model, they are only three layers, which makes it possible to interconnect them. This paper designs an embedded protocol conversion gateway, S3C2410 processor is used as main controller, SPC3 and SJA1000 are selected as Profibus and CAN protocol chips. The design has realized Profibus and CAN bus protocol conversion, using this gateway in industrial field can bring certain economic benefits for the enterprise.

HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms

Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.

Design and implementation challenges for adoption of the IEEE 1500 standard

The IEEE 1500 standard for embedded core test, approved in 2005, defines a scalable and reusable wrapper architecture that allows the testing of, and access to, embedded cores within a system on chip (SoC). The wrapper is controlled using a Wrapper Instruction Register (WIR), and has serial and parallel ports for test access mechanisms (TAMs) to deliver test vectors to the cores under test. In this study, the authors consider two implementation challenges that are outside the IEEE 1500 standard: how multiple WIRs within a SoC are controlled and accessed and also the TAM architecture. The authors present novel solutions to both challenges in the form of a test controller to interface with the embedded IEEE 1500 structures and also a TAM architecture that reuses the physical interconnections of an on-chip system bus. The test controller facilitates concurrent test of multiple IEEE 1500 wrapped cores in an SoC through the IEEE 1149.1 test access port (TAP). Reusing the physical interconnections of the system bus as a TAM is not dependent on the system bus protocol or functionality.

Task Allocation and Optimization of Distributed Embedded Systems with Simulated Annealing and Geometric Programming

We consider the task model of periodic tasks running on a network of processor nodes connected by a bus based on the time-triggered protocol, an industry-standard bus protocol designed for safety-critical automotive and avionics distributed embedded systems, and present an integrated optimization framework that jointly considers one or more of the following attributes: task-to-processor allocation, task priority assignment, task period assignment and bus access configuration. We adopt a hierarchical optimization framework, where each possible task allocation and priority assignment is treated as one top-level coarse-grained state, which may contain many lower-level fine-grained states defined by different task period assignments and bus access configurations. Simulated annealing is used to explore the top-level states, which calls a geometric programming solver as a subroutine to explore the lower-level states contained within a given top-level state. Performance evaluation shows that our framework has good performance in terms of solution quality and scalability.

DeviceNet network health monitoring using physical layer parameters

Since the 1980s, the manufacturing environment has seen the introduction of numerous sensor/actuator bus and network protocols for automation systems, which led to increased manufacturing productivity, improved inter- changeability of devices from different vendors, facilitated flexibility and reconfigurability for various applications and improved reliability, while reducing installation and maintenance costs. However, such heightened manufacturing integration facilitated by industrial networks also leads to dramatic consequences of improper or degraded network operation. This paper presents a novel Network Health Management system that provides diagnostic and prognostic information for DeviceNet at the device and network level. It extracts features from analog waveform communication signals, as well as logic and timing features from digital packet logs. These features are used to evaluate the network system performance degradation by applying multidimensional clustering techniques. In addition, this work proposes a hybrid prognostics structure using combined physical and logic layer features to provide fault location information that cannot easily be realized with analog or digital data independently. Furthermore, an intermittent connection diagnostic algorithm which analyzes patterns of interrupted and error packets on the network was developed. This tool can be used as a packet source identification method which uses joint analog features and digital information inferred from analog waveforms. A test-bed was constructed and the experiments of network impedance mismatch, cable degradation, and intermittent connections were conducted in laboratory environment. Experimental results show that the proposed system can detect degradations of the network and identify the location of the intermittent connection successfully. Field tests performed in an industrial environment were also conducted and their results are discussed.

The Design of RS232 and CAN Protocol Converter Based on PIC MCU

CAN bus will be increasingly used in wide range of applications for its superiority, but it couldn’t communicate with computer directly. The article describes the design of RS232 and CAN bus protocol converter depending on PIC Microcontroller, which solves the problem that CAN networks can not directly communicate with PC. At present, single-chip microcomputer of 51 series with CAN controller SJA1000 are widely used in domestic. Considering cost and converter size, the paper will talk about PIC18F2580 with integrated CAN microcontroller designed for RS232 and CAN protocol converters to facilitate the direct communication between computers and CAN bus.

Provably correct on-chip communication

Hardware module reuse is a standard solution to the problems of increasing complexity of chip architectures and pressure to reduce time to market. In the absence of a single module interface standard, predesigned modules for “plug-and-play” usually require a converter between incompatible interface protocols. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the HDL implementation level or grossly simplify the structure of the protocols considered. This work presents a state-machine-based formalism for modeling bus-based communication protocols and a notion of protocol compatibility and of correct conversion between incompatible protocols. This formalism is used to derive algorithms for checking protocol compatibility and for provably correct, automatic converter synthesis. Experiments with automatic converter synthesis between different configurations of widely used commercial bus protocols, such as AMBA AHB, ASB APB, and the Open Core Protocol (OCP) are discussed. The work here is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modeling of protocol characteristics that is also close to HDL.

A Phase-Based Approach for On-Chip Bus Architecture Optimization

As the integration scale of a chip increases, on-chip interconnects suffer from the increased area occupied by a large number of bus signals. To reduce the overhead for communication, this paper formulates a new concept of an on-chip communication approach, called phase-based interconnection, with an example protocol, system-on-chip network protocol (SNP). In the phase-based communication, a small number of signals called phase signals are used to distinguish the types of signals transmitted through the main communication channel. To identify transactions transmitted through the channel, the SNP protocol defines the allowed sequence of phases for each transaction. A theoretical framework provides conditions for a phase-based protocol to allow immediate decoding of transactions. Simulation results show that the bandwidth of SNP is greater than that of a de facto standard bus protocol although SNP has wires only about three-fifths of the standard bus protocol. Although the signal-toggling rate is increased because of the multiplexed transmission of various signals through a single communication channel, simulation results show that the increase is not significant for multimedia applications that frequently transmit burst transfers. The phase omission of SNP helps to reduce the transaction failure rate to 65% while the hardware implementation cost for the support of phase omission is negligible.

Transmission of moving images via Flexray

Within a feasibility study Fujitsu Microelectronics Europe GmbH (FME) and the Laboratory for Embedded Systems at the University of Applied Science, Aschaffenburg, installed a Flexray system as a prototype to transmit moving images. The intention was to find out whether the bus protocol is suitable for transmitting moving images without having to install a multimedia network. The article explains technical aspects, presents results and possible applications.

A Hierarchical Framework for Design Space Exploration and Optimization of TTP-Based Distributed Embedded Systems

Time-triggered protocol (TTP) is a time-division multiple access (TDMA)-based bus protocol designed for use in safety-critical avionics and automotive distributed embedded systems. Design space exploration (DSE) for TTP-based distributed embedded system involves searching through a vast design space of possible task-to-CPU mappings, task/message schedules and bus access configurations to achieve certain design objectives. In this paper, we present an efficient two-level hierarchical DSE framework for TTP-based distributed embedded systems, with the objective of minimizing the total bus utilization while meeting an end-to-end deadline constraint. Logic-based Benders decomposition (LBBD) is used to divide the problem into a master problem of mapping tasks to CPU nodes to minimize the total bus utilization, solved with a satisfiability modulo theories (SMT) solver, and a subproblem of finding a feasible solution of bus access configuration and task/message schedule under an end-to-end deadline constraint for a given task-to-CPU mapping, solved with a constraint programming (CP) solver. Performance evaluation results show that our approach is scalable to problems with realistic size.

Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

A monitor generation method for formal monitor‐based verification considering input constraints

AbstractVarious kinds of methods have been proposed for hardware module interface verification. We focus on monitor‐based formal verification. In our approach, to verify interface specifications more comprehensively, we describe specifications of a module interface in a specification language based on regular expressions, and then behavioral models are constructed. Next, a monitor circuit is generated. This method prevents monitor circuits from involving errors because of automated monitor generation. Usually, input constraints must also be given for a design, when each module is verified one by one, because undesirable input patterns may be provided. Instead of giving input constraints, we propose a method of monitor generation including input constraints. Input constraints are extracted from specification of interfaces. Therefore, verification of individual modules becomes less difficult. We show an experimental result on formal verification of circuits compliant to the AMBA AHB bus protocol. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(12): 19–26, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20360

Hardware accelerated constrained random test generation

Recent design and verification languages, such as SystemVerilog, support a rich test bench language, which provides significant support towards developing layered, structured, constrained random test bench architectures. Typically, the test bench language offers many features that are not synthesisable and therefore cannot be carried into the hardware for hardware accelerated simulation. One of the main challenges in improving the performance of hardware accelerated simulation is to run the task of random value selection under specified constraints in hardware. This problem (possibly for the first time) is addressed and a two-step approach is presented. In the first step, the constraints are pre-processed in software to generate a set of entailed regions. In the second step, random value selection is performed in hardware using the entailed regions pre-computed in the first step. It is shown that this method has modest area overhead and produces constraint satisfying random valuations within very few cycles. Results on test bench architectures for the ARM AMBA Bus and IBM CoreConnect protocol suites have been reported.

A New Trace-Driven Shared-Memory Multiprocessors Machine Simulator

As the gap between processor and memory speeds continues to widen, methods for measuring memory system designs before they are implemented in hardware are becoming increasingly important. The performance of the bus protocol maintaining the coherence of the same data in all caches for the shared-memory multiprocessors can be measured in advance by many analytical methods, the inevitable use of a simplified assumption to analyze a computer system with increasing complexity restrictions the predetermined conditions of the analytical results. The study introduces the development, implementation and future work for a trace-driven memory simulator for shared-memory multiprocessors. The simulator can measure the performance for different multiprocessors architectures under real operating systems and applications as a reference for the decision on the design or modification of the system, with the aim of increasing production efficiency and save R&D expenses.

Availability of ARINC 629 Avionic Data Bus

The three traditional objectives of computer security are confidentiality, integrity and availability. Availability can be defined as the prevention of denial of service. Confidentiality and integrity have been addressed in several theoretical works whereas the concept of availability has not been much investigated by the scientific community. This paper is an attempt to define through a case study the concept of availability. We first define a set of availability constraints that avionic data bus protocols should enforce. Then, we consider the ARINC 629 Basic Protocol (BP) and the ARINC Combined Protocol (CP) which were implemented on the Boeing 777. We check whether these protocols respect our availability constraints or not.

CTL-property Transformations along an Incremental Design Process

This paper formalizes an incremental approach to design flow-control oriented hardware devices described by Moore machines. The method is based on successive additions of new behaviours to a simple device in order to build a more complex one. The new behaviours added must not override the previous ones. A set of CTL formulae is assigned to each step of the design. The links between the formulae of two consecutive design steps are formalized as a set of formula-transformations F, stating that: for all CTL formula f with atomic propositions related to step i, f is satisfied on a design at step i, iff F(f) is satisfied on the design extended at step i + 1. This result extends the classical CTL property preservation results in a particular context. Moreover, it simplifies the writing of properties for a new device. This approach has been applied in the design of bus protocol converters and the transformations were useful to perform non-regression analysis. It could also be applied in order to simplify both system and formulae in particular cases.