Burn-in Test Research Articles

Effective mitigation of photodarkening-induced transverse mode instability in a monolithic fiber laser oscillator by 450 nm laser irradiation.

The photodarkening (PD) and transverse mode instability (TMI) effects are two main factors limiting the power increase and long-term stability of high-power fiber lasers. A prolonged burn-in test for an all-fiber laser oscillator below the TMI threshold was carried out. We observed the PD-induced TMI effects, which manifested as a sudden decrease in the output power due to higher-order mode leakage. After several minutes of exposure to a high-power density 450 nm laser diode (LD), the output power returned to its initial state, significantly enhancing the oscillator's stability. The 450 nm LD probably mitigates the accumulation of thermal effects by inhibiting the photodarkening effect, thus preventing the occurrence of the TMI effects and improving the stability of the oscillator's output power. Our work provides useful guidance for the development of high-stability fiber laser oscillators.

Burn-in test and thermal performance evaluation of Silicon Photomultipliers for the JUNO-TAO experiment

This study evaluates more than 4,000 tiles made of Hamamatsu visual-sensitive silicon photomultipier (SiPM), each with dimensions of 5 × 5 cm2, intended for the central detector of the Taishan Anti-neutrino Observatory (TAO), a satellite experiment of the Jiangmen Underground Neutrino Observatory (JUNO) aimed at measuring the reactor anti-neutrino energy spectrum with unprecedented energy resolution. All SiPM tiles underwent a room temperature burn-in test in the dark for two weeks, while cryogenic testing analyzed the thermal dependence of parameters for some sampled SiPMs. Results from these comprehensive tests provide crucial insights into the long-term performance and stability of the 10 square meters of SiPMs operating at -50°C to detect scintillation photons in the TAO detector. Despite some anomalies awaiting further inspection, all SiPMs successfully passed the burn-in test over two weeks at room temperature, which is equivalent to 6.7 years at -50°C. Results are also used to guide optimal SiPM selection, configuration, and operation, ensuring reliability and sustainability in reactor neutrino measurements. This work also provides insights for a rapid and robust quality assessment in future experiments that employ large-scale SiPMs as detection systems.

N-BIR: A NUMERIC OPTIMIZATION APPROACH FOR POWER ELECTRONIC CONVERTER BURN-IN TESTING TIME REDUCTION

Burn-in testing is an effective method for detecting early faults in electronic products before they reach the market. This test has a high cost due to lengthy test time on a test bench. In this paper, we propose N-BIR (Numeric optimization approach for power electronic Burn-In testing time Reduction), an algorithm capable of predicting the burn-in (BI) test temperature of power electronic converters, intending to shorten the duration of such tests. This algorithm optimizes by least squares a theoretical model of the system, using as data a fraction of the total burn-in test. Moreover, not only is it capable of making accurate predictions, but it also accompanies them with a prediction interval (PI), so that the algorithm itself can quantify how confident it is of its predictions. We show that using 40% of a conventional rolling test total, our algorithm outperforms several of today's most common Machine Learning (ML) algorithms. Furthermore, we show that it can reduce burning time by 50% to 60% by making accurate predictions, which makes it possible to identify a significant portion of converters that don't require full testing, ultimately lowering costs and boosting productivity. Keywords: Burn-in temperature prediction, Burn-in time reduction, Levelized Cost of Energy, Machine Learning, Electronic Power Converter, Reliability.

A tale of three failure-oriented-accelerated-test (FOAT) types and their roles in assuring aerospace electronics-and-photonics reliability: Perspective

Our “tale of three failure-oriented-accelerated-test (FOAT) types” includes (chronologically) 1) some product development tests (such as, e.g., shear-off or temperature cycling tests), 2) FOATs at the design stage (that should be applied, when a new technology, a new design or a new application of an existing aerospace electronic or a photonic product is considered, and suitable HALTs are not developed yet) and 3) Burn-in-tests (BITs). Their roles, significance and attributes are indicated and briefly discussed.

Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT

Throughout device testing, one key parameter to be considered is the switching activity (SWA) of the circuit under test (CUT). To avoid unwanted scenarios due to excessive power consumption during test, in most cases the SWA of the CUTs must be retained to a minimal value when the test stimulus is applied. However, there are specific cases where the opposite, namely the SWA maximization within the CUT, or a certain sub-module of it, can be proven beneficial. For example, during dynamic Burn-In testing we aim at maximizing the internal stress by applying suitable stimuli. This can be done in a functional manner by following the Software-Based Self-Test paradigm. However, generating such suitable programs represents a costly and arduous task for the test engineers. We consider the case where the CUT is a pipelined processor core and we aim to maximize the SWA of certain core sub-modules. We present a comprehensive methodology based on formal methods, able to automatically generate the best two-instruction stress-inducing sequence for the targeted processor module. The generated stimulus is composed of a short, arbitrarily-long repeatable sequence of a pair of assembly instructions, thus guaranteeing the maximum possible constant switching activity. The proposed method was applied to the OpenRISC 1200 and the RI5CY (PULP) processor cores demonstrating its effectiveness when compared to other methods. We show that the time for generating the best repeatable instruction sequence is limited in most cases, while the generated sequence can always achieve a significantly higher repeatable and constant SWA than other solutions.

Quality assessment and lifetime prediction of base metal electrode multilayer ceramic capacitors: Challenges and opportunities

Base metal electrode (BME) multilayer ceramic capacitors (MLCCs) are widely used in aerospace, medical, military, and communication applications, emphasizing the need for high reliability. The ongoing advancements in BaTiO3-based MLCC technology have facilitated further miniaturization and improved capacitive volumetric density for both low and high voltage devices. However, concerns persist regarding infant mortality failures and long-term reliability under higher fields and temperatures. To address these concerns, a comprehensive understanding of the mechanisms underlying insulation resistance degradation is crucial. Furthermore, there is a need to develop effective screening procedures during MLCC production and improve the accuracy of mean time to failure (MTTF) predictions. This article reviews our findings on the effect of the burn-in test, a common quality control process, on the dynamics of oxygen vacancies within BME MLCCs. These findings reveal the burn-in test has a negative impact on the lifetime and reliability of BME MLCCS. Moreover, the limitations of existing lifetime prediction models for BME MLCCs are discussed, emphasizing the need for improved MTTF predictions by employing a physics-based machine learning model to overcome the existing models’ limitations. The article also discusses the new physical-based machine learning model that has been developed. While data limitations remain a challenge, the physics-based machine learning approach offers promising results for MTTF prediction in MLCCs, contributing to improved lifetime predictions. Furthermore, the article acknowledges the limitations of relying solely on MTTF to predict MLCCs’ lifetime and emphasizes the importance of developing comprehensive prediction models that predict the entire distribution of failures.

A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (MCU) equipped with a couple of embedded processors, some standard common peripheral units, and a few KB memories. Moreover, the proposed Burn-In tester could be integrated into a System Level Test equipment which is typically based on MCUs to communicate functionally with the DUT. This paper provides full details about the architecture of such a low-cost innovative tester, which can supply the DUT with unlimited pseudo-random patterns created autonomously by the MCU firmware from any selected seed. The tester prototype developed to collect experimental results includes a low-cost System-on-Chip based on a multi-core MCU and a set of peripheral cores, encompassing timers and Direct Memory Access modules. The tester prototype is used to stress an automotive chip accounting for about 20 million gates, 700 thousand scan flip-flops, and several scan modes. The combination of pseudo-random pattern generation with the ability to control different scan and Design for Testability (DfT) modes, including LBIST, permits to reach a higher coverage of stress metrics than by the application of a limited set of pre-computed ATPG patterns. The toggle coverage level reached is up to 95.89%. The application speed achieved by the tester with non-optimized connections is up to about 10MHz.

Customizing Random Replacement Model and Flexible Warranty Model from the Perspective of Screening Reliability

In the present academic and engineering fields, every measure function of product reliability is modeled and estimated from the statistical perspective. These indicate that there universally exist differences in the reliabilities of new identical products that survive the burn-in test. On the basis of the differences in the reliabilities of new identical products, designing through-life maintenance models for managing the different reliabilities is a very practical topic for engineering fields. In this study, a random warranty model and a random maintenance model are designed by screening product reliabilities to manage the through-life reliabilities of products. In the random warranty model, the coverage areas of the warranty are set as the different areas for applying flexibility to them to control the warranty costs of new identical products with different reliabilities, and thus this warranty is called a flexible random free repair warranty (FRFRW) model. In the random maintenance model, two random replacement actions are customized by setting different replacement ranges for controlling maintenance costs and lengthening service life. This random maintenance model is called a customized random replacement (CRR), which is used to manage product reliabilities after the FRFRW expiration. These two random models are characterized from the mathematical perspective, and some derivatives of both are provided to model other maintenance problems. The characteristics of every model and the performance of the CRR are explored and illustrated through numerical experiments. The results show that the CRR is superior to random age replacement.

Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques

During device testing, an important parameter to be considered by the test engineers is the switching activity (SWA) of the circuit under test (CUT). It is well known that the SWA must be kept to a minimum in order to avoid catastrophic scenarios on the CUTs, e.g., unacceptable peak power consumption or over-stressing that can lead to an artificial yield loss. However, there are scenarios, where the inverse, namely the switching activity maximization, can be proven beneficial. For example, this happens during Burn-In testing, when we aim at exercising the circuit under extreme operating conditions in terms of temperature and temperature gradients to accelerate aging phenomena in a controlled manner. In some cases, this is achieved by applying to the CUT stimuli in a functional manner, based on the Software-Based Self-Test (SBST) paradigm. Though, the generation of such appropriate programs for this task represents a challenge for the test engineers. In this paper we consider the scenario where the modules to be stressed are the units of a pipelined processor. We present a method, based on an evolutionary approach, that is able to automatically generate maximum stress programs, i.e., sequences of instructions achieving a high switching activity in the target module. With respect to other approaches, the generated sequences are built from the ground-up, are short and repeatable, thus guaranteeing their easy usability to stress a module (and increase its temperature). The processor we used for our experiments is the Open RISC 1200. Results demonstrate that the generated stimuli from the proposed method are effective in achieving a high value of sustained switching activity within the considered processor modules while also achieves a better results when comparing with other methods (e.g., stuck-at oriented test programs).

Modified benders decomposition and metaheuristics for multi-machine parallel-batch scheduling and resource allocation under deterioration effect

Batch scheduling problem is a common difficulty in mass production, which includes many decisions such as grouping, batch ordering, and resource allocation. Motivated by the semiconductor burn-in test process, this paper investigates a combinatorial optimization problem considering the deterioration effect and resource allocation. The objective is to design an appropriate job sequencing and resource allocation scheme to achieve an overall minimization of makespan and resource costs. The problem, subject to parallel-batch, multi-machine, deterioration effect, and resource constraints, is NP-hard. We decompose it into a master problem and a sub-problem based on Benders Decomposition (BD). A cut filtering rule that limits the number of cuts is proposed to control the complexity of the problem. Meanwhile, some structural properties are deduced to guide the design of two algorithms combined with Variable Neighborhood Search (VNS). We conduct extensive simulation experiments on instances of different scales, and the results demonstrate that the cut filtering method can effectively reduce the solution time. In large-scale computational experiments, it is more obvious that the proposed algorithms have good convergence and robustness.

Failure-oriented-accelerated-testing (FOAT) and its role in assuring electronics reliability: review

A highly focused and highly cost-effective failure-oriented-accelerated-testing (FOAT) suggested about a decade ago as an experimental basis of the novel probabilistic design for reliability (PDfR) concept is intended to be carried out at the design stage of a new electronic packaging technology and when high operational reliability (like the one required, e.g., for aerospace, military, or long-haul communication applications) is a must. On the other hand, burn-in-testing (BIT) that is routinely conducted at the manufacturing stage of almost every IC product is also of a FOAT type: it is aimed at eliminating the infant mortality portion (IMP) of the bathtub curve (BTC) by getting rid of the low reliability “freaks” prior to shipping the “healthy” products, i.e., those that survived BIT, to the customer(s). When FOAT is conducted, a physically meaningful constitutive equation, such as the multi-parametric Boltzmann-Arrhenius-Zhurkov (BAZ) model, should be employed to predict, from the FOAT data, the probability of failure and the corresponding useful lifetime of the product in the field, and, from the BIT data, as has been recently demonstrated, - the adequate level and duration of the applied stressors, as well as the (low, of course) activation energies of the “freaks”. Both types of FOAT are addressed in this review using analytical (“mathematical”) predictive modeling. The general concepts are illustrated by numerical examples. It is concluded that predictive modeling should always be conducted prior to and during the actual testing and that analytical modeling should always complement computer simulations. Future work should be focused on the experimental verification of the obtained findings and recommendations.

Sabic introduces LNP™ Konduit™ compound suitable for complex DDR memory IC test sockets and ramps up PCR-offerings

On November 28, SABIC introduced LNP™ KONDUIT™ 8TF36E compound, a new specialty material that should help address the stringent demands of burn-in test sockets (BiTS) used to stress-test double-data-rate (DDR) memory integrated circuits (ICs). As the number of pins and the testing temperature for DDR ICs increase and their dimensions shrink, materials used in BiTS components must deliver enhanced properties. SABIC’s new compound reportedly provides very high flow to help enable complex, miniaturized BiTS designs, excellent dimensional stability and high temperature resistance to enhance BiTS functionality during testing, and high thermal conductivity to rapidly dissipate heat afterwards.

A Burn-in Test Station for the ATLAS Phase-II Tile-Calorimeter Low-Voltage Power Supply Transformer-Coupled Buck Converters

The upgrade of the ATLAS hadronic tile-calorimeter (TileCal) Low-Voltage Power Supply (LVPS) falls under the high-luminosity LHC upgrade project. This article serves to provide an overview of the development of a burn-in test station for a Phase-II upgrade LVPS component known as a Brick. These Bricks are radiation hard transformer-coupled buck converters that function to step-down bulk 200 V DC power to the 10 V DC power required by the on-detector electronics. To ensure the high reliability of the Bricks, once installed within the TileCal, a burn-in test station has been designed and built. The Burn-in procedure subjects the Bricks to sub-optimal operating conditions that function to accelerate their aging as well as to stimulate failure mechanisms. This results in elements of the Brick that would fail prematurely within the TileCal failing within the burn-in station or to experience performance degradation that can be detected by followup testing effectively screening out the ’weak’ sub-population. The burn-in station is of a fully custom design in both its hardware and software. The development of the test station will be explored and the preliminary burn-in procedure to be employed will be presented. The commissioning of the burn-in station will be presented along with a summary and outlook of the project.

Visualization of localized facet Joule heating induced optical degradation on mid-infrared quantum cascade lasers.

Reversible lasing performance degradation is investigated on an uncoated actively- biased GaAs/Al0.45Ga0.55As mid-infrared quantum cascade laser (MIR-QCL) facet. The surface temperature rises (ΔT) on the MIR QCL are characterized before and after the device undergoes an accelerated aging burn-in test, followed by hydrogen plasma treatment. The data is visualized by spatially resolved time-domain thermoreflectance (SR-TDTR) microscopy. On the laser facet, ΔT decreases with a drop in lasing performance and ΔT increases with an increase in lasing performance. Along the laser cavity, the thermal property change is negligible before and after the aging test, independent of the optical performance change. The results verify that thermal-induced facet oxidation is the main reason for the rapid degradation of the lasing performance in the early aging stage.

Predicting early failure of quantum cascade lasers during accelerated burn-in testing using machine learning

Device life time is a significant consideration in the cost of ownership of quantum cascade lasers (QCLs). The life time of QCLs beyond an initial burn-in period has been studied previously; however, little attention has been given to predicting premature device failure where the device fails within several hundred hours of operation. Here, we demonstrate how standard electrical and optical device measurements obtained during an accelerated burn-in process can be used in a simple support vector machine to predict premature failure with high confidence. For every QCL that fails, at least one of the measurements is classified as belonging to a device that will fail prematurely—as much as 200 h before the actual failure of the device. Furthermore, for devices that are operational at the end of the burn-in process, the algorithm correctly classifies all the measurements. This work will influence future device analysis and could lead to insights on the physical mechanisms of premature failure in QCLs.

A Study on Parallel Test Approach for the Flash Burn-in Experiment in Laboratory

Abstract With the increasing number of lab burn-in samples, this paper proposes a parallel test approach for the problem that the single-device test board cannot meet the requirements of the JEDEC standard for the large number of samples with high efficiency. The designed FPGA control board independently separates 4 control SCAN signals, different SCAN chips perform read operations in sequence, and complete the operation in parallel. The experimental results show that, compared with the single-device test board, the MT test board can test 80 chips at the same time, which meets the requirements of the JEDEC standard, and reduces the requirement for hardware resources in the burn-in test, and improves test efficiency.

Design, Analysis and Validation of MCP Package for GaAs Monolithic Microwave Integrated Circuits Packaging

This paper describes the design aspects of high reliable packages including package resonance, material selection, and feed-through design to match the die designer specifications. Design, simulation and thin film fabrication of 50Ω microstrip line on a 10 mil Al2O3 substrate suitable for MMIC assembly are also presented. Al2O3 substrate is taken because of lower transitional losses at the seal ring of the package, lower leakage and best suitable for hermiticity. Strip line design, study and the input-output transitions between two ports is analysed and optimized. Evidence of package self resonating mode study carried out theoretically and similar is simulated by using CST microwave studio. Package physical model analysis is carried out on a metal-ceramic package (MCP) which is suitable for embedding an amplifier of 20 dB gain and low power in c-band, 35 dB gain and low noise figure in s-band and 28 dB typical gain in x-band. Packaging effects in each case is analysed and optimised to meet the design requirements. With systematic ideas, the complete package modelling, characterization and MMICs packaging are carried out as per the reliability standards for space application. This package is sealed using the hermetic sealing technique to assure no leakage when subjected to the environmental test conditions like operating temperature test, active burn-in test for 240 h and steady-state life test for 1000 h to check MMIC behaviour under overstress conditions. Packaged module RF performances are noted at pre-subjected and post-subjected temperature conditions. Drifts are calculated at both temperature stages.

Non-parametric estimation of bivariate reliability from incomplete two-dimensional warranty data

A two-dimensional warranty coverage is available for those items for which age and usage jointly fall below the respective warranty limits, thus making the warranty field data incomplete. In this paper, the joint reliability function of age and usage from the observed incomplete two-dimensional warranty data has been estimated in terms of reliability function and density function of age and usage rate respectively by using non-parametric method under the assumption of independence between age and usage rate. Bivariate mean residual life for age and usage has also been determined using the bivariate reliability function. From the reliability engineering perspective, mean residual life provides valuable information for various decision making problems, such as optimizing burn-in test, extending warranty policy, and making maintenance decision. In this paper, the mean residual life has been predicted for formulating extended warranty policy. Pro-rata warranty policy has also been considered here using linear and non-linear pro-rata functions. The utilities of this research work have been demonstrated with the help of a real-life warranty data set.

Performance of liquid crystalline polyester composite burn-in board connectors under cyclic high-temperature condition

The performances of connectors for burn-in tests made of various glass fibre/liquid crystalline polyester composites were analysed using mechanical testing and finite element analyses. Three different composites (E6006L, E6007LHF, and E6808UHF) were evaluated, containing one of two fibre types (chopped or milled) at different contents by weight. Material characterisations of the composites were accomplished by static tensile and fatigue testing under three temperature conditions (23 °C, 160 °C, and 220 °C). The tensile strength, failure strain, and S–N curves of the materials were identified and applied in finite element analyses of the connector structure. The structural integrity of each connector subjected to cyclic high temperature condition was then evaluated using stress and fatigue analyses, and the fatigue life was calculated according to material. Finally, the 40 wt% milled glass fibre/liquid crystalline polyester composite was identified as the most appropriate material for the burn-in test board connector structure.

Burn-in-Testing (BIT) Challenge: to BIT or not to BIT?

Abstract Burn-in testing (BIT) is a costly undertaking. Predictive modeling enables shading useful light on what and how should be tested, if at all. Three analytical (“mathematical”) predictive models recently suggested by the author are addressed in this mini-review: 1) A model based on the analysis of the infant mortality portion (IMP) of the bathtub curve (BTC) suggests that the non-random time derivative of the expected “statistical” failure rate (SFR) at the beginning of the IMP could be viewed as a suitable criterion (“figure of merit”) to answer the basic question of the BIT undertaking: “to BIT or not to BIT?” 2) A model based on the analysis of the random failure rate (RFR) of the mass-produced components that the manufactured product of interest is comprised of suggests that the above derivative is, in effect, the RFR variance of these components. 3) A model based on the use of the kinetic multi-parametric Boltzmann-Arrhenius-Zhurkov (BAZ) constitutive equation is employed to establish the BIT's adequate duration and level, if this kind of failure-oriented-accelerated-testing (FOAT) is found to be necessary. The theoretical findings are illustrated by calculated data. It is concluded that predictive modeling should always precede the actual BIT, that analytical modeling should always complement computer simulations and that future work should address the experimental validation and possible extension of the obtained results and recommendations.