Silicon-on-insulator Research Articles

Passive matrix Schottky barrier 2D photodiode array on graphene/SOI platform

Abstract We fabricated 4 × 4 pixel two-dimensional (2D) photodiode array (PDA) out of monolayer graphene and n-type silicon (n-Si) electrodes on a silicon-on-insulator (SOI) substrate. Our device design is based on passive matrix sensor array architecture consisting of individual graphene and silicon electrodes aligned perpendicular to each other. I-V measurements conducted at room temperature to reveal the electronic characteristics of graphene and Si junction in the device structure. The spectral responsivity, respond speed and the optical crosstalk of each G/Si pixels in the array have been determined by wavelength resolved and time dependent photocurrent spectroscopy measurements. Micro-Raman mapping measurements were conducted to examine the surface coverage of graphene electrode on each pixel. The results of Micro-Raman mapping measurements were correlated with the corresponding photocurrent data acquired under light illumination. We believe that this work constitutes a significant potential in integrating variety of 2D materials and SOI technology into next generation image sensing and multiple pixel light detection applications.

Optimized design of UTB SOI MOSFET and connections for 2.45 G weak energy density harvesting

Optimized design of UTB SOI MOSFET and connections for 2.45 G weak energy density harvesting

Ultrafast pulse propagation time-domain dynamics in dispersive one-dimensional photonic waveguides

Abstract Ultrafast pulses, particularly those with durations under 100 fs, are crucial in achieving unprecedented precision and control in light–matter interactions. However, conventional on-chip photonic platforms are not inherently designed for ultrafast time-domain operations, posing a significant challenge in achieving essential parameters such as high peak power and high temporal resolution. This challenge is particularly pronounced when propagating through integrated waveguides with nonlinear and high-dispersion profiles. In addressing this challenge, we present a design methodology for ultrafast pulse propagation in dispersive integrated waveguides, specifically focused on enhancing the time-domain characteristics of one-dimensional grating waveguides (1DGWs). The proposed methodology aims to determine the optimal structural parameters for achieving maximum peak power, enhanced temporal resolution, and extended pulse storage duration during ultrafast pulse propagation. To validate this approach, we design and fabricate two specialized 1DGWs on a silicon-on-insulator (SOI) platform. A digital finite impulse response (FIR) model, trained with both transmission and phase measurement data, is employed to obtain ultrafast time-domain characteristics, enabling easy extraction of these results. Our approach achieves a 2.8-fold increase in peak power and reduces pulse broadening by 24 %, resulting in a smaller sacrifice in temporal resolution. These results can possibly pave the way for advanced light–matter interactions within dispersive integrated waveguides.

Highly scalable In0.95Ga0.05As based controllable leaky-integrate-fire neuron for high performance spiking neural network and applications

Abstract In this work, we design and simulate a leaky integrate-and-fire (LIF) neuron based on a single Indium Gallium Arsenide (In0.95Ga0.05As) MOSFET. The proposed implementation results in significant improvements in energy, area, and cost reduction. The In0.95Ga0.05As -MOSFET LIF neuron imitates neuron behaviour accurately, with low breakdown voltage, high impact ionization coefficient, and sharp breakdown. Due to the storage of induced holes in the potential well of the In0.95Ga0.05As -MOSFET, impact ionisation is the main mechanism creating the spiking characteristic in this case. It requires only 7.11 pJ/spike of energy, compared to the silicon-based SOI MOSFET, which requires 45 pJ/spike. The LIF neuron exhibits a 0.5 MHz high spiking frequency, which is 5 times higher than real nerves in the human body. Compared to biology, MHz operation provides appealing hardware acceleration. In0.95Ga0.05As -MOSFET LIF neuron firing may be controlled through the application of gate voltage, which can increase the spiking neural networks (SNN) energy efficiency by causing sparse activity. The effects of gate metal work function, Gallium mole fraction, and temperature on spike current variations are also investigated. This neuron circuit has promising potential for large-scale integration in spiking neural network hardware. Reconfigurable threshold logic gates have been investigated for the proposed neuron in order to implement universal digital logic functions, such as NAND and NOR.

Optical beam steering and distance measurement experiments through an optical phased array and a 3D printed lens

We present beam steering experiments based on the wavelength tuning of edge-coupled 1D optical phased arrays (OPAs) on a 3 µm silicon on insulator (SOI) platform. Two versions of 512-channel OPA with different pitch values, namely 2 µm and 3 µm, are designed, fabricated, and characterized. For the 2 µm pitch, the width of the output array is 1 mm, steering sensitivity is measured to be 1°/nm, and the maximum beam steering angle is 45°. For the 3 µm pitch, the output array is 1.5 mm wide, the steering sensitivity is 0.6°/nm, and the maximum beam steering angle is 30°. Since the chip doesn’t offer vertical collimation, both a cylindrical (2D-shaped) lens and a 3D printed (3D-shaped) lens were tested with the OPA chips. The high number of output channels results in a wide width of the output array, therefore enabling frequency-modulated continuous-wave (FMCW) distance measurements up to a few meters. The ability to achieve precise steering angles and distance measurements with up to 5 cm accuracy improves the efficiency of light detection and ranging (LiDAR) systems in various fields, such as autonomous vehicles, robotics, and environmental mapping.

Reconfigurable Free Form Silicon Photonics by Phase Change Waveguides

AbstractThe rapid reprogramming of photonic integrated circuits (PICs) offers transformative potential for photonic technologies. Traditional programmable photonic devices, relying on thermo‐optic or electro‐optic effects, face limitations like large size and high energy consumption. Chalcogenide phase‐change materials (CPCMs) have gained attention for enabling energy‐efficient, non‐volatile optical manipulation on‐chip, crucial for in‐memory optical computing. Sb₂S₃ emerges as a promising alternative to conventional CPCMs, providing low loss and reversibility. This work introduces a CMOS‐compatible reconfigurable waveguide platform using Sb₂S₃ thin film on silicon‐on‐insulator (SOI). Laser direct writing enables the creation of complete channel waveguides in a single step, with the flexibility to erase and rewrite segments for rapid design adjustments. The platform demonstrates stable waveguide erasure using a cost‐effective laser engraver and low‐loss coupling between SOI and the phase‐change material‐on‐silicon (PCMoS) waveguide. By combining an economical fabrication process with a robust device architecture, this integration scheme offers a versatile solution for applications such as optical interconnects, neuromorphic and quantum computing, and microwave photonics.

Atmospheric-level carbon dioxide gas sensing using low-loss mid-IR silicon waveguides.

Interest in carbon dioxide (CO2) sensors is growing rapidly due to the increasing awareness of the link between air quality and health. Indoor, high CO2 levels signal poor ventilation, and outdoor the burning of fossil fuels and its associated pollution. CO2 gas sensors based on integrated optical waveguides are a promising solution due to their excellent gas sensing selectivity, compact size, and potential for mass manufacturing large volumes at low cost. However, previous demonstrations have not shown adequate performance for atmospheric-level sensing on a scalable platform. Here, we report the clearly resolved detection of 500 ppm CO2 gas at 1 s integration time and an extrapolated 1σ detection limit of 73 ppm at 61 s integration time using an integrated suspended silicon waveguide at a wavelength of 4.2 µm. Our waveguide design enables suspended strip waveguides with bottom anchors while maintaining a constant waveguide core cross-sectional geometry. This unique design results in a low propagation loss of 2.20 dB/cm. The waveguides were implemented in a 150 mm silicon on insulator (SOI) platform using standard optical lithography, providing a clear path to low-cost mass manufacturing. The low CO2 detection limit of our proposed waveguide, combined with its compatibility for high-volume production, creates substantial opportunities for waveguide sensing technology in CO2 sensing applications such as fossil fuel combustion monitoring and indoor air quality monitoring for ventilation and air conditioning systems.

Color variations of silicon-on-insulator wafers with silicon device layer thickness.

The perceived colors of silicon-on-insulator (SOI) wafers with etched Si surface layers of thickness 90 nm to 30 nm vary from turquoise to purple to golden. Measured reflectance curves spanning ultraviolet, visible, and near infrared wavelengths have an amplitude modulated oscillatory pattern. Multilayer reflectance calculations indicate the oscillatory pattern results from the 2 µm thick buried SiO2 layer which functions as a nearly lossless reflective Fabry-Perot etalon in the near infrared where SiO2 and Si are transparent. The amplitude modulation of the oscillatory pattern in the visible region where Si is absorbing results from thin-film effects in the Si surface layer. The changing modulation with Si thickness and wavelength results in the observed color variations. It is therefore possible to estimate the Si thickness based on the etched SOI wafer color observed visually. This ability is useful when initially optimizing the etching process to produce a specific thin Si layer, for example when fabricating photodiodes or other photonic devices on SOI wafers. Accurate measurements of the Si thickness and the buried SiO2 thickness can be performed by analyzing the modulated oscillatory reflectance curve using multilayer reflectance calculations.

Temperature compensation study of pressure sensors after leadless packaging

Purpose The purpose of this paper is to reduce the problem of temperature drift causing output errors in such sensors, three hardware compensation schemes are proposed in this paper, and three compensation schemes are designed and implemented. Design/methodology/approach In response to the problem of temperature drift causing output errors in this type of sensor, this paper proposes three hardware compensation schemes and carries out the design and implementation of the three compensation schemes. Finally, the advantages and disadvantages of the three compensation schemes are discussed through the analysis of the experimental results. The three hardware compensation methods are series-parallel resistance network compensation, digital signal processor (DSP) compensation and the joint compensation of resistance network and DSP. Series parallel resistance network compensation is to connect the low-temperature drift resistance and the sensor in series and parallel; DSP compensation is based on the combination of cubic spline interpolation and linear fitting algorithm, which uses DSP to process the data. Joint compensation is a new compensation method composed of the above two compensation methods. Findings The experimental results show that the relative error of the output is reduced to a certain extent after the three compensation methods, and the relative error of the output after the joint compensation is reduced to about 0.2%, which proves that the three compensation methods are feasible. Originality/value This paper presents three novel hardware compensation methods to reduce temperature drift in silicon on insulator (SOI) high-temperature pressure sensors. The joint compensation method, combining resistance network and DSP compensation, is particularly innovative and significantly improves output accuracy, reducing relative error to about 0.2%.

Infrared photoresponse of GeSiSn p-i-n photodiodes based on quantum dots, quantum wells, pseudomorphic and relaxed layers.

Structural and photoelectric properties of p-i-n photodiodes based on GeSiSn/Si multiple quantum dots both on Si and silicon-on-insulator (SOI) substrates were investigated. Elastic strained state of grown films was demonstrated by x-ray diffractometry. Annealing of p-i-n structures before the mesa fabrication can improve the ideality factor of current-voltage characteristics. The lowest dark current density of p-i-n photodiodes based on quantum dots at the reverse bias of 1 V reaches the value of 0.8 mA/cm2. The cutoff wavelength shifts to the long-wavelength region with the Sn content increase. Maximum cutoff wavelength value is found to be 2.6 μm. Moreover, multilayer periodic structures with GeSiSn/Ge quantum wells and GeSiSn relaxed layers on Ge substrates were obtained. Reciprocal space maps were used to study the strained state of GeSiSn layers. The optimal growth parameters were determined to obtain slightly relaxed GeSiSn layers. Designed p-i-n photodiodes based on these structures demonstrated the minimal dark current density of 0.7 mA/cm2 and the cutoff wavelength of about 2μm.

Fabrication and simulation of silicon nanogaps pH sensor as preliminary study for Retinol Binding Protein 4 (RBP4) detection

In this research, a silicon nanogap biosensor has the potential to play a significant role in the field of biosensors for detecting Retinol Binding Protein 4 (RBP4) molecules due to its unique nanostructure morphology, biocompatibility features, and electrical capabilities. Additionally, as preliminary research for RBP4, a silicon nanogap biosensor with unique molecular gate control for pH measurement was developed. Firstly, using conventional lithography followed by the Reactive-ion etching (RIE) technique, a nanofabrication approach was utilized to produce silicon nanogaps from silicon-on-insulator (SOI) wafers. The critical aspects contributing to the process and size reduction procedures were highlighted to achieve nanometer-scale size. The resulting silicon nanogaps, ranging from 100 nm to 200 nm, were fabricated precisely on the device. Secondly, pH level detection was performed using several types of standard aqueous pH buffer solutions (pH 6, pH 7, pH 12) to test the electrical response of the device. The sensitivity of the silicon nanogap pH sensor was 7.66 pS/pH (R² = 0.97), indicating that the device has a wide range of pH detecting capacity. This also includes the silicon nanogap biosensor validated by simulation, with the sensitivity obtained being 3.24 μA/e.cm² (R² = 0.98). The simulation of the sensitivity is based on the interface charge (Qf) that represents the concentration of RBP4. The results reveal that the silicon nanogap biosensor has excellent characteristics for detecting pH levels and RBP4 with outstanding sensitivity performance. In conclusion, this silicon nanogap biosensor can be used as a new electrical RBP4 biosensor for biomedical diagnostic applications in the future.

Polarization-insensitive and compact single-mode filter on a 340 nm silicon-on-insulator platform.

In this paper, we propose and demonstrate an integrated polarization-insensitive single-mode filter (SMF) on a 340 nm silicon-on-insulator (SOI) platform, by introducing two lateral coupling waveguides to couple high-order modes from central single-mode waveguide to lateral waveguides. The experimental results show that the excess loss is <0.29 dB and the extinction ratio is >20 dB with a broad bandwidth of 136 nm for the fabricated SMF with a compact footprint of <13 µm.

First‐Principles Investigation of the Valley Splitting of Si Quantum Slabs

First‐principles calculations based on density functional theory are performed on silicon (Si) quantum slabs to investigate the valley splitting of the lowest sub‐bands at the Γ point in the conduction band. The calculations show that strong strain in the [110] direction of the slab largely enhances the valley splitting, which may be related to the giant valley splitting observed in a device consisting of silicon‐on‐insulator and buried oxide layers. The relation between the valley splitting and the atomic configuration of the slabs is also examined.

Silicon Nitride Spot-Size Converter with Coupling Loss &lt; 1.5 dB for Both Polarizations at 1W Optical Input

Microwave photonics (MWP) applications often require a high optical input power (&gt;100 mW) to achieve an optimal signal-to-noise ratio (SNR). However, conventional silicon spot-size converters (SSCs) are susceptible to high optical power due to the two-photon absorption (TPA) effect. To overcome this, we introduce a silicon nitride (SiN) SSC fabricated on a silicon-on-insulator (SOI) substrate. When coupled to a tapered fiber with a 4.5 μm mode field diameter (MFD), the device exhibits low coupling losses of &lt;0.9 dB for TE modes and &lt;1.4 dB for TM modes at relatively low optical input power. Even at a 1W input power, the additional loss is minimal, at approximately 0.1 dB. The versatility of the SSC is further demonstrated by its ability to efficiently couple to fibers with MFDs of 2.5 μm and 6.5 μm, maintaining coupling losses below 1.5 dB for both polarizations over the entire C-band. This adaptability to different mode diameters makes the SiN SSC a promising candidate for future electro-optic chiplets that integrate heterogeneous materials such as III-V for gain and lithium niobate for modulation with the SiN-on-SOI for all other functions using advanced packaging techniques.

Lithium niobate electro-optical modulator based on ion-cut wafer scale heterogeneous bonding on patterned SOI wafers

This paper presents the design, fabrication, and characterization of a high-performance heterogeneous silicon on insulator (SOI)/thin film lithium niobate (TFLN) electro-optical modulator based on wafer-scale direct bonding followed by ion-cut technology. The SOI wafer has been processed by an 8 inch standard fabrication line and cut into 6 inch for direct bonding with TFLN. The hybrid SOI/LN electro-optical modulator operated at the wavelength of 1.55 μm is composed of couplers on the Si layer and a Mach–Zehnder interferometer (MZI) structure on the LN layer. The fabricated device exhibits a stable value of the product of half-wave voltage and length (V π L) of around 2.9 V·cm. It shows a good low-frequency electro-optic response flatness and supports 96 Gbit/s data transmission for the NRZ format and 192 Gbit/s data transmission for the PAM-4 format.

Low cross talk, low P π silicon optical switch based on highly balanced couplers and folded phase shifters

The cross talk and power consumption of the 2 × 2 optical switch is a key metric in the design of large-scale photonic integrated circuits (PICs). We build a theoretical model of a 2 × 2 Mach–Zehnder interferometer (MZI) optical switch, taking into account both imbalances in the arm loss and the coupler splitting ratio. The splitting ratio imbalance requirement for a given switch cross talk is summarized, which provides a guideline for the switch design. A 2 × 2 multimode interference (MMI) coupler design with low excess loss (&lt;0.14 dB) and low imbalance (&lt;0.13 dB) over the C-band is given. Its robustness to width variations up to ±40 nm is demonstrated. The 2 × 2 MZI switches with such an MMI are fabricated on a silicon-on-insulator (SOI) substrate using both electron beam (EB) and deep ultraviolet (DUV) lithography. The EB and DUV MMI switches exhibit cross talk of &lt;−35 dB and &lt;−30 dB over 40 nm, respectively. Folded configurations are used for both the silicon waveguides and the metal heaters to increase the power efficiency, resulting in a Pπ of ∼8 mW.

Mitigation of 1-Row Hammer in BCAT Structures Through Buried Oxide Integration and Investigation of Inter-Cell Disturbances

Dynamic random-access memory (DRAM) is crucial for high-performance computing due to its speed and storage capacity. As the demand for high-capacity memory increases, DRAM has adopted a scaled-down approach for the next generation. However, the reduced distance between cells leads to electrical interference, known as the 1-row Hammer effect, which degrades DRAM performance and poses security risks. Therefore, the 1-row Hammer effect is a critical issue in current DRAM technology. In this study, we investigate the principles and impact of the 1-row Hammer phenomenon on DRAM. The 1-row Hammer effect can cause two types of failures: D0 and D1. We focus on D0 failures, which occur when stored data transition from 0 to 1 due to repeated accesses. This phenomenon involves the capture and diffusion of electrons, influenced by interfacial traps and device structures. To investigate the D0 failure, we simulated the 1-row Hammer effect using a mixed-mode approach to examine its effects on interfacial traps and device structure changes. This study aims to improve our understanding of row Hammer and suggests a mitigation strategy using buried oxide. The proposed structure mitigates the D0 failure by approximately 25%, effectively improving the security and reliability of DRAM.

Polarization-insensitive thermo-optic Mach-Zehnder switches on silicon.

Polarization-insensitive photonic switches are crucial for the case with random polarization states encountered in optical systems. In this paper, we propose and demonstrate a polarization-insensitive 2 × 2 thermo-optic Mach-Zehnder switch (PIMZS) on a 340-nm silicon-on-insulator (SOI) platform by incorporating low-loss polarization-insensitive multimode interference (PIMMI) couplers whose core width is varied optimally. The fabricated 2 × 2 PIMZS exhibits a low excess loss of 0.15-0.79 dB and a high extinction ratio of >24 dB for both polarizations, and low polarization-dependent loss (PDL) of <0.47 dB is achieved across the C-band.

Tailoring the performance of the multidimensional electrostatically formed nanowire gas sensor

Abstract Multi-gate field effect transistors (FETs) based on silicon-on-insulator (SOI) have been popular for several decades due to their improved electrostatic control of the channel current between the source and the drain. Chemical sensors based on such multi-gate FET platform can leverage this improved electrostatic control to detect gases at very low concentration with ultrahigh sensitivity. Electrostatically formed nanowire (EFN) is a multiple-gate FET device which has proven to be an excellent platform for detecting volatile organic compounds and gases. In case of such multi-gate FET sensors, it is imperative to rigorously understand the influence of each gate in controlling the sensing performances. Using palladium nanoparticles decorated EFN (Pd-EFN) as an example, the current work presents a detailed methodology for determining the operating parameters for maximal sensing performances of the Pd-EFN sensor towards hydrogen sensing. We observed that a single operating point does not yield best results with regard to sensor response, dynamic range, and power efficiency. By optimising the operating points (by varying the different gate biases), a sensor response of 107 % was reached even at low concentrations of hydrogen (500 ppm) which is significantly lower than the lower explosive limit of 4% and a tunable dynamic range over three decades (4-8000 ppm) was obtained. Also, the sensor response was not compromised at low driving voltages (100 mV) thus contributing to low power consumption of the sensor. Such a correlation between the working point of the transistor and the various sensor performance metrics (maximum sensor response, dynamic range etc ) has not been studied before to the best of our knowledge and this study can be extended to EFN for other gases and any other multi-gate FET sensors (not limited to Si based sensors).This study can pave the way for effective design of future multi-gate transistors for gas sensing.

Silicon-based light-emitting transistor with Ge(Si) nanoislands embedded in a photonic crystal: Control of the spectrum and spatial distribution of the emission

Light-emitting transistors (LETs) represent the next step in the development of light-emitting diodes (LEDs), offering additional control over emission. In this work, the transport properties and spatial distribution of electroluminescence (EL) in the spectral range of 1.2–1.7 μm were studied for lateral p+-i-n+ LEDs based on silicon-on-insulator structures with self-assembled Ge(Si) islands embedded in photonic crystals. It is shown that due to the low mobility of holes and their effective trapping in the islands, the maximum EL yield is observed at the i/p+ junction of the LED. It is demonstrated that the sign and magnitude of the bias voltage applied to the substrate (to the gate) have a significant influence on the transport and emission properties of the LEDs with Ge(Si) islands, turning them into LETs. In particular, applying a negative gate voltage shifts the position of the maximum emission region from the i/p+ to the i/n+ junction of the LET, which is related to the formation of a hole conductivity channel near the buried oxide layer. The embedding of a specially designed photonic crystal in the i-region of the LET makes it possible to manage the spectral properties of the near-IR emission by changing the sign of the gate voltage. The results obtained may be useful for the future development of optoelectronic devices.