Buried Gate Static Induction Transistors Research Articles

3 kV Normally-Off 4H-SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

3 kV normally-off SiC-buried gate static induction transistors (SiC-BGSITs) were fabricated by using an innovative fabrication process that was used by us previously to fabricate 0.7–1.2 kV SiC-BGSITs. The fabricated device shows the lowest specific on-resistance of 9.16 mΩ·cm2, compared to all other devices of the same class. The threshold voltage of this device was 1.4 V at room temperature and was maintained at values more than 1 V with normally-off characteristics at 200 °C. The device can block drain voltage of 3 kV with a leakage current density of 6.9 mA/cm2.

Experimental Study of Short-Circuit Capability of Normally-off SiC-BGSITs

We investigated the short-circuit capabilities of 1.2 kV normally-off SiC buried gate static induction transistors (SiC-BGSITs). The maximum short-circuit energy was found to be 35.6 J/cm2, which is twice that of normally-on SiC-BGSITs and 3.3–5.6 times higher than that of the Si-IGBTs. The maximum short-circuit time was 590 μs. It is concluded that these high short-circuit capabilities result from saturation characteristics of the normally-off SiC-BGSITs.

980 V, 33A Normally-Off 4H-SiC Buried Gate Static Induction Transistors

In this work, we succeeded in developing high performance normally-off SiC buried gate static induction transistors (SiC-BGSITs). To achieve the normally-off characteristics, design parameters around the channel region were optimized and process conditions were improved to realize these parameters. The off-state characteristic of the SiC-BGSIT showed an avalanche breakdown voltage of VBR=980 V at a gate voltage of VG=0 V. Furthermore, the leakage current at VD=950 V is lower than 0.5 μA. These results indicate that the BGSIT has a good normally-off characteristic. At VG=2.5 V, an on-resistance of 28.0 mΩ corresponding to the specific on-resistance of 1.89 mΩ•cm2 was obtained and the current rating was calculated as 33 A at a power density of 200 W/cm2 in the on-state characteristic.

Crystalline Quality of Channel Regions in SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

We investigated the crystalline quality and electrical properties of the channel regions in 4H-SiC buried gate static induction transistors (SiC-BGSITs). To accurately determine the characteristics of the channel regions, we performed transmission electron microscopy and scanning spreading resistance microscopy. It was found that the channel regions have high crystalline quality and no significant fluctuations in doping concentration.

Radiation Hardness Evaluation of SiC-BGSIT

In this study, we evaluated the radiation hardness of SiC Buried Gate Static Induction Transistors (SiC-BGSITs) and Si-based switching devices up to the absorbed dose of 10 MGy(SiO2). The on-voltage Von of Si-IGBT degraded excessively at the early stage of the irradiation (>~0.1 MGy(SiO2)) due to the bulk damage produced by Compton electrons like the gain degradation in Si bipolar transistors. The threshold voltage Vth of Si-MOSFET was very sensitive against the radiation due to the competing mechanism between the generation of the hole traps in the gate SiO2 and the SiO2/Si interface states. Moreover, the breakdown voltage VBR and leak current Ileak of MOSFET degraded significantly against the absorbed dose. While, the electrical properties of SiC-BGSIT was very stable even after the irradiation of 10 MGy(SiO2).

Short-Circuit Capability of SiC Buried-Gate Static Induction Transistors: Basic Mechanism and Impacts of Channel Width on Short-Circuit Performance

Fundamental short-circuit operations of silicon carbide static induction transistors with buried-gate structures (BGSITs) were experimentally clarified, with subsequent device simulations. The impacts of channel width and source length on short-circuit capabilities were investigated. In particular, a design concept of the channel width was proposed to improve the short-circuit energy without a serious increase in on-resistance. The maximum short-circuit capability of the fabricated BGSITs was 18 J/cm2 at room temperature, which shows excellent performance compared with that of conventional Si insulated-gate bipolar transistors.

Evaluation of Refilled Channel Regions in 4H-SiC Buried Gate Static Induction Transistors

We evaluated the crystalline quality of the channel region in silicon carbide buried gate static induction transistors (SiC-BGSITs) by transmission electron microscopy (TEM) and scanning spreading resistance microscopy (SSRM). TEM observations revealed that no crystalline defects were generated in the channel region of SiC-BGSITs during epitaxial regrowth in trenches. The SSRM result indicated that the refilled channel region had a spreading resistance distribution of about ten times due to a high noise resulting from contact resistance. This noise was so high that we could not detect carrier density distributions from SSRM signals. However, on the basis of the leakage current and blocking characteristics of the SiC-BGSITs, we confirmed that there was no serious carrier density distribution that affected the device operation in the channel region.

Silicon Carbide Static Induction Transistor with Implanted Buried Gate

Buried gate static induction transistors (BGSITs) were fabricated on commercial 4H-SiC wafer with 20 m thick n-type epilayer having a net donor density of 0.71015 cm-3. Buried gate regions were formed by the selective implantation of high energy (up to 2 MeV) aluminium performed at 600 °C. Nitrogen was implanted at temperature of 400 °C to form a heavily doped blanket source region. Post-implantation annealing was carried out at the atmospheric pressure in argon using a graphite capping layer. Fabricated normally-on devices with source contact diameter of 0.2 mm were tested at temperatures up to 500 °C and current densities up to 270 A/cm2. The specific on-resistance of a completely open 4H-SiC BGSIT was 34 mcm2 and showed a thermally activated behaviour at temperatures up to 500 °C.

Short-Circuit Operation of SiC Buried Gate Static Induction Transistors (SiC BGSITs)

Short-circuit capabilities of silicon carbide static induction transistors with the buried gate structures (BGSITs) have been measured for the first time, and have been followed by 2D device simulations. The short-circuit operation of the normally-on type BGSITs is characterized by an abrupt decrease in the output current through a high peak in the initial phase of the short-circuit period, which is distinguished from that of the conventional IGBTs and power MOSFETs. This operation is caused by the inherent operation of the SITs including the non-saturating current-voltage characteristics with the unipolar operation. Decreasing the channel width adequately is a useful method to increase the short-circuit capability.

Three Dimensional Analysis of Turnoff Operation of SiC Buried Gate Static Induction Transistors (BG-SITs)

The turnoff mechanism of SiC buried gate static induction transistors (SiC-BGSITs) were analyzed by three dimensional device simulation. A current crowding occurs in the portion near the channel center away from the gate contact during the initial phase of the turnoff operation, which is resulted from a non-uniform potential distribution through the gate finger with the displacement current flowing there. This increases the turnoff delay time. The impact of source length on the turnoff performance was made clear.

1270V, 1.21mΩ·cm<sup>2</sup> SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.