Buried-channel p-MOSFETs Research Articles

Reduction of Low Frequency Noise of Buried Channel PMOSFETs With Retrograde Counter Doping Profiles

Reduction of Low Frequency Noise of Buried Channel PMOSFETs With Retrograde Counter Doping Profiles

Improved noise performance from the next-generation buried-channel p-MOSFET SiSeROs

The Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detector output stage for charge-coupled device (CCD) image sensors. Developed at MIT Lincoln Laboratory, this technology uses a p-MOSFET transistor with a depleted internal gate beneath the transistor channel. The transistor source-drain current is modulated by the transfer of charge into the internal gate. At Stanford, we have developed a readout module based on the drain current of the on-chip transistor to characterize the device. In our earlier work, we characterized a number of first prototype SiSeROs with the MOSFET transistor channels at the surface layer. An equivalent noise charge (ENC) of around 15 electrons root mean square (RMS) was obtained. In this work, we examine the first buried-channel SiSeRO. We have achieved substantially improved noise performance of around 4.5 electrons root mean square (RMS) and a full width half maximum (FWHM) energy resolution of 132 eV at 5.9 keV, for a readout speed of 625 kpixel/s. We also discuss how digital filtering techniques can be used to further improve the SiSeRO noise performance. Additional measurements and device simulations will be essential to further mature the SiSeRO technology. This new device class presents an exciting new technology for the next-generation astronomical X-ray telescopes requiring fast, low-noise, radiation-hard megapixel imagers with moderate spectroscopic resolution.

Effect of substrate doping on threshold voltages of buried channel pMOSFET based on strained-SiGe technology

The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied. By physically deriving the models of the threshold voltages, it is found that the layer which inversely occurs first is substrate doping dependent, giving explanation for the variation of plateau observed in the C-V characteristics of this device, as the doping concentration increases. The threshold voltages obtained from the proposed model are −1.2805 V for buried channel and −2.9358 V for surface channel at a lightly doping case, and −3.41 V for surface channel at a heavily doping case, which agrees well with the experimental results. Also, the variations of the threshold voltages with several device parameters are discussed, which provides valuable reference to the designers of strained-SiGe devices.

Electron Substrate and Gate Current Modeling for Single-Drain Buried-Channel p-Type Metal–Oxide–Semiconductor Field-Effect Transistors Including Tunneling Mechanisms

A model of nonlocal electron substrate and gate currents is presented for single-drain (SD) buried-channel (BC) p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs). A nonlocal impact ionization coefficient with characteristic length dependence both in the exponential term and the pre-exponential factor is used in the electron substrate current model. The gate current model is developed by originating a modified lucky electron concept that includes quantum-mechanical tunneling effects in parallel. The channel electric field is first calculated by using an analytical pseudo-two-dimensional MOSFET model, and the spatial distribution of electron temperature along the channel is then derived using a simplified energy balance equation. Having calculated the nonlocal impact ionization coefficient and electron temperature, and modified the lucky electron concept, the nonlocal electron substrate and gate currents can be derived. This model is a time-saving computer-aided-design (CAD) model and is physics transparent for SD BC pMOSFETs.

Compact Hot-Electron Induced Oxide Trapping Charge and Post-Stress Drain Current Modeling for Buried-Channel p-Type Metal–Oxide–Semiconductor Field-Effect-Transistors

In this paper, we present a complete and physics-based drain current model for hot-carrier damaged buried-channel (BC) p-type metal–oxide–semiconductor field-effect-transistors (pMOSFETs) operated in the forward and reverse-biased modes. Experimentally it was found that the post-stress drain current of BC pMOSFETs increases, this is caused by hot-carrier-induced electron trapping in the oxide. Considering the subthreshold operation, we present an complete electron gate current model and calculate the spatial distribution of oxide-trapping-charges by using an oxide trapping mechanism, and then we can model the hot-carrier damaged drain current by substituting the spatial distribution of oxide-trapping-charges into the damaged BC MOSFET drain current model. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias and stress-time-dependent resistance. The degraded BC MOSFET drain current model is applicable for circuit simulation and its accuracy has been verified by experimental data.

Analytical model of drain current of Si/SiGe heterostructure p-channel MOSFETs for circuit simulation

An analytical model of drain current of Si/SiGe heterostructure p-channel MOSFETs is presented. A simple polynomial approximation is used to model the sheet carrier concentration (p/sub s//sup H/) in the two-dimensional hole gas at the Si/SiGe interface. The interdependence of p/sub s//sup H/ and the hole concentration at the Si/SiO/sub 2/ interface (p/sub s//sup S/) is taken into account in the model, which considers current flow at both the Si/SiGe and the Si/SiO/sub 2/ interfaces. This model is applicable to compressively strained SiGe buried-channel heterostructure PMOSFETs as well as tensile-strained surface-channel PMOSFETs. The model has been implemented in SABER, a circuit simulator. The results from the model show an excellent agreement with the experimental data.

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.

Effect of plasma process-induced damage on bias temperature instability of MOSFETs

For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage on bias temperature instability (BTI) was investigated. The gate oxide thickness, t ox, of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage V th and of linear drain current I dlin were measured after applying a BTI stress at a temperature of 125 °C. The measured shifts of V th and I dlin indicate that BTI on ultra-thin gate CMOS devices appears only in the form of SiO 2/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET.

Halo implant in pseudomorphic SiGe channel p-MOSFET devices to reduce short channel effect

Halo ion implantation was adopted to reduce the short channel effect (SCE) of a buried channel p-MOSFET device on pseudomorphic Si0.70Ge0.30 layers. The strained pseudomorphic Si0.70Ge0.30 layer of 10 nm thickness, with a Si cap layer on top, was grown using molecular beam epitaxy. The results show an overall reduction in threshold voltage (Vth) roll-off in both Si and pseudomorphic SiGe devices. Halo implantation of As+, 120 keV and dose 2 × 1013 cm−2, was successfully used to reduce roll-off for the 2 nm Si cap SiGe device by 0.3 V. However, it was found that halo implantation causes the reverse short channel effect (RSCE) on the devices, which can result in Vth roll-up with reducing channel length. The effect of the RSCE becomes greater with increasing Si cap thicknesses of the SiGe devices. Also, non-halo implanted devices were found to demonstrate the RSCE. This is due to excess interstitials from the source/drain implant and their subsequent diffusion, which causes virtual halo dopant to form in non-halo implanted devices.

1/f noise in Si and si/sub 0.7/Ge/sub 0.3/ pMOSFETs

Strained layer Si/sub 0.7/Ge/sub 0.3/ pMOSFETs were fabricated and shown to exhibit enhanced hole mobility, up to 35% higher for a SiGe device with 3-nm-thick Si-cap, and lower 1/f noise compared to Si surface channel pMOSFETs. The 1/f noise in the investigated devices was dominated by mobility fluctuation noise and found to be lower in the SiGe devices. The source of the mobility fluctuations was determined by investigating the electric field dependence of the 1/f noise. It was found that the SiO/sub 2//Si interface roughness scattering plays an important role for the mobility fluctuation noise, although not dominating the effective mobility. The physical separation of the carriers from the SiO/sub 2//Si interface in the buried SiGe channel pMOSFETs resulted in lower SiO/sub 2//Si interface roughness scattering, which explains the reduction of 1/f noise in these devices. The 1/f noise mechanism was experimentally verified by studying 1/f noise in SiGe devices with various thicknesses of the Si-cap. A too large Si-cap thickness led to a deteriorated carrier confinement in the SiGe channel resulting in that considerable 1/f noise was generated in the parasitic current in the Si-cap. In our experiments, the SiGe devices with a Si-cap thickness in the middle of the interval 3-7 nm exhibited the lowest 1/f noise.

An Analytical Model for a Gate-Induced-Drain-Leakage Current in a Buried-Channel PMOSFET

An Analytical Model for a Gate-Induced-Drain-Leakage Current in a Buried-Channel PMOSFET

Simultaneous optimization of short-channel effects and junction capacitance in pMOSFET using large-angle-tilt-implantation of nitrogen (LATIN)

A widely used halo implant process of counter doping has a tradeoff between the short channel effects and the parasitic junction capacitance. In this letter, we propose a novel drain engineering concept, large-angle-tilt-implantation of nitrogen (LATIN) to improve the short-channel effects without the increase of the junction capacitance in the buried-channel pMOSFET using sub-0.25-/spl mu/m CMOS technology. We compare the electrical characteristics of devices fabricated using LATIN, a conventional arsenic halo implant process (As HALO), and BF/sub 2//sup +/ source/drain (S/D) implantation only. The LATIN improves the short-channel effects when compared to the case of BF/sub 2//sup +/ S/D implant only. In addition, the LATIN reduces junction capacitance by 18% when compared to As HALO. As a consequence, the LATIN is shown to be a drain engineering concept to simultaneously optimize the short-channel effects and junction capacitance. Calibrated two-dimensional simulations confirm the improvement with LATIN.

DRAM reliability

Dynamic random access memory (DRAM) reliability is investigated for future DRAMs where small geometrical devices are used together with new materials and novel process technologies. Among the several items of DRAM reliability, the most important aspect to consider for DRAM reliability is infant mortality which is caused by process-induced defects including random defects. Since the process-induced defects are strongly dependent on process technology, it is inevitable to minimize process-induced defects by developing new process technology. However, whenever new process technology is introduced, new screening techniques or methods are necessary for suppressing infant mortality. The degradation of pMOSFET due to buried-channel pMOSFET during burn-in stress and soft error rate due to α-particle and cosmic ray irradiation become concerns as device dimension shrinks. However, it cannot be limitations of DRAM reliability because pMOSFET degradation due to hot electron induced puchthrough can be suppressed by new layout of pMOSFET, and the soft error events can be overcome by soft error resistant device structure and proper material choices. From these considerations, it can be expected that the advances of DRAM technology generation not only improve the device performance but also enhance the reliability.

Thorough characterization of deep-submicron surface and buried channel pMOSFETs

In this paper, the short channel effects in buried and surface channel pMOSFETs are studied. The effective channel length, threshold voltage, source–drain series resistance, carrier mobility in various temperature ranges and the drain-induced-barrier-lowering effect are investigated. Hot carrier degradation is performed in order to extrapolate the device lifetimes and the maximum drain bias that can be applied. Low frequency noise measurements are also carried out in order to evaluate the impact of the gate doping type on the device noise performance.

Channel engineering using RTA prior to the gate oxidation for high density DRAM with single gate CMOS technology

A non-uniform lateral boron profile along the channel width is observed in a buried-channel p-MOSFET and a memory cell transistor when BF 2 implantation is applied at the dose of ∼10 13 cm −2 to form a channel. SIMS profile analysis and two-dimensional simulation results show that this abnormal profile is formed by transient enhanced diffusion (TED) due to BF 2 implantation damage during gate oxidation process. It is found that RTA process just prior to the gate oxidation is useful to eliminate the TED of boron so that inverse narrow width effect, short channel effect and threshold voltage fluctuation are remarkably improved in a buried-channel p-MOSFET. In addition, the RTA process can also reduce BF 2 implantation dose without decreasing threshold voltage by the suppression of boron diffusion in a cell transistor. Therefore, the retention time of DRAM can be enhanced by reducing space charge region field in a cell transistor due to lower boron concentration compared with a conventional device.

High hole mobilities in fully-strained Si/sub 1-x/Ge/sub x/ layers (0.3>x>0.4) and their significance for SiGe pMOSFET performance

Materials studies, hole transport measurements, and process and device simulations have been employed to determine the optimum epitaxial architecture of a fully-pseudomorphic Si/SiGe pMOSFET heterostructure that is intended for application in a near-standard CMOS process. Numerical simulations have shown that SiGe inter-diffusion severely limits the Ge content that can be achieved in a practical process flow. The SiGe hole wave-functions have been calculated and it is shown that hole confinement effects become very significant for SiGe layers less than 5 nm thick. Furthermore, estimates of the barrier penetration by the hole wave-function indicate that the beneficial effects of the buried-channel structure upon the hole mobility would be significantly reduced for Si cap thickness less than 2 nm. Buried-channel SiGe pMOSFETs are known to suffer from parallel conduction in the Si capping layer and calculations of the charge distribution indicate that high Ge contents (>30%) and thin Si cap thickness (<3 nm) are required in order to confine all of the inversion charge to the SiGe layer. The hole drift mobility has been measured at room temperature for fully-strained Si/sub 1-x/Ge/sub x/ layers with a range of alloy contents (0.3<x<0.4), and with hole densities between 3/spl times/10/sup 11/ cm/sup -2/ and 4/spl times/10/sup 12/ cm/sup -2/. The measured room temperature mobilities are consistently higher than the equivalent Si inversion layer mobilities and these results have been incorporated into two-dimensional (2-D) device simulations in order to understand their significance for SiGe pMOS device performance. It is found that improvements in current drive can be obtained, but only for the most aggressive vertical architectures. For Si cap thickness greater than 1.5 nm, parallel conduction in the cap layer counteracts much of the advantage of the high mobility channel and, even for thin Si caps, velocity saturation effects at high lateral electric fields significantly limit the current drive of a SiGe pMOSFET to values close to that of the conventional Si device. The diminished gate control, due to the inclusion of the cap layer, and the smaller SiGe bandgap also lead to a significant deterioration of the subthreshold characteristics.

Simulation and optimization of strained Si 1−xGe x buried channel p-MOSFETs

Deep submicron (0.35 μm) strained Si 1− x Ge x buried channel p-MOSFETs with a Ge concentration up to 50% were simulated using the MEDICI device simulator. A buried channel structure offers several benefits over a surface channel structure without a Si cap. Simulation results show that the maximum drain current increases monotonically with the Ge mole fraction. The drive current enhancement is more than 300% for Si 0.5 Ge 0.5 over Si. Subthreshold characteristics were analyzed for different Ge mole fractions in this study. The effects of Si cap layer thickness and Si 1− x Ge x channel thickness on drive current and gate voltage operating window were analyzed. The simulation results show that the drive current is the highest when the Si 1− x Ge x layer thickness is between 100 and 300 Å and that Si 1− x Ge x layer thickness can be as low as 50 Å with less than 10% penalty in the drive current, for structures with a 50 Å Si cap layer.

Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation

A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand anisotype junctions in a buried channel structure, we have incorporated charge sharing effect in the quasi-2-D Poisson model. The proposed model correctly predicts the effects of drain bias (V/sub DS/), counter doping layer thickness (x/sub CD/), counter doping concentration (N/sub CD/), substrate doping concentration (N/sub sub/) and source/drain junction depth (x/sub j/), and the new model performs satisfactorily in the sub-0.1 /spl mu/m regime. By using the proposed model on the threshold voltage reduction and subthreshold swing, we have obtained the process windows of the counter doping thickness and the substrate concentration. These process windows are very useful for predicting the scaling limit of the buried channel pMOSFET with known process conditions or systematic design of the buried channel pMOSFET.

A high performance 0.15 μm buried channel pMOSFET with extremely shallow counter doped channel region using solid phase diffusion

A new process for a counter-doped region suitable for a 0.15 μm (gate length) buried channel (BC) pMOSFET is presented. At present serious short-channel effects of BC p-MOSFETs are recognized broadly as prohibitive for application at 0.1 μm. In order to realize 0.15 μm BC pMOSFETs, we propose a new process step, making use of a boron solid phase diffused channel (SPDC) from a Boron-doped silicate glass (BSG) to form an extremely shallow counter-doped region, which enables suppression of short-channel effects. Devices fabricated in this way exhibit good short-channel behavior at 0.15 μm gate length and, additionally, provide an excellent current driving-ability. Threshold voltage control is easy by optimizing the diffusion condition. We propose SPDC as a suitable process applicable to 0.2–0.1 μm BC p-MOSFET.

Single-gate 0.15 and 0.12 μm CMOS with Co salicide technology

A high-speed 0.15 μm single-gate Co salicide CMOS technology has been demonstrated, which suppresses short channel effects in 0.15 μm buried channel pMOSFETs by optimizing the fabrication conditions of their extension region. An unloaded CMOS inverter ring-oscillator delay of 19.8 ps has been obtained. At 0.12 μm gate length, 11.4 ps gate delay was observed.