Bump Joints Research Articles

Bonding Property of Flip-Chip Chip-Scale Package with Vacuum Reflow and Thermal Compression Bonding Processes

The package-on-package technology has been developed to facilitate high-density integration of semiconductor packaging. As the solder bump pitch is decreased, the void content in solder bump joints increases, thereby decreasing its reliability. Consequently, vacuum reflow (VR) is used to increase void fluidity and decrease void content in micro bump joints. Generally, silicon chips in application processor modules are bonded using thermal compression (TC) bonding, followed by the attachment of passive components through hot air reflow soldering. However, the simultaneous bonding of Si chips and passive components using VR can improve productivity.In this study, we performed TC and VR bonding without additional solder pastes, between an Si chip with a Cu pillar/Sn-2.5Ag bump and a bismaleimide triazine substrate plated with electroless-nickel electroless-palladium immersion-gold. It was observed that the void content at the Si chip solder joints yielded by VR (10.8%) was similar to that yielded by TC (11.2%). Furthermore, the Si chip solder joint of the VR sample was thicker than that of the TC sample. This process also resulted in the formation of the intermetallic compounds Cu<sub>6</sub>Sn<sub>5</sub>, (Cu,Ni)<sub>6</sub>Sn<sub>5</sub>, Ag<sub>3</sub>Sn, and Ni<sub>3</sub>P, at the Si chip solder joints. The results of this study suggest that co-bonding of active and passive components is possible through VR soldering for semiconductor packaging.

Numerical Analysis of the Welding Behaviors in Micro-Copper Bumps

In this study, three-dimensional simulations of the ultrasonic vibration bonding process of micro-copper blocks were conducted using the finite element method. We analyzed the effects of ultrasonic vibration frequency on the stress field, strain field, and temperature field at the copper bump joint surface. The results showed that the bonding process is successfully simulated at room temperature. The stress curve of the bonding process could be divided into three stages: stress rising stage, stress falling stage, and stress stabilization stage. Moreover, it was found that the end of the curve exhibited characteristics of a solid solution phase at higher frequencies. It is hypothesized that the high-density dislocations formed at this stage may result in conveyance channels that facilitate the atomic diffusion at the contact surface. The simulation results indicated that copper micro-bump bonding occurs at an ultrasonic frequency of 50 kHz or higher.

Growth Behavior of Intermetallic Compounds in Various Solder Joints Induced by Electromigration

With the development of the fine pitch technology, the size of the solder bumps contacting the chip and the substrate has decreased, thereby significantly increasing the current density. As a result, intermetallic compounds (IMCs) are formed in solder bumps, and the formation/growth of Kirkendall voids is the main reason for failure, which is accelerated by electromigration. Therefore, various studies have been conducted to restrain the growth of IMCs and Kirkendall voids. This study summarizes the issues that should be considered when investigating the effects of electromigration on solder joints. The prediction and observation of the growth behavior of the IMCs is summarized for various solder bump joints. In addition, we provide an effective method for assisting the fine pitch technology. Key words: Electromigration, Solder bump joints, Intermetallic compounds, Kirkendall voids, Modeling

Research on Articulated Connector Load Identification Based on Dynamics

At present, articulated vehicles are developing rapidly in China and articulated connectors are important parts of articulated vehicles. In March 2016, CRRC Qiqihar Rolling Stock co. LTD designed the GJ1 articulated connector. Due to the complexity of the articulated connector structure and stress distribution, it is necessary to study its loads in the application process. In this paper, the load identification of an articulated connector was mainly studied based on dynamic analysis. The dynamic model of the two coupling articulated vehicle was established. The relative motion relation of bump joints and the load conditions under some working conditions were analyzed. Finally, the finite element model was established and the static strength of the articulated connector was analyzed by means of the definition contact between the articulated connector parts. The results showed that the relative lateral displacement and relative side roll rotation angle of the concave and bump joints of the articulated connector were maximum in each working condition. More attention should be paid to the actual operation. The static strength of the main stressed parts of an articulated connector meet the design requirements. Since the material used for traction pin was not determined, high-strength tool steels T10 and T10A were recommended.

Cool Interconnect: A 1024-bit Wide Bus for Chip-to-Chip Communications in 3-D Integrated Circuits

In this paper, we present “Cool Interconnect,” a 1024-bit wide bus that we have developed to provide a standardized method of interconnecting chips in 3-D integrated circuits (3DICs). This wide bus chip-to-chip interconnect can be used to realize low-power high-performance multicore systems to meet the increasing demand for advanced electronics to enable autonomous vehicles and Internet of Things devices. The bus has been implemented using a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40\times 40$ </tex-math></inline-formula> fine-pitch array of through-silicon vias and bump joints. In addition, we have developed a testing methodology based on the boundary scan method to confirm the electrical performance of wide bus chip-to-chip interconnect in 3DICs. Cool Interconnect test chips were designed, fabricated, and flip-chip stacked. Joint Test Action Group (JTAG) and electrical connection tests were used to confirm the successful operation of the test chips, including the chip-to-chip interconnect.

The Effect of the Thermal Mechanical Properties of Nonconductive Films on the Thermal Cycle Reliability of 40-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m Fine Pitch Cu-Pillar/Ni/SnAg Microbump Flip-Chip Assembly

Nonconductive films (NCFs) have been introduced for 3-D through-silicon via chip stacking interconnection using reliable fine pitch Cu-pillar/Ni/SnAg microbumps. In this paper, four NCF materials with various elastic modulus and coefficient of thermal expansion (CTE) values were used to investigate the effect of the thermomechanical properties of the NCFs on the thermal cycle reliability of fine pitch Cu-pillar/Ni/SnAg/Cu-pad interconnections. The NCFs’ materials properties were adjusted by changing the ratio of epoxy resins and the curing accelerators. Compared with the borate curing accelerator, the use of the imidazole curing accelerator resulted in better thermomechanical properties on NCFs. And, NCFs containing higher ratio of solid epoxy resins showed higher elastic modulus and higher Tg values when using imidazole curing accelerator. After thermocompression bonding using four different types of NCFs, a thermal cycle reliability test (−40 °C–125 °C) was performed to investigate the effects of the NCFs’ thermomechanical properties on the reliability of Cu-pillar/Ni/SnAg/Cu-pad joints. Due to the CTE mismatch of chips and printed circuit board (PCB) substrates, the SnAg solder joint interconnections were damaged during the thermal cycling. Compared with the four types of NCFs, NCFs with higher elastic modulus at 30 °C showed better thermal cycle reliability. And among the NCFs with similar CTE values, those with higher Tg and higher elastic modulus at 30 °C value showed better thermal cycle reliability. In summary, the NCFs with lower CTE and higher elastic modulus at 30 °C were suitable for highly thermal cycle reliable Cu-pillar/Ni/SnAg/Cu-pad bump joints.

Carbon-nanotube bundle-base bump joint structure for advanced 3D semiconductor devices

Carbon-nanotube bundle-base bump joint structure for advanced 3D semiconductor devices

Enhancement of Cu pillar bumps by electroless Ni plating

Cu pillar bumps were mechanically enhanced using electroless Ni plating for fine-pitch electronic packaging applications. The interfacial reaction and mechanical properties of the Ni-plated Cu pillar bump joints were evaluated. After reflowing, the plated Ni layer dissolved into the Sn-Ag solder caps. The Ni was incorporated into the interfacial reactions, forming a (Cu,Ni)6Sn5 intermetallic compound on the Cu pillar bumps. Adding Ni to the Cu pillar bumps significantly affected the mechanical properties of the joint and increased the bump shear strength of the solder cap.

Moisture Effects on NCF Adhesion and Solder Joint Reliability of Chip-on-Board Assembly Using Cu Pillar/Sn–Ag Microbump

Electronic devices as well as electronic packaging technology have required higher speed, I/O capability, and density. To meet these requirements, flip-chip solder bumps interconnection combined with reflow assembly process has been a widely used. In spite of the many advantages of flip-chip solder bump joints, there is a limitation for less than 100 $\mu \text{m}$ fine pitch interconnection due to the solder bump bridging during the assembly process. Therefore, nonconductive films (NCFs) and Cu pillar/Sn–Ag microbump interconnection become a promising interconnection solution for fine pitch assembly. However, NCFs technology has some problems for flip-chip assembly. Epoxy-based NCF can easily absorb moisture, causing delamination reliability problem at moisture environment. In order to solve the interconnection, the NCF adhesion should be enhanced. Silane coupling agent (SCA) was added to NCFs to secure the microbump joint reliability for chip-on-board assembly by increasing the adhesion strength in the pressure cooker test. After the humidity test, the NCFs’ modulus and Tg were increased by adding SCA content. Moreover, the measured adhesion strength and energy showed similar results after the humidity test that higher SCA content showed high adhesion strength and energy than lower SCA content and unmodified NCF at the interface between NCF and solder resist of the printed circuit board substrate. The bump joint lifetime of 5wt% SCA NCF was longer than 1wt% SCA and unmodified NCF after the humidity test. In this paper, we report results of our investigations on effects of employing SCA in NCF composition for improved moisture resistance.

Effects of Thermocompression Bonding Parameters on Cu Pillar/Sn-Ag Microbump Solder Joint Morphology Using Nonconductive Films

In this paper, wafer-level preapplied nonconductive films (NCFs) were used to interconnect the Cu pillar/Sn-Ag microbumps for 3-D through silicon via vertical interconnection. Thermocompression bonding is a common method to interconnect chips to substrates using NCFs, and thermocompression bonding time should be reduced to increase the bonding productivity. Therefore, isothermal bonding method without heating and cooling process in bonding profile was introduced to reduce the bonding time. Solder joints bonded by an isothermal bonding method were compared to those joints bonded by a conventional ramp-up bonding method that was consist of heating, bonding, and cooling process. Final joint gap was decreased using an isothermal bonding method due to higher heating rate, and solder joint morphology was also changed according to the final solder joint gap. Furthermore, solder joint should have enough contact area to substrate metal pads without solder wetting on the Cu pillar sidewall to avoid reliability problems by Sn consumption at the solder joint. Effects of isothermal bonding parameters were investigated in terms of the bonding pressure, temperature, and time to optimize the isothermal bonding parameters for good solder joint. As bonding pressure and bonding temperature increased, solder joint gap decreased because final joint gap was determined by bonding pressures and dynamic viscosity of NCFs. Isothermal bonding times can be reduced to 10 s, because the degree-of-cure of NCFs could be over 90% after 2.2 s. As a summary, solder joint bonded with NCFs using optimized isothermal bonding parameters showed excellent bump joint resistances and solder wetting on substrate metal pads.

Capillary Self-Assembly for 3D Heterogeneous System Integration and Packaging

ABSTRACTThe self-assembly of known good dies (KGDs) on substrates using the liquid capillary method is shown to be a promising technology to achieve three-dimensional (3D) heterogeneous system integration and packaging. Firstly, the effects of the edge structures of self-assembled substrates and chips on alignment accuracies were investigated. When hydrophobic sidewalls with 10-µm-height steps were applied to both chips and assembly sites formed on substrates, the alignment accuracy within 1.0 µm was realized. The alignment accuracies were within 2.0 µm using either substrates or chips having 10-µm-height step structures with hydrophobic sidewalls. Self-assembly of 12-ch vertical-cavity surface-emitting lasers (VCSELs) with a long rectangle shape on glass substrates were also demonstrated. Separation of assembly sites into twelve areas enhanced the resultant force acting on the VCSEL short edge. The enhanced resultant force provided the high alignment accuracies within 2.0 μm. After the self-assembly of the VCSEL and the subsequent thermal compression, the chips successfully exhibited no degradation of their current–voltage (I–V) characteristics and appropriate 850-nm light emission. We demonstrated self-assembly and microbump bonding using non-conductive film (NCF)-covered dies with Cu/Sn microbumps for high-throughput and high-yield multichip-to-wafer 3D integration. The self-assembly of the NCF-covered dies provided high alignment accuracy within 1.1 μm on average. After the self-assembly of NCF-coved dies and thermal compression, microbump chains composed of 7396 bump joints were successfully obtained, resulting in good electrical properties of 32 mΩ/joint without any bridge shorts and failures. The variations of microbump joint resistance were maintained within 5% of the initial value after thermal cycle testing of even 1000 cycles.

Characterization of transmission lines with through-silicon-vias and bump joints on high-resistivity Si interposers for RF three-dimensional modules

Microstrip lines and coplanar waveguides (CPWs) for RF three-dimensional (3D) modules were characterized on high-resistivity Si interposers: 2,000 Ω·cm. The diameter and thickness of through-silicon-vias (TSVs) in Si interposers were 50 and 250 µm, respectively. A signal TSV around five ground TSVs, and a signal solder bump around five ground solder bumps were designed to obtain the vertical transitions with low electrical loss between the transmission lines. For the 3D interconnections between Si interposers, a fluxing underfill material was developed and used as a preapplied underfill during the thermocompression bonding. The S-parameters of transmission lines and stacked transmission lines were measured from 0.5 to 10 GHz using a vector network analyzer (VNA) and de-embedded so that their electrical losses were obtained and compared. By comparing with the electrical loss of the transmission line on low-temperature cofired ceramics (LTCC), we found that both transmission lines were sufficiently good for applications in RF 3D modules.

Effects of PCB Pad Metal Finishes on the Cu-Pillar/Sn-Ag Micro Bump Joint Reliability of Chip-on-Board (COB) Assembly

While solder bumps have been used as the bump structure to form the interconnection during the last few decades, the continuing scaling down of devices has led to a change in the bump structure to Cu-pillar/Sn-Ag micro-bumps. Cu-pillar/Sn-Ag micro-bump interconnections differ from conventional solder bump interconnections in terms of their assembly processing and reliability. A thermo-compression bonding method with pre-applied b-stage non-conductive films has been adopted to form solder joints between Cu pillar/Sn-Ag micro bumps and printed circuit board vehicles, using various pad metal finishes. As a result, various interfacial inter-metallic compounds (IMCs) reactions and stress concentrations occur at the Cu pillar/Sn-Ag micro bumps joints. Therefore, it is necessary to investigate the influence of pad metal finishes on the structural reliability of fine pitch Cu pillar/Sn-Ag micro bumps flip chip packaging. In this study, four different pad surface finishes (Thin Ni ENEPIG, OSP, ENEPIG, ENIG) were evaluated in terms of their interconnection reliability by thermal cycle (T/C) test up to 2000 cycles at temperatures ranging from −55°C to 125°C and high-temperature storage test up to 1000 h at 150°C. The contact resistances of the Cu pillar/Sn-Ag micro bump showed significant differences after the T/C reliability test in the following order: thin Ni ENEPIG > OSP > ENEPIG where the thin Ni ENEPIG pad metal finish provided the best Cu pillar/Sn-Ag micro bump interconnection in terms of bump joint reliability. Various IMCs formed between the bump joint areas can account for the main failure mechanism.

Aging resistance and mechanical properties of Sn3.0Ag0.5Cu solder bump joints with different bump shapes

The effects of bump shape on the aging resistance and mechanical properties of Sn3.0Ag0.5Cu (SAC) solder bump joints were investigated by high-temperature aging test and shear test. Three different SAC solder bump joints with barrel type, cylinder type, and hourglass type, respectively, were provided by controlling solder process. The results indicate that as the bump volume decreases from barrel bump to hourglass bump in the reflow, the thickness growth rate of intermetallic compounds (IMCs) between different solder joints and Cu substrates in the isothermal aging of 150 °C decreases. And the change of shear strength of hourglass interconnection solder joint with the increase in temperature is the minimum in the three interconnection solder joints. Thus, as the solder dosage decreases properly, hourglass interconnection solder joint is obtained, which is avail to enhance the solder joint reliability at the high-temperature aging and the ability to adapt to the change of environment temperature suddenly.

Properties and Reliability of Solder Microbump Joints Between Si Chips and a Flexible Substrate

Future generations of electronics are expected to include flexible, bendable, and wearable devices. There have been very few studies, however, on the bonding technology and reliability of bonding joints between a chip and a flexible substrate. In this study, we investigated the properties and reliability of joints formed with Sn-58Bi solder microbumps between a Si chip and a flexible substrate. For fine-pitch bonding, we formed Cu pillar bumps and Sn-58Bi solder microbumps with diameter of 25 μm by electroplating. The Si chips were then bonded on a flexible substrate finished with electroless nickel immersion gold (ENIG) using flip-chip technology, processing at 170°C under a force of 1 N, 2 N, or 3 N for 15 s. Cross-sectional images of bump joints were analyzed using field-emission scanning electron microscopy. While the Cu6Sn5 intermetallic compound (IMC) was formed on the Cu-pillar-bump side, another IMC, Ni3Sn4, was formed on the ENIG–substrate side. In addition, we performed a shear test, thermal shock test, and bending test to evaluate the joints’ mechanical properties and reliability. The bending test was performed by a machine designed for joints on flexible substrates. Unit shear force of 2 N was the nominally highest value obtained from joints prepared under the three bonding conditions. After the thermal shock test, we observed cracks initiated at the Cu6Sn5/Sn-58Bi interface, which then propagated within the solder bumps or at the interface. In the case of the bending test, failure occurred at the Ni3Sn4/Sn-58Bi interface or within the solder bumps.

Enhancement of mean-time-to-failure of Sn3.0Ag0.5Cu solder bump joint under current stressing via controlling bump shape

In this research, two different Sn3.0Ag0.5Cu solder bump joints with barrel shape and hourglass shape respectively were fabricated by controlling solder process, and evolution of intermetallic compounds (IMC) between different solder joint and Cu substrate under 4 × 103 A/cm2 current stressing at 60 °C were investigated. The results indicate that both the decrease of IMC layer thickness in the cathode and the increase of IMC layer thickness in the anode of the hourglass-shaped solder bump joint were obviously slower than that of barrel-shaped solder bump joint, and the formation of the voids at cathode interface was observed in the barrel-shaped solder bump joint after current stressing for 240 h. The mean-time-to-failure (MTTF) of solder joint with hourglass-shaped bump is efficiently improved compared to that with barrel-shaped bump. Compared to that of the solder joint with barrel-shaped bump, enhancement of MTTF of the solder joint with hourglass-shaped bump is attributed to relieve current crowding in entrance and outlet of electric current.

Theoretical and experimental determination of Cu diffusivity in eutectic Sn–Ag system at 235–280 °C

This study evaluated the Cu diffusion and dissolution behaviors in eutectic Sn–Ag alloy with a mathematical model in combination with experimental data. The diffusion was performed at temperatures ranging from 235°C to 280°C with a Cu/Sn–3.5Ag solder bump joint, where the Cu substrate was a solid but the Sn–3.5Ag solder bump was a liquid at all of the temperatures examined. The Cu diffusion coefficient (DCu) with respect to temperature, the activation energy of the Cu diffusion (Q), and the average Cu concentration (Cavg) as a function of diffusion time (t) were investigated via this metallurgical system. The coefficients DCu were 1.2(±0.4)×10−9m2/s (235°C), 2.4(±0.6)×10−9m2/s (250°C), 2.6(±0.7)×10−9m2/s (265°C), and 3.9(±1.6)×10−9m2/s (280°C), which are of the same order as those acquired from the capillary-reservoir technique for the bulk Cu/Sn system by Ma and Swalin in 1969. The activation energy Q was estimated based on the Arrhenius relation and was approximately 13.3kJ/mol at 235–280°C, reflecting the insensitivity of DCu to temperature. A calculated Cavg–t profile predicted that Cavg approaches saturation after 70s (235°C), which agrees well with experiments. The modeling results were consistent with the experimental and literature data, indicating that the proposed mathematical model is an effective method to represent the Cu diffusion/dissolution behavior in a confined solder alloy.

Comparison of Cu-Sn Compound Formation Between Snag and Pure Sn Solder Bumps by EBSD

Anisotropic behavior of Sn based solder during electromigration has been studied by many researchers, and it is very important to control the microstructure for more reliable bump joints[1]. Here, we prepared various SnAg bumps with different Ag concentrations including pure Sn[2]. Unary electroplating has various advantages such as easy handling bath, negligible bump composition and maintaining equipment with securing about environmental health and safety issue.Figure 1 shows our preliminary experiments for the cross-sectional EBSD and EDS measurement of Cu pillar with pure Sn bump, and it is reflowed at 235°C for 6 min. In this study, we will report comparison of Sn microstructures according to various Ag inclusions by using cross-sectional EBSD(electron backscattered diffraction) analysis and EDS(energy dispersive spectroscopy) measurement. We carried out multiple reflows at various atmosphere how this impact IMC(intermetallic compound) growth along with microstructures. Through this crystallographic aspect approach, we will present optimum condition for resistance of electro migration and void formation.[1] Yiwei Wang, Kuan H. Lu, Vikas Gupta, Leon Stiborek, Dwayne Shirley, Seung-Hyun Chae, Jay Im, Paul S. Ho, J. Mater. Res., 27, 1131 (2008)[2] Ui-Hyoung Lee, Moongi Cho, Woojin Choi, Ha-Young You, Jinho Choi and Jaihyung Won, 224th ECS meeting, San Francisco, Oct. (2013)

15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications

In this paper, we report the development of reliable fine-pitch micro bump interconnections that used a high-precision room-temperature bonding approach. The accuracy of the bonding process is improved by modifying conventional bump/planar-bonding-pad interconnections to form self-aligned micro bumps/truncated inverted pyramid (TIP) bonding pads, i.e., misalignment self-correction elements (MSCEs). Thermosonic flip-chip bonding (FCB) is utilized to form reliable bonds between these MSCEs at acceptable low temperatures. By applying the proposed bonding approach, the demonstration of fine-pitch Cu bump to Au bonding pad interconnects chip stacking has been realized. Microstructure analyses reveal that 15-µm-pitch micro bump joints are fabricated at room temperature.

3차원 적층 패키지를 위한 ISB 본딩 공정의 파라미터에 따른 파괴모드 분석에 관한 연구

3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder <TEX>${\mu}$</TEX>-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.