Bump Bonds Research Articles

Inversion for Thermal Properties with Frequency Domain Thermoreflectance.

3D integration of multiple microelectronic devices improves size, weight, and power while increasing the number of interconnections between components. One integration method involves the use of metal bump bonds to connect devices and components on a common interposer platform. Significant variations in the coefficient of thermal expansion in such systems lead to stresses that can cause thermomechanical and electrical failures. More advanced characterization and failure analysis techniques are necessary to assess the bond quality between components. Frequency domain thermoreflectance (FDTR) is a nondestructive, noncontact testing method used to determine thermal properties in a sample by fitting the phase lag between an applied heat flux and the surface temperature response. The typical use of FDTR data involves fitting for thermal properties in geometries with a high degree of symmetry. In this work, finite element method simulations are performed using high performance computing codes to facilitate the modeling of samples with arbitrary geometric complexity. A gradient-based optimization technique is also presented to determine unknown thermal properties in a discretized domain. Using experimental FDTR data from a GaN-diamond sample, thermal conductivity is then determined in an unknown layer to provide a spatial map of bond quality at various points in the sample.

Towards MightyPix, an HV-MAPS for the LHCb Mighty Tracker upgrade

The Mighty Tracker is a proposed upgrade to the downstream tracking system of LHCb for operations at luminosities of up to 1.5 × 1034 cm−2 s−1 starting with the LHC Run 5 data taking period. It foresees the replacement of the most central area of the current scintillating fibre tracker with High Voltage CMOS (HV-CMOS) pixel sensors. Due to the increased luminosity, occupancy will be too high for track reconstruction in the fibre tracker and the fibres would no longer withstand the radiation damage. HV-CMOS sensors have demonstrated a significant radiation tolerance and good performance making them an ideal choice of technology for the LHCb experiment. Monolithic Active Pixel Sensors (MAPS) fabricated in HV-CMOS processes provide fast charge collection via drift and allow the implementation of the readout on the same die as the sensitive volume. Due to the use of commercial processes, these sensors can be fabricated at low cost as no hybridisation with bump bonds is required. Since they are not fully depleted, the inactive volume can be reduced by thinning to achieve a total die thickness of 50 to 100 microns. A dedicated sensor called the MightyPix is developed for this programme. It is based on the HV-MAPS families MuPix and ATLASPix and tailored to the requirements of LHCb. To demonstrate the feasibility of this technology for the LHCb environment, prototypes have been irradiated. These sensors are tested in terms of efficiency, time resolution and power dissipation in temperature controlled environments.

Formation of Ohmic Contacts to n-GaAs at Temperatures Compatible with Indium Flip-Chip Bonding

Heterogenous integration of III-V photodetectors with Si readout circuitry is an enabling technology for applications including focal plane arrays [1] and concentrating solar cells [2, 3]. Typical integration schemes include low temperature flip-chip bonding using indium (In) bump bonds, followed by epoxy underfill, and mechanical and/or chemical removal of the III-V substrate to expose the epitaxially grown detector layers [1]. For maximum flexibility in device design and processing, it is desirable to be able to form low resistance illumination-side contacts to either p-type or n-type layers after flip-chip bonding. Formation of non-alloyed contacts to p-GaAs is relatively straightforward and can be readily implemented after flip-chip bonding [4]. Conventional contacts to n-GaAs are formed by evaporation of Ge/Au/Ni followed by a rapid thermal annealing step at 400 °C [4], considerably above the 156 °C melting point of In and above the degradation temperature of many standard underfill epoxies. Several groups have studied the formation of ohmic contacts to n-GaAs through low temperature annealing of Pd/Ge/Au metal stacks [3, 5, 6], however all reports to date have used annealing temperatures near or above the melting point of In. In this work, we report the formation of ohmic contacts with a specific contact resistivity as low as 5.6×10-6 Ω-cm2 after annealing at a temperature of 140 °C, significantly below the In melting point. Figures 1 and 2 show experimental results of transfer line method (TLM) test structures measured on an epitaxially grown 800 nm thick, 1x1018 cm-3 n-GaAs layer with 7 nm Pd/ 50 nm Ge/ 200 nm Au contacts patterned with photolithography and evaporation. The samples were annealed in an oven with a N2 ambient and measured repeatedly throughout the annealing process. We observe a transition from Schottky to ohmic behavior after 10 hours of annealing followed by a steady decrease in resistance for annealing times out to 48 hours. A companion sample that had been flip-chip bonded with In bumps and underfilled with Epotek 301 epoxy showed no degradation after annealing. The black line in Fig. 1 is provided as a reference of the measured specific contact resistivity of a standard Ge/Au/Ni/Au metal stack deposited on the same n-GaAs layer after a 30 second, 400 °C anneal. The creation of low-resistance ohmic contacts to n-GaAs at this low temperature is an enabling technology for III-V heterogeneous integration efforts with a wide array of temperature-sensitive materials such as In, epoxies, photoresists, and plastics. Acknowledgment Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

(Invited) Heterogeneous Integration of III-V Semiconductors for Imaging and High-Speed Communication

Heterogenous integration of III-V compound semiconductors with Si circuitry is an enabling technology for applications including high-bandwidth communications [1], focal plane arrays [2] and concentrating solar cells [3, 4]. Typical integration schemes include low temperature flip-chip bonding using indium bump bonds along with epoxy underfill and may include the integration of micro-optics for collimation and focusing. In this talk, I will discuss previous and ongoing compound semiconductor heterogenous integration efforts at Sandia National Laboratories and the challenges involved in forming high-yield devices. Specific programs to be discussed include the ARPA-E MOSAIC solar concentrator (Fig. 1), infrared focal plan arrays (Fig. 2), and the recently-awarded DARPA PIPES ultra-low-energy-per-bit photonic transceiver. References Ciftcioglu, et al, “3-D integrated heterogenous intra-chip free-space optical interconnect,” Opt. Express, vol. 20 2012.W. Peters, et al., “Resonant ultrathin infrared detectors enabling high quantum efficiency,” IEEE RAPID, 2018.Li, et al., “Wafer integrated micro-scale concentrating photovoltaics,” Prog. Photovoltaics, vol. 26, 2018.H. Jared, et al., “Integration of wafer-level solar cells and micro-optic concentrators for micro-scale concentrating photovoltaics,” ASPE Annual Meeting, 2017. Acknowledgment This work was supported in part by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Figure 1

Mitigating leakage errors due to cavity modes in a superconducting quantum computer

A practical quantum computer requires quantum bit (qubit) operations with low error probabilities in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of coaxial Pogo pins. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We analyze these interference effects in the context of qubit coherent leakage and qubit decoherence induced by damped modes. We propose two methods, half-wave fencing and antinode pinning, to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed pins and can be engineered to be significantly higher than the highest qubit frequency. We estimate that the error probabilities and decoherence rates due to suitably shifted modes in realistic scenarios can be up to two orders of magnitude lower than the state-of-the-art superconducting qubit error and decoherence rates. Our methods can be extended to different types of packages that do not rely on Pogo pins. Conductive bump bonds, for example, can serve the same purpose in qubit architectures based on flip chip technology. Metalized vias, instead, can be used to mitigate modes due to the increasing size of the dielectric substrate on which qubit arrays are patterned.

Ball-grid array architecture for microfabricated ion traps

State-of-the-art microfabricated ion traps for quantum information research are approaching nearly one hundred control electrodes. We report here on the development and testing of a new architecture for microfabricated ion traps, built around ball-grid array (BGA) connections, that is suitable for increasingly complex trap designs. In the BGA trap, through-substrate vias bring electrical signals from the back side of the trap die to the surface trap structure on the top side. Gold-ball bump bonds connect the back side of the trap die to an interposer for signal routing from the carrier. Trench capacitors fabricated into the trap die replace area-intensive surface or edge capacitors. Wirebonds in the BGA architecture are moved to the interposer. These last two features allow the trap die to be reduced to only the area required to produce trapping fields. The smaller trap dimensions allow tight focusing of an addressing laser beam for fast single-qubit rotations. Performance of the BGA trap as characterized with 40Ca+ ions is comparable to previous surface-electrode traps in terms of ion heating rate, mode frequency stability, and storage lifetime. We demonstrate two-qubit entanglement operations with 171Yb+ ions in a second BGA trap.

PETA4: a multi-channel TDC/ADC ASIC for SiPM readout

The PETA4 ASIC is the latest member of a family of chips targeted mainly at the readout of Silicon Photomultipliers in PET, with possible use in other detector applications. PETA4 houses 36 channels on a 5 × 5mm2 die and is fabricated in the UMC 180nm technology.It uses bump bonds with a convenient pitch of ≈ 270μm to allow the construction of very compact modules at moderate substrate cost. The chip requires nearly no external components by integrating everything (PLL loop filter, bandgap reference, bias DACs,…) on chip. Power consumption is ⩽ 40mW per channel, depending on digital speed and bias settings.Every channel has two independent frontends: an established differential amplifier which has shown to be insensitive to pickup in the target application of PET/MRI, and a single-ended frontend with very low input impedance (Zin ≈ 7Ω) for high channel count operation. A fast discriminator with tunable threshold and a noise of ⩽ 300μV self-triggers time stamping with a bin width of 50ps as well as an integratorwith programmable integration time. The amplitude signal is converted by a ≈ 9-bit SAR ADC. After conversion, events with sufficient amplitude arequeued for serial readout. The previous chip version PETA3 has achieved a CRT time resolution of ≈ 200ps when reading out scintillation lightfrom a 3 × 3×5mm3 LYSO crystal coupled at room temperature to a 3 × 3mm2 SiPM from FBK. Energy resolution for LYSO is ≈ 12.5%FWHM. LYSO crystals of 1.3mm size could be clearly identified with SiPMs of 4 × 4mm2 when using a light spreader.The architecture of PETA4 and its performance in the lab and with SiPMs will be presented.

Development of Through-Wafer Interconnects for MEMS Deformable Mirrors

A MEMS deformable mirror (DM) packaging process development effort is described. This development provides a path towards direct integration of future large actuator count optical MEMS arrays (> 4000) with underlying driver electronics. Characteristic features of the packaging process include creating electrical interconnection paths through the silicon wafer for each actuator, depositing gold bump bonds on the backside of the wafer, and fusing that array of bump bonds to an interposer substrate. This process differs from existing processes for MEMS arrays, which generally employ lithographically patterned wire-routing and peripheral wire bonding from the front surface of the MEMS array. In this article a feasibility experiment is described and successful results and process parameters are presented.

3D design activities at Fermilab—Opportunities for physics

Fermilab began exploring the technologies for vertically integrated circuits (also commonly known as 3D circuits) in 2006. These technologies include through silicon vias (TSV), circuit thinning, and bonding techniques to replace conventional bump bonds. Since then, the interest within the High Energy Physics community has grown considerably. This paper will present an overview of the activities at Fermilab over the last 3 years which have helped spark this interest.

Effect of Warpage of Flip Chip Packages Due to the Underfill Encapsulating Process on Interconnect Reliability

In flip chip packages, it is common practice for interconnects to be encapsulated with a liquid underfill material. This paper describes the effects of different underfill processes, i.e., the conventional capillary-flow underfill and two no-flow underfill processes, on flip chip packaging. The warpage of the package was examined, and the value of this during three different underfill encapsulating processes was measured. In addition, the interconnect reliability of the bump bonds after thermal-cycling was evaluated using a test circuit. The warpage of the package before curing varied depending on the assembly process, but that after curing was almost the same for all the processes studied. It was found that the interconnect reliability is closely related to the differences in the warpage arising from the assembly process, and that the smaller change in warpage introduced by the curing process gave a higher interconnect reliability for the bump bonds. Based on these findings, lower curing temperatures are considered to be more effective for improving the mountability of the package and the interconnect reliability.

Implementation and Experimental Evaluation of a Cryocooled System Prototype for High-Throughput SFQ Digital Applications

We report on development of a cryocooled system prototype for high-throughput single flux quantum (SFQ) digital applications. The system was designed to have 32 I/O links with a bandwidth of 10 Gbps/port. An SFQ multi-chip module (MCM), double mu-metal magnetic shields, a 40-K radiation shield, customized GaAs cryogenic amplifiers, a 32-pin wide-bandwidth cryo-probe, and 32 I/O cables were packaged in a vacuum chamber together with a two-stage 4-K 1-W Gifford-McMahon (G-M) cryocooler. S-parameter measurements showed that the analog bandwidth of the I/O link was 23 GHz. We demonstrated high-speed cryocooled operation of a test module, in which a 5 mm times 5 mm SFQ circuit chip was flip-chip bonded on a 16 mm times 16 mm MCM carrier with phi30 mum InSn bump bonds, at bit rates up to 12.5 Gbps. Measured bit error rate (BER) was less than 10-12 for a 1023 - 1 pseudorandom bit sequence (PRBS) at 10 Gbps.

Test structure assembly for bump bond yield measurement on high density flip chip technologies

Modern flip chip technologies for imaging applications have achieved a very high integration level together with the possibility of large area assemblies. These developments have resulted in an enormous increase in the total number of bump bonds per assembly. Consequently, yield tests become difficult, and an accurate measurement of it is often discarded. This problem is aggravated in medical applications, where the critical information can be limited to a few pixels, and therefore, yield should be very close to 100%. In these cases, a variation of a small percentage in bump bond yield can make the difference between an usable and a non-usable assembly. Therefore, quantitative and precise measurement of bump bond yield is needed to characterize the quality of any high density flip chip technology for these applications. In this paper, we present a newly developed test structure for electrical measurement of the bump bond yield of high density flip chip technologies, allowing both optimization and statistical control of the process. This test structure facilitates the identification of possible process deviations with precise quantitative yield measurements. It also allows to pin point any localized systematic failure in the bump bonding process. The test structure has been used to evaluate the yield of different flip chip technologies and has contributed to their fine optimization where necessary.

Study of temperature dependence of bump bonding for the BTeV pixel detector

The pixel detector proposed for the BTeV experiment at the Fermilab Tevatron will use bump-bonding technology based on either Indium or Pb/Sn solder to connect the front-end readout chips to the silicon pixel sensors. We have studied the behavior of the bumps by visual inspection of the bumps bonding silicon sensor modules to dummy chips made out of glass. The studies were done before and after thermal cycles, exposure to intense irradiation, and with the assemblies glued to a graphite substrate. We have also carried out studies on effects of temperature changes on both types of bump bonds by observing the responses of single-chip pixel detectors to a /sup 90/Sr source. We report the results from these studies as well as the noise and threshold behavior of the pixel readout at various temperatures.

SCUBA-2: A large-format TES array for submillimetre astronomy

SCUBA-2, which replaces the Submillimetre Common User Bolometer Array (SCUBA) (Mon. Not. R. Astron. Soc. 303 (1999) 659) on the James Clerk Maxwell telescope in 2006, will be the first CCD-like array for submillimeter astronomy. Unlike previous detectors which have used discrete bolometers, SCUBA-2 has two DC-coupled, monolithic, filled arrays with a total of ∼10,000 bolometers. It will offer simultaneous imaging of an 8×8 arcmin field of view at wavelengths of 850 and 450μm. SCUBA-2 is expected to have a huge impact on the study of galaxy formation and evolution in the early Universe as well as star and planet formation in our own Galaxy. Mapping the sky to the same S/N up to 1000 times faster than SCUBA, it will also act as a pathfinder for the new submillimetre interferometers such as ALMA. SCUBA-2's absorber-coupled pixels use superconducting transition edge sensors (Ph.D. Thesis, Stanford, 1995) operating at ∼120mK for photon noise limited performance. The monolithic silicon detector arrays are deep-etched by the Bosch process to isolate the pixels on silicon nitride membranes (Nucl. Instr. and Meth. A, these proceedings). Electrical connections are made through indium bump bonds to a backplane that incorporates a SQUID time-domain multiplexer. We describe the key technologies that make SCUBA-2 possible and give an update on the considerable progress in the detector development and instrument design that has taken place over the last 2 years.

A technique for interconnecting millimeter wave integrated circuits using BCB and bump bonds

A low cost interconnection scheme for millimeter wave modules is presented. This technique allows the integration of hybrid components using an inexpensive micromachined silicon motherboard and benzocyclobutene (BCB) films. The excellent planarity of BCB allows vias to be formed using bumps fabricated prior to BCB application. This approach eliminates the need for laser drilling, plasma etching, and plated holes. Several representative GaAs pHEMT's were packaged using this technique. Measurements show minimal performance degradation from 1 GHz to 48 GHz.

Threshold characterisation of the Medipix1 chip

The Medipix1 chip is a hybrid pixel detector working in photon counting mode and has the ability to put a discriminating threshold on each photon signal. To increase the image quality the threshold voltage can be electronically fine tuned with a 3 bit threshold adjust for each pixel. This electronic adjustment can only equalise the inhomogeneities of the electronics, not those of the physical frontend (conversion material and bump bonds). The remaining noise of the threshold has an obvious impact on the image quality. To optimise the uniformity over the whole chip we did threshold scans with a cadmium X-ray source analysing every pixel. With those scans we were able to create a bit mask including the physical frontend. Comparing the results of the different methods we can judge the quality of the electronically generated mask and draw conclusions about the properties of the physical frontend. Furthermore, simulations have been carried out for comparison with the measured data.

Silicon nitride micromesh bolometer array for submillimeter astrophysics

We present the design and performance of a feedhorn-coupled bolometer array intended for a sensitive 350-mum photometer camera. Silicon nitride micromesh absorbers minimize the suspended mass and heat capacity of the bolometers. The temperature transducers, neutron-transmutation-doped Ge thermistors, are attached to the absorber with In bump bonds. Vapor-deposited electrical leads address the thermistors and determine the thermal conductance of the bolometers. The bolometer array demonstrates a dark noise-equivalent power of 2.9 x 10(-17) W/ radicalHz and a mean heat capacity of 1.3 pJ/K at 390 mK. We measure the optical efficiency of the bolometer and feedhorn to be 0.45-0.65 by comparing the response to blackbody calibration sources. The bolometer array demonstrates theoretical noise performance arising from the photon and the phonon and Johnson noise, with photon noise dominant under the design background conditions. We measure the ratio of total noise to photon noise to be 1.21 under an absorbed optical power of 2.4 pW. Excess noise is negligible for audio frequencies as low as 30 mHz. We summarize the trade-offs between bare and feedhorn-coupled detectors and discuss the estimated performance limits of micromesh bolometers. The bolometer array demonstrates the sensitivity required for photon noise-limited performance from a spaceborne, passively cooled telescope.

High-speed interchip data transmission technology for superconducting multi-chip modules

We have developed an interchip data transmission scheme through passive transmission lines on a multi-chip-module (MCM) carrier and 100-/spl mu/m solder bump bonds. In rapid single flux quantum (RSFQ) logic, digital data are in the form of single flux quantum (SFQ) pulses. A reliable scheme for transmission of SFQ pulses through non-superconducting solder bumps between chips through a passive MCM substrate is yet to be established. Therefore, we have devised a scheme that converts SFQ pulses into toggles in a voltage waveform for interchip transmission. Data in the form of SFQ pulses are reconstructed from this voltage waveform using a sensitive quantizing pulse receiver. Our objective is to eliminate the need for amplification of the transmitted signal. This is achieved by increasing the receiver sensitivity. However, a sensitive receiver, a dc SQUID, may produce more than one SFQ pulse for each rising/falling edge of the voltage waveform. A simple circuit, pulse resurrection logic (PRL), is employed to discard any extra SFQ pulses. Together with the sensitive quantizer, the PRL circuit makes our scheme error tolerant. We have demonstrated the receiver operation using 3-/spl mu/m Nb RSFQ circuits at frequencies up to 20 GHz.

High-Sensitivity Visible-Blind AlGaN Photodiodes and Photodiode Arrays

Visible-blind UV cameras based on a 32 × 32 array of backside-illuminated GaN/AlGaN p-i-n photodiodes have been successfully demonstrated. The photodiode arrays were hybridized to silicon readout integrated circuits (ROICs) using In bump bonds. Output from the UV cameras were recorded at room temperature at frame rates of 30−240 Hz. These new visible-blind digital cameras are sensitive to radiation from 285−365 nm in the UV spectral region.

UV-Specific (320-365 nm) Digital Camera Based On a 128×128 Focal Plane Array of GaN/AlGaN p-i-n Photodiodes

An ultraviolet-specific (320-365 nm) digital camera based on a 128×128 array of backside-illuminated GaN/AlGaN p-i-n photodiodes has been successfully developed. The diode structure consists of a base n-type layer of AlGaN (~23% Al) followed by undoped and then p-type GaN layers deposited by metal organic vapor phase epitaxy. Double-side polished sapphire wafers serve as transparent substrates. Standard photolithographic, etching, and metallization procedures were employed to fabricate the devices. The fully-processed photodiode array was hybridized to a silicon readout integrated circuit (ROIC) using In bump bonds for electrical contact. The UV camera was operated at room temperature at frame rates ranging from 15 to 240 Hz. A variety of UV scenes were successfully recorded with this configuration.