Bulk Static Random Access Memories Research Articles

Impact of Dynamic Voltage Scaling on SEU Sensitivity of COTS Bulk SRAMs and A-LPSRAMs Against Proton Radiation

In the aerospace industry, commercial-off-the-shelf (COTS) static random access memories (SRAMs) are a cost-effective solution for obtaining high performance at the system level, which is difficult to obtain using space-qualified components. In addition, the usage of dynamic voltage scaling (DVS) is commonly used in space environments, where low power consumption is a critical issue. This article presents an analysis of the sensitivity against single-event upsets (SEUs) of various COTS bulk SRAMs and advanced low-power SRAMs (A-LPSRAMs) against proton radiation when using DVS to save power. Experimental results will show clear evidence that the sensitivity to SEUs increases when the power is lowered. Two sets of successive technologies (130-, 90-, and 65-nm bulk SRAMs, and 150- and 110-nm A-LPSRAMs) are evaluated against 15-MeV protons and compared with results of 14-MeV neutrons presented in a previous work. Experimental data are finally compared with analytical simulations obtained by using the multiscales single-event phenomena predictive platform (MUSCA-SEP3) Monte Carlo tool to predict the effect of DVS on the SEE sensitivity on more modern technologies in the ITRS/IRDS roadmap.

Statistical analysis of temperature dependence of worst case static random access memory data retention voltage using extreme value theory

The extreme value theory was adopted to analyze the temperature dependence of the worst case data retention voltage (DRV) in static random access memory (SRAM). It was found that the measured worst case DRV of bulk and fully depleted silicon-on-thin-buried-oxide (SOTB) SRAM follow a Gumbel distribution. By extrapolating the fitted Gumbel distribution, the worst DRV of large capacity SRAM at high temperature was estimated. It was also found that the temperature dependence of the worst case DRV in bulk SRAM diminishes as the capacity increases while that in SOTB SRAM is almost unchanged.

Irradiation Test of 65-nm Bulk SRAMs With DC Muon Beam at RCNP-MuSIC Facility

Negative and positive muon irradiation tests of static random access memories (SRAMs) were performed at Muon Science Innovation Channel (MuSIC) of Research Center for Nuclear Physics (RCNP), Osaka University. The muon-induced single event upset (SEU) cross sections for 65-nm bulk SRAMs were measured. The SRAM device was irradiated by the muon beams with average momenta ranging from 37.8 to 41.0 MeV/c at the beam exit. The incident muon fluence was measured using a one-by-one muon detection system with a plastic scintillator by taking advantage of the direct current (dc) muon beam and reliable absolute values of SEU cross sections were obtained. In addition to the measurement of the SEU cross sections, we measured muonic X-rays from the irradiated device to investigate the relation between the measured SEU cross section and the emission rate of muonic X-rays associated with the stopping position of the muons as a function of incident muon momentum. The result suggested that negative muons have a significant effect on SEUs by the emission of secondary light ions via negative muon capture reaction when negative muons stop near sensitive volumes (SVs) in SRAMs.

Measurement of Single-Event Upsets in 65-nm SRAMs Under Irradiation of Spallation Neutrons at J-PARC MLF

A neutron irradiation test of static random access memories (SRAMs) was performed using a spallation neutron source at Materials and Life Science Experimental Facility (MLF) in the Japan Proton Accelerator Research Complex (J-PARC). The probability of neutron-induced single-event upsets (SEUs) was measured for 65-nm bulk and silicon on thin buried oxide (SOTB) SRAMs under neutron irradiation at the BL10 experimental facility. The measured SEU data were compared with the previous data of the same SRAMs which were measured at other irradiation facilities having different neutron spectra. The differences in the operating voltage dependence of the measured SEU probabilities are discussed with particular attention to the impact of irradiation side on SEUs. The particle and heavy ion transport code system (PHITS) simulation based on the simple sensitive volume model qualitatively reproduced the operating voltage dependence seen in the measured ratio of SEUs for the Bulk SRAM between the resin side and board side irradiations under different neutron fields.

Similarity Analysis on Neutron- and Negative Muon-Induced MCUs in 65-nm Bulk SRAM

Multiple-cell upset (MCU) in static random access memory (SRAM) is a major concern in radiation effects on very large scale integration (VLSI) since it can spoil error correcting codes (ECCs). Neutron-induced MCUs have been characterized for terrestrial environment. On the other hand, negative muon-induced MCUs, which are caused by secondary ions generated through muon capture process, were recently reported. Neutron- and negative muon-induced MCUs are both caused by secondary ions, and hence, they are expected to have some similarity. In this paper, we compare negative muon- and neutron-induced MCUs in 65-nm bulk SRAMs at the irradiation experiments using spallation and quasi-monoenergetic neutrons and monoenergetic negative muons. The measurement results show that the dependencies of MCU event cross section on operating voltage are almost identical. The high operating voltage makes both negative muon- and neutron-induced MCU cross sections larger due to parasitic bipolar action. Consequently, large-bit MCUs are observed under the irradiation using both neutrons and muons. On the other hand, at 0.4 V, neutrons induce larger-bit MCUs (> 12 bits) whereas negative muons cause up to 11-bit MCUs. Upsets of 3 or larger bits along word line (WL) are observed at spallation neutron beams. To explain the similarity of MCUs induced by neutrons and negative muons, the Monte Carlo simulation is conducted to investigate the deposited charge. The distributions of deposited charge obtained by the simulation are consistent with the above-mentioned experimental observations.

Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs

Negative and positive muon-induced single-event upset (SEU) rates were estimated for 65-nm bulk and ultrathin body and thin buried oxide silicon-on-insulator (UTBB-SOI) static random access memories (SRAMs). The SEU cross sections for muon incidence on the two SRAMs were experimentally characterized and compared. The experimental results showed that the negative muon SEU cross sections for the bulk SRAM are significantly larger than those for the UTBB-SOI. Estimation of muon SEU rates at ground level was performed using the experimental results and the Monte Carlo simulation with the Particle and Heavy Ion Transport code System (PHITS). The estimated muon SEU rates were compared with the measured neutron SEU rates. The contribution of muons was found to be considerably smaller than that of neutrons. Attenuation effect of muons and neutrons in a five-story building was also investigated by particle transport simulation with PHITS. The muon SEU rate on the first floor was estimated to be at most 10% of the neutron SEU rate on the same floor.

Mechanisms of atmospheric neutron-induced single event upsets in nanometric SOI and bulk SRAM devices based on experiment-verified simulation tool**Project supported by the National Natural Science Foundation of China (Grant No. 11505033), the Science and Technology Research Project of Guangdong Province, China (Grant Nos. 2015B090901048 and 2017B090901068), and the Science and Technology Plan Project of Guangzhou, China (Grant No. 201707010186).

In this paper, a simulation tool named the neutron-induced single event effect predictive platform (NSEEP2) is proposed to reveal the mechanism of atmospheric neutron-induced single event effect (SEE) in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory (SRAM) device can be considered to calculate the real-time soft error rate (RTSER) in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP2, RTSERs of 90 nm–32 nm silicon on insulator (SOI) and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.

Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

This paper shows the impact of low linear energy transfer heavy ions on the reliability of 28-nm Bulk static random access memory (RAM) cells from Artix-7 field-programmable gate array. Irradiation tests on the ground showed significant differences in the multiple bit upset cross section of configuration RAM and block RAM memory cells under various angles of incidence and rotation of the device. Experimental data are analyzed at transistor level by using the single-event effect prediction tool called multiscale single-event phenomenon prediction platform coupled with SPICE simulations.

Impact of temperature on single event upset measurement by heavy ions in SRAM devices

The temperature dependence of single event upset (SEU) measurement both in commercial bulk and silicon on insulator (SOI) static random access memories (SRAMs) has been investigated by experiment in the Heavy Ion Research Facility in Lanzhou (HIRFL). For commercial bulk SRAM, the SEU cross section measured by 12C ions is very sensitive to the temperature. The temperature test of SEU in SOI SRAM was conducted by 209Bi and 12C ions, respectively, and the SEU cross sections display a remarkable growth with the elevated temperature for 12C ions but keep constant for 209Bi ions. The impact of temperature on SEU measurement was analyzed by Monte Carlo simulation. It is revealed that the SEU cross section is significantly affected by the temperature around the threshold linear energy transfer of SEU occurrence. As the SEU occurrence approaches saturation, the SEU cross section gradually exhibits less temperature dependency. Based on this result, the experimental data measured in HIRFL was analyzed, and then a reasonable method of predicting the on-orbit SEU rate was proposed.

Investigation of Threshold Ion Range for Accurate Single Event Upset Measurements in Both SOI and Bulk Technologies

Experimental evidences are presented showing obvious differences in threshold ion range for silicon-on-insulator (SOI) and bulk static random access memories (SRAMs). Single event upset (SEU) cross sections of SOI SRAMs start to decline off the Weibull curve at ion ranges of 20.7 μm to 40.6 μm, depending on the ion species and also the thickness of metallization layers. Whereas for the bulk SRAMs, threshold range of Bismuth beam is unexpectedly larger than 60.4 μm. Underlying mechanisms are further revealed by Monte Carlo simulations and in-depth analysis. The relative location of ion's Bragg peak to the sensitive region and also the position of ion LET in the σ-LET curve of test device turn out to be two key parameters in determining the threshold ion range which can explain the experimental results. Significant discrepancies are observed in the deposited energy spectrums in sensitive regions of bulk SRAM by ions at different sides of the Bragg peak, but with almost the same LET at die surface (all with ion range larger than 30 μm). Energy straggling of incident ions at the die surface is considered by Monte Carlo calculations. Implications for hardness assurance testing are also discussed. A formula is proposed for calculating the “worst case” threshold ion range.

Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

The minimum operation voltage (Vmin) of intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells are measured and compared with those of conventional bulk SRAM cells in order to directly compare the worst cells. It is confirmed that the worst Vmin of 1 kbit SOTB SRAM cells is half that of 1 kbit bulk cells. The distribution of Vmin of 48 kbit SOTB and bulk SRAM cells are also measured and compared. The results show a great advantage of SOTB SRAM cells for lower power and lower voltage operation upon introducing SOTB, because of reduced VTH variability.

Prediction of low-LET ion induced single event upset cross sections for advanced SRAM

This paper describes a simple circuit-level simulation-based approach to predict single event upset cross section induced by low-linear energy transfer (LET) ions for advanced bulk static random access memory (SRAM). A basic Simulation Program with Integrated Circuit Emphasis (SPICE) model with effective collection depth considered is developed for performing single event analysis quickly and efficiently. Through this circuit-level simulation model, radiation effects can be shown as the SPICE-simulated curve of LETs versus the corresponding affected distances, which are used for upset cross-section prediction. Furthermore, a fine-grain geometric model for cross-section prediction with fine sensitivity coefficient considered is utilized in the prediction. The calculated results based on this method are in good agreement with experimentally measured results reported for six-transistor SRAM fabricated in 90 nm and 65 nm process technologies.

Investigation of Cell Stability and Write Ability of FinFET Subthreshold SRAM Using Analytical SNM Model

In this paper, the static noise margin (SNM) of FinFET static random access memory (SRAM) cells operating in the subthreshold region was investigated using an analytical solution of 3-D Poisson's equation. An analytical SNM model for subthreshold FinFET SRAM was demonstrated and validated by 3-D technology computer-aided design (TCAD) mixed-mode simulations. When compared with bulk SRAM, the standard 6T FinFET cell showed larger nominal READ SNM (RSNM), better variability immunity, and lesser temperature sensitivity of cell stability. Furthermore, examination of the stabilities of several novel independently controlled gate FinFET SRAM cells by using the proposed SNM model showed significant nominal RSNM improvements in these novel cells. However, the write ability is found to be degraded, which thus becomes an important concern for certain configurations in the subthreshold region. The result obtained indicates that the READ/WRITE word line voltage control technique is more effective than transistor sizing in improving the stability and write ability of the FinFET subthreshold SRAM. Furthermore, the impacts of process-induced variations on cell stability were also assessed. When compared with RSNM, it was found that WRITE SNM is more susceptible to process variations. While 6T is not a viable candidate for subthreshold SRAM, and 8T/10T cells must be used in bulk CMOS, the present analysis established the potential of 6T FinFET cells for subthreshold SRAM applications.

Evaluation of soft error rates using nuclear probes in bulk and SOI SRAMs with a technology node of 90nm

Abstract The difference of soft error rates (SERs) in conventional bulk Si and silicon-on-insulator (SOI) static random access memories (SRAMs) with a technology node of 90 nm has been investigated by helium ion probes with energies ranging from 0.8 to 6.0 MeV and a dose of 75 ions/μm2. The SERs in the SOI SRAM were also investigated by oxygen ion probes with energies ranging from 9.0 to 18.0 MeV and doses of 0.14–0.76 ions/μm2. The soft error in the bulk and SOI SRAMs occurred by helium ion irradiation with energies at and above 1.95 and 2.10 MeV, respectively. The SER in the bulk SRAM saturated with ion energies at and above 2.5 MeV. The SER in the SOI SRAM became the highest by helium ion irradiation at 2.5 MeV and drastically decreased with increasing the ion energies above 2.5 MeV, in which helium ions at this energy range generated the maximum amount of excess charge carriers in a SOI body. The soft errors occurred by helium ions were induced by a floating body effect due to generated excess charge carriers in the channel regions. The soft error occurred by oxygen ion irradiation with energies at and above 10.5 MeV in the SOI SRAM. The SER in the SOI SRAM gradually increased with energies from 10.5 to 13.5 MeV and saturated at 18 MeV, in which the amount of charge carriers induced by oxygen ions in this energy range gradually increased. The computer calculation indicated that the oxygen ions with energies above 13.0 MeV generated more excess charge carriers than the critical charge of the 90 nm node SOI SRAM with the designed over-layer thickness. The soft errors, occurred by oxygen ions with energies at and below 12.5 MeV, were induced by a floating body effect due to the generated excess charge carriers in the channel regions and those with energies at and above 13.0 MeV were induced by both the floating body effect and generated excess carriers. The difference of the threshold energy of the oxygen ions between the experiment and the computer calculation might be due to the difference between the designed and real structures.