Bulk-driven Quasi-floating Gate Research Articles

Process voltage temperature analysis of MOS based balanced pseudo-resistors for biomedical analog circuit applications

PurposeAdoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.Design/methodology/approachIn this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.FindingsThe obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.Research limitations/implicationsVarious balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.Social implicationsThe PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.Originality/valueThe BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

A bulk-driven quasi-floating gate FVF current mirror for low voltage, low power applications

This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage. Benefiting from the interesting properties of (BD-QFG) MOSFET (MOST) technique, the proposed FVF current mirror circuit exhibits superior performance compared to other previously reported works. The workability of the proposed circuit has been verified through ELDO simulator based on a 0.18 μm USMC process. It achieves an enhanced bandwidth (2.7 GHz), low power consumption (79.33 μW), a low input impedance (130 Ω), and high output impedance (9.5 G Ω) from a low supply voltage (0.8 V). Monte Carlo simulation is also carried out, which proves the robust performance of the proposed circuit against mismatches. An application of the proposed current mirror is presented in the form of the current comparator to ensure the workability of the proposed BD-QFG current mirror.

A 1.1 μW biopotential amplifier based on bulk-driven quasi-floating gate technique with extremely low-value of offset voltage

Biopotential amplifier (BPA) remains one of the most crucial blocks for the successful implementation of any of the biomedical systems. However, design of a BPA remains challenging owing to most of the topologies reported in literature displaying high values of noise, consuming high value of power and working in limited range of bandwidth. Thus, circuit topologies capable of providing an optimum and an acceptable combination of these parameters remains a topic of immense interest among researchers. We in this paper, report the results of a BPA designed using Bulk-Driven Quasi-Floating Gate (BDQFG) technique with a special focus on the effect of variation in the values of biasing resistor (Rlarge). Results obtained through mathematical modelling and analysis of the circuit have been verified by conducting simulations in Cadence Analog Design Environment using standard 0.18 µm technology. Circuit design has been optimized for least values of power consumption of the order of 1.1 µW, noise (≈ 3.15 µVRMS), mid-band gain of 39.9 dB (from 0.266 Hz to f-3dB of 2.8 kHz), offset voltage of 455 μV and phase margin of 65.83°.

High-Precision Current Conveyor Based on BDQFG Miller Ota

The paper presents a sub-volt design of highly precise second-generation current conveyor (CCII  ) using Miller compensated Operational Transconductance Amplifier (OTA) designed using bulk driven quasi-floating gate (BDQFG) MOSFET. The bulk-driven approach help in working of proposed CCII  at low supply voltage. Moreover, followed BDQFG technique results in improves the transconductance and frequency response of the circuit over standalone bulk-driven technique. The proposed CCII  operates at  0.4V. Other performances which encourage its wide applicability are in terms of high current range and high bandwidth. The analysis of proposed current conveyor is carried in 0.18 m twin-well CMOS technology using HSpice.

Multiple-input bulk-driven quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits

This brief presents the first experimental results of the multiple-input bulk-driven quasi-floating-gate (MI-BD-QFG) MOS transistor (MOST) which is suitable for low-voltage (LV) low-power (LP) integrated circuits design. The MI-BD-QFG MOST is an extension to the principle of the bulk-driven quasi-floating-gate (BD-QFG) MOST. However, unlike the BD-QFG the MI-BD-QFG MOST offers multiple-input that simplifies specific CMOS topologies and reduce their power consumption. To confirm the advantages of the MI-BD-QFG MOST a Differential Difference Current Conveyor (DDCC) with very simple CMOS structure has been designed and fabricated in a standard n-well 0.18 µm CMOS process from TSMC with total chip area 350 µm × 78 µm. The fabricated circuit uses a 0.5 V power supply, consumes 1.7 µW power and offers near rail-to-rail input common mode range.

Fully‐balanced four‐terminal floating nullor for ultra‐low voltage analogue filter design

This study presents a new complementary metal–oxide–semiconductor (CMOS) structure for a fully balanced four-terminal floating nullor (FBFTFN) which is suitable for ultra-low-voltage and low-power applications. This structure employs a bulk-driven quasi-floating-gate (BD-QFG) metal–oxide–semiconductor transistor technique to provide the capability of ultra-low-voltage, low-power operations as well as extended input voltage range. The functionality of the proposed circuits is demonstrated through simulations using SPICE and TSMC 0.18 µm n-well CMOS technology with supply voltage of 0.5 V and dissipation power of 9.4 µW. To confirm the attractive features of the proposed circuit, the fully balanced filters such as band-pass Sallen–Key filter, voltage-mode universal biquadratic filter and current-mode sixth-order low-pass filter using proposed BD-QFG FBFTFN as active elements have been designed.

A Novel Design of Low-Voltage VDIBA and Filter Application

In this study, a low-voltage low-power design of previously introduced analog signal processing element called as Voltage Differencing Inverting Buffered Amplifier (VDIBA) is presented. Level shifter current mirrors are used in the circuit design in order to accomplish the low-voltage low-power operation. The configuration operates only with ±0.4 V supply voltages and consumes power 569 µW at the bias current 50 µA. Also, low-voltage transconductor which has highly linear g m is executed with the use of bulk-driven quasi-floating gate (BD-QFG) and source degeneration techniques. The simulations of the introduced circuit have been performed with 0.18 μm TSMC CMOS technology by SPICE. The theoretical approaches have been confirmed by the simulation results. DOI: http://dx.doi.org/10.5755/j01.eie.22.6.17224

A High Performance Bulk Driven Quasi Floating Gate MOSEFT Based Current Mirror

A high performance low voltage bulk driven quasi floating gate MOS based current mirror has been proposed. The combination of bulk driven and quasi FGMOS decreases the input impedance upto 120Ω which is four times smaller than current mirror based on only bulk driven technique. The bandwidth has also been improved upto 173MHz which is three folds of bandwidth of conventional bulk driven current mirror. Very high output impedance upto 1GΩ is achieved using self cascode technique in output section depending the value of factor m. Small signal analysis of proposed circuit verifies the simulated results. The circuit is simulated using 0.18μm CMOS technology with supply voltage of ±0.3V. The proposed current mirror is highly suitable for low voltage applications.

Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror

A low voltage self-biased high-swing cascode current mirror using bulk-driven quasi-floating gate MOSFET is proposed in this paper. The proposed current mirror bandwidth and especially the output impedance show a significant improvement compared to prior arts. The current mirror presented is designed using bulk-driven and bulk-driven quasi-floating gate N-channel MOS transistors, which helped it to operate at very low supply voltage of $${\pm }0.2\,\hbox {V}$$±0.2V. To achieve high output resistance, the current mirror uses regulated cascode stage followed by super cascode architecture. The small-signal analysis carried out proves the improvement achieved by proposed current mirror. The current mirror circuit operates well for input current ranging from 0 to $$250\,{\upmu }\mathrm{A}$$250μA with good linearity and shows the bandwidth of 285 MHz. The input and output resistances are found as $$240\,\Omega $$240Ω and $$19.5\,\hbox {G}\Omega $$19.5GΩ, respectively. Further, the THD analysis and Monte Carlo simulations carried prove the robustness of proposed current mirror. The complete analysis is done using HSpice on UMC $$0.18\,\upmu \mathrm{m}$$0.18μm technology.

Sub-Volt Fully Balanced Differential Difference Amplifier

This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

The experimental results of the bulk-driven quasi-floating-gate MOS transistor

This brief presents the experimental results of the new principle technique named bulk-driven quasi-floating-gate (BD-QFG) (Khateb and Khatib, 2013 [27]) MOS transistor (MOST) that was presented in AEU – International Journal of Electronics and Communications in year 2014. The BD-QFG MOST offers high transconductance value and extended common mode voltage range (CMVR) all under low-voltage supply (LV) low-power consumption (LP) conditions. Based on this technique a differential difference current conveyor (DDCC) was designed and fabricated in Cadence platform using 0.35μm CMOS AMIS process with total chip area 213μm×266μm. The voltage supply and the power consumption are ±500mV and 37μW, respectively. The experimental result shows near rail-to-rail common mode voltage range.

Ultra-Low-Voltage Low-Power Bulk-Driven Quasi-Floating-Gate Operational Transconductance Amplifier

A new ultra-low-voltage (LV) low-power (LP) bulk-driven quasi-floating-gate (BD-QFG) operational transconductance amplifier (OTA) is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW.

Comparative study of sub-volt differential difference current conveyors

Enhancing the performances of analog circuits with sub-volt supplies becomes a great challenge for circuit designers. Techniques such as bulk-driven (BD) and quasi-floating gate (QFG) count among the suitable ones for ultra-low voltage (ULV) operation capability with extended input voltage range and simple CMOS circuitry. However, in comparison to the conventional gate-driven (GD) MOS transistor (MOST), these techniques suffer from several disadvantages such as low transconductance value and bandwidth that limit their applicability for some applications. Therefore, the idea of merging the BD and QFG techniques to eliminate their drawbacks appears as efficacious solution. This new merging is named bulk-driven quasi-floating gate (BD-QFG)* technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-QFG techniques. The significant increment of the transconductance and the bandwidth values of the BD-QFG are clearly observed. The proposed CMOS structures of the DDCCs work at ±300mV supply voltage and 18.5µW power consumption. The simulation results using 0.18µm CMOS n-Well process from TSMC show the features of the proposed circuits.

Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design

In this paper, novel non-conventional techniques,11Note: In this paper the presented techniques are a national patent application registered by the Industrial Property Office in the Czech Republic under registration number 303698, for year 2013 [56]. named by the author of this paper “bulk-driven floating-gate (BD-FG)” MOS transistor (MOST) and “bulk-driven quasi-floating-gate (BD-QFG) MOST” for low-voltage (LV) low-power (LP) analog circuit design are presented. These novel techniques appear as a good solution to merge the advantages of floating-gate (FG) and quasi-floating-gate (QFG) with the advantages of bulk-driven (BD) technique and suppress their disadvantages. Consequently, the transconductance and transient frequency of BD-FG and BD-QFG MOSTs approach the conventional gate driven (GD) MOST values. Furthermore, a novel LV LP class AB second generation current conveyor based on BD-FG MOST is presented in this paper as an example. The supply voltage is only ±0.4V with a rail-to-rail voltage swing capability and total power consumption of mere 10μW. PSpice simulation results using the 0.18μm P-well CMOS technology are included to confirm the attractive properties of these new techniques.