Built-in Clock Research Articles

Low power delta sigma capacitor conversion circuit

To accurately measure the micro capacitance, a kind of capacitance conversion circuit that uses a second-order Sigma-Delta modulation technique is introduced, and the measuring range of inductive capacitance is extended by a 4-bit DAC capacitor. The loop oscillator is used to provide the modulator with a 16 kHz square wave signal. Because the circuit has a built-in clock generation circuit, no external clock signal is required outside the chip. Chopping technology is used to reduce the impact of 1/f noise on circuit performance. This capacitance conversion circuit is based on the SMIC 0.18um process, simulated and verified with cadence, MATLAB and other tools. The circuit achieves a capacitance range from 0 to 35pF and consumes 25μA from a 1.2V single supply. The conversion time for one measurement is 15ms, during which the resolution is 4fF and good linearity is achieved.

Low-power and high-precision SPAD array readout circuit based on built-in clock

Low-power and high-precision SPAD array readout circuit based on built-in clock

RTC Based Power Control System

This research proposes a technology-enhanced alternative to manual switching that is both user-friendly and safe. The ATMEGA328p-based time-controlled electrical device control system takes over the task of turning on and off electrical equipment according to time. It has a built-in real-time clock that tracks the current time. When the real time matches the planned time, the associated device is turned on or off according to the ON/OFF time. Using the rotary encoder, you may change the switching time at any moment. The LCD display shows the current time and the encoded. Keywords: RTC, ATmega328P, LCD, Relay, Rotary encoder, Power Controller.

Restoring circadian gene profiles in clock networks using synthetic feedback control

The circadian system—an organism’s built-in biological clock—is responsible for orchestrating biological processes to adapt to diurnal and seasonal variations. Perturbations to the circadian system (e.g., pathogen attack, sudden environmental change) often result in pathophysiological responses (e.g., jetlag in humans, stunted growth in plants, etc.) In view of this, synthetic biologists are progressively adapting the idea of employing synthetic feedback control circuits to alleviate the effects of perturbations on circadian systems. To facilitate the design of such controllers, suitable models are required. Here, we extend our recently developed model for the plant circadian clock—termed the extended S-System model—to model circadian systems across different kingdoms of life. We then use this modeling strategy to develop a design framework, based on an antithetic integral feedback (AIF) controller, to restore a gene’s circadian profile when it is subject to loss-of-function due to external perturbations. The use of the AIF controller is motivated by its recent successful experimental implementation. Our findings provide circadian biologists with a systematic and general modeling and design approach for implementing synthetic feedback control of circadian systems.

Design and FPGA implementation of a multirate Δ∑ time-to-digital converter with third-order noise-shaping

This paper presents a third-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC). An FPGA development board of Altera Stratix IV was used to implement the prototype of the proposed TDC. Multirating technique is employed in this work to improve the performance over conventional TDCs. Measured results demonstrate considerable influence of multirating technique on enhancing signal-to-noise ratio (SNR), from 50.68 dB in single-rate mode to 64.8 dB in multi-rate mode (a gain of 14.12 dB). Different sampling clocks and Gated Switched-Ring Oscillators (GSROs) operating frequencies are generated utilizing built-in clock circuitries of the FPGA board. Thus, no discrete sources are needed for measurement by the proposed TDC. Moreover, the proposed design yields low complexity and power consumption since it does not consist of any calibration block and loop. Experimental results of this work and comparing them with state-of-the art Δ∑ TDCs prove that the proposed 1-1-1 MASH TDC can be incorporated in accurate and fast applications such as biosensors and ADPLLs.

Design and Analysis of a Multirate 5-bit High-Order 52 fsrms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA

This paper describes FPGA implementation of a high-order continuous-time multi-stage noise-shaping (MASH) $\Delta \Sigma $ time-to-digital converter (TDC). The TDC is based on Gated Switched-Ring Oscillator (GSRO) and employs multirating technique to achieve improved performance over conventional $\Delta \Sigma $ TDCs. The proposed TDC has been implemented on an Altera Stratix IV FPGA development board. Dynamic and static tests were performed on the proposed design and experimental results demonstrate that it can perform its function without the need of calibration. The built-in clock circuitries of the FPGA board provides sampling clocks and operating frequencies of the GSROs. This work presents a 52 fsrms, 89.7 dB dynamic range and 0.18 ps time-resolution at 200 MHz, 800 MHz, 1600 MHz sampling rate at the first, second and third stage, respectively, which demonstrate that the proposed third-order TDC can play an important role in applications such as ADPLLs and range finders in which accuracy and speed are vital.

GNSS Spoofing Detection Using Static or Rotating Single-Antenna of a Static or Moving Victim

GNSS spoofing works as follows: the GNSS signal generator transmits a signal simulation of several satellites at the GNSS frequency. If the level of the simulated signal exceeds the signal strength of real satellites, the GNSS receiver will “capture” the fake signal and calculate the position based on it. All receivers that fall into the spoofing zone will calculate the same coordinates, while the receivers located in different places will have a slight mismatch in time. The interference can be done away with such interference that simulates the movement of the receiver along the path defined by the spoofer. Receiver of the GNSS signals determines the XYZT coordinates. Suppose that the receiver has a built-in clock, the accuracy of which is comparable to the accuracy of the clock of GNSS, i.e., in the framework of this paper, we abstract from the need for correction of T. For a ship, only the XY coordinates are significant, so we will focus only on the calculations of the XY coordinates, and the Z coordinate is used only to detect a spoofing. This paper proposes three methods of spoofing detection using a single antenna, including measuring the altitude of a victim, measuring the coordinates of a moving victim at two points on the route, and measuring the victim’s coordinates in two points of space using a rotating antenna.

Standardization of time management from the viewpoint of ME device time errors

To reduce the risk of medical accidents and litigation, it is required to perform management such that the built-in clocks of ME devices are always accurate. However, there are no laws and guidelines concerning time management of ME devices, and there is concern about the reliability and adequacy of medical manuals in our facility regarding this type of device.

Performance of IEEE 802.11’s Timing Advertisement Against <italic>Sync</italic>TSF for Wireless Clock Synchronization

The lack of provisioning of synchronized timing support from known timing standards in IEEE 802.11 wireless networks has been overcome in IEEE 802.11-2012 through the timing advertisement (TA) mechanism. The scheme, however, presents a synchronization architecture of a cascade of four clocks. It provides no information on how the external time will be synchronized with the built-in clock of the access point (AP) and when the timestamping is performed on the wireless link, which can lead to a loss in synchronization accuracy. To this end, this work analyzes the quantitative performance of the TA mechanism with a non-IEEE802.11 mechanism, Sync TSF, which also uses the same four clocks as in the TA mechanism and compares their performance with the help of simulations. Both schemes offer similar accuracy and precision if the offset corrections involved in both schemes are carried out properly. Nevertheless, Sync TSF is more flexible, as it can be easily implemented using commercial off-the-shelf hardware using only software support. For the implementation of TA mechanism, additional guidelines from the IEEE 802.11 Standard along with dedicated hardware support is required.

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology

This paper presents a fully-integrated chipset for 4×25 Gb/s transceiver gearbox along with laser driver and photo detector front-ends. The transceiver provides 10:4 multiplexing and 4:10 demultiplexing conversion, with built-in clock generation, equalization, and amplification. The optical front-ends are realized as 4-element arrays, presenting remarkable performance with commercial vertical-cavity surface-emitting lasers and photodiodes. Feedforward equalizers and continuous-time linear equalizers are employed to compensate for loss and distortion in both electrical and optical domains. Fabricated in 65 nm CMOS technology, these chips can be lumped together as a compact module with performance exceeding typical 100 GbE standards.

Design of a Switched-Capacitor DC-DC Converter With a Wide Input Voltage Range

A triple-mode step-up/step-down switched-capacitor DC-DC converter is proposed, and it can work with a wide input voltage range. There are three operational modes in the proposed converter: triple-step-up, double-step-up, and step-down modes. A built-in clock generator was designed to generate a constant switching frequency, independent of the input voltage. The proposed circuit was implemented by a 0.35-μm CMOS mixed-signal 2P4M 3.3/5 V polycide process with a die area of 1.56×1.47 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The output voltage is fixed at 3.3 V, while the input voltage range is 1.8-5 V. The maximal load current for a 1.8-V input voltage is 10 mA, while it increases to 30 mA when the input voltage is larger than 3 V.

A 2$\,\times\,$25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet

A 2 × 25-Gb/s receiver for 100-Gb Ethernet (100 GbE) has been implemented in 65-nm CMOS technology. A new regulation mechanism is applied to the limiting amplifier to minimize its gain and bandwidth variations. Two low-power full-rate CDRs (with a built-in clock generator) and a high-speed 2:5 DMUX circuit are integrated. Although only two channels are implemented, this receiver provides exactly the same operation as a four-channel one while dealing with independent channels. The prototype achieves bit error rate <;10-12 with 20-mVpp input sensitivity, consuming a total power of 510 mW from a 1.2-V supply.

BRISK: a portable and flexible distributed instrumentation system

Researchers and practitioners in the area of parallel and distributed computing have been lacking a portable, flexible and robust distributed instrumentation system. This paper presents the reference implementation of Baseline Reduced Instrumentation System Kernel (BRISK). BRISK was developed as a part of a realtime system instrumentation and performance visualization project. The design is based on a simple distributed instrumentation system model for flexibility and extensibility. The basic implementation poses minimalistic system requirements and achieves high performance. The paper also shows evaluations of BRISK on both basic and advanced configurations. The first evaluation emphasizes local, simple performance metrics; and the second highlights aggregate performance, built-in clock synchronization and dynamic on-line sorting. Copyright © 2000 John Wiley & Sons, Ltd.

A high-speed 32-channel CMOS VCSEL driver with built-in self-test and clock generation circuitry

This paper describes the design, electrical, and optical test results for a high-speed 32-channel CMOS vertical-cavity surface emitting laser (VCSEL) driver integrated circuits with built-in self-test and clock generation circuitry. The circuit design and silicon parts are available to the research community through the Consortium for Optical and Optoelectronic Technologies in Computing (CO-OP) and the Optoelectronics Industry Association (OIDA). This device is specifically targeted at users building VCSEL-based smart photonic system demonstrators. A ten-channel version of this driver chip is also available with the same functionality and performance.

Modernization of the MX-1321 mass-spectrometer: A new information system for GC/MS analysis

Abstract A new informatic system for the MX-1321 mass-spectrometer is described. The system includes a specialized station for acquisition and initial selection of data, and a PC AT computer. The main tasks of the system are cyclic scanning of spectra during GC/MS analysis, acquisition and conversion of data in real time to a mass spectrum (nominal mass-amplitude form) and saving data on a hard disc. The system, without any major modification, can be used to update other types of mass-spectrometers or be incorporated into measuring assemblies that feature high-frequency sampling from a few separate channels. Since the system has built-in clocks, it is especially suited to handling devices operating periodically.

How daylight affects reproduction in sheep

Seasonal patterns of reproduction in New Zealand sheep flocks arise primarily from the annual changes in daily photoperiod. Sheep detect these changes in lighting by means of a built-in biological clock and this information is relayed to the hypothalamic-gonadal axis via the pineal gland. The current level of understanding of the mechanisms which are involved in these processes is briefly reviewed.

A system-oriented 5 V NMOS LSI circuit for data acquisition and front-end digital control

A 5 V n-channel enhancement/depletion circuit performs 8 bit data acquisition with a 5 V analog input range. It provides front-end digital control with adjustable set point and hysteresis. A simple constant-slope converter was developed, which is calibrated for a given application by tuning the built-in clock oscillator and adjusting the only reference, analog ground. For temperature compensation, the oscillator and the current source track with temperature. Digital subtraction was implemented with a three-decade synchronous BCD up/down counter, which produces positive or negative readings by a reversal of the counter. The circuit has a multiplexed three-digit TTL compatible BCD output. The chip size is 13 mm/SUP 2/ and it consumes 150 mW.

Cresswell's Colleague TLM

In an illuminating criticism ([ 1] ) of an article of mine ([2]), Cresswell sketches the semantical views of a Traditional Logician known as TLM, whose final initial must I suppose stand for Montague, and who, it is claimed, also shares the outlook of David Lewis, David Kaplan, Dana Scott, and perhaps A. N. Prior. I agree that the views of TLM correspond reasonably well with those of Montague, though I think Prior's differ in certain respects; the others must speak for themselves. On evidence, it is likely that the views of TLM are a good representation of those of Cresswell. To motivate discussion, I should say that it seems to me that the project of a dialectical reduction of logic is an extremely interesting one, and one that someone ought to be working on. If we knew how to program a computer to speak English well enough to be able to take part in conversations with ordinary English users, not only language but also logic need have no further mysteries for us. But although such a machine would have to be capable of registering various features of its context, it would not need an accurate built-in clock or calendar, since humans do not. Consequently, logic should not need to make reference to real times and dates. It is of course already accepted by most logicians that logicality is consistent with faulty sense-organs, but the point apparently needs special argument for the case of time, which Kant thought was perceived by an internal sense. Naturally, the truth of a tensed statement such as It's Monday cannot be determined by someone who has no information about the time of its utterance. But truth, unlike necessary truth and logical relations such as incompatibility, is not a logical property and should enter logic at most hypothetically. Now when someone says It's raining today on 21st March 1973, a day which for short I shall refer to as day D, his

North Sky Guides Birds

> THE SMALL indigo bunting apparently steers his way 2,000 miles south every year by looking over its shoulder at the northern sky. This night-flying immigrant does not seem to rely on any one star or constellation for his direction, said Stephen T. Emlen of the University of Michigan. Rather he recognizes the entire pattern of stars within 35 degrees of the North Star, and can be confused only when that part of the sky is blocked. Mr. Emlen's experimental results, reported at the American Institute of Biological Sciences meeting, College Park, Md., diverged from most theories currently used to explain bird migrations. Birds supposedly find their direction from a single star or group of stars and then compensate for the time of night, Mr. Emlen said. In other words, they are thought to have a built-in clock for recognizing where the star should be at any one hour. However, in testing this theory under artificial planetarium skies, Mr. Emlen found he could not confuse the bunting by moving the stars ahead as much as six hours. They still oriented themselves south in the fall and north in the spring, despite the fact the constellations were far west of their normal positions. The birds were not much bothered by having the entire southern sky disappear even when they were headed in that direction. But when Mr. Emlen shut off the northern sky, the birds simply stopped orienting altogether and did nothing. Mr. Emlen then proceeded to find out whether the bunting depends for direction on any single cue, such as the Milky Way, the Big Dipper, Cassiopeia or the North Star. He was unsuccessful, which leads him to believe the birds must take their direction from the geometrical pattern formed by all these cues together. He also found that different birds take slightly different cues. Some were disoriented by one test, others by a second. However, the majority lost their direction when the circumpolar area was blocked. At the same session on animal perception, William Hermnkind of the University of Miami, Coral Gables, Fla., revealed that fiddler crabs have an optical system whereby they can measure polarized light in the sky and find their way from sea to shore. Polarized light is only one of three cues they use, but it is an important one, said Mr. Hermkind. The other two are the shore itself and the position of the sun. By putting the crabs in a pan of water and covering it with a polaroid filter, Mr. Herrnkind found he could make the crabs change direction according to the position of the filter.