Design and Analysis of a Multirate 5-bit High-Order 52 fsrms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA

Ahmad Mouri Zadeh Khaki,Sawal Hamid Md Ali,Ebrahim Farshidi,Masuri Othman,Karim Ansari Asl

doi:10.1109/access.2021.3111918

Abstract

This paper describes FPGA implementation of a high-order continuous-time multi-stage noise-shaping (MASH) $\Delta \Sigma $ time-to-digital converter (TDC). The TDC is based on Gated Switched-Ring Oscillator (GSRO) and employs multirating technique to achieve improved performance over conventional $\Delta \Sigma $ TDCs. The proposed TDC has been implemented on an Altera Stratix IV FPGA development board. Dynamic and static tests were performed on the proposed design and experimental results demonstrate that it can perform its function without the need of calibration. The built-in clock circuitries of the FPGA board provides sampling clocks and operating frequencies of the GSROs. This work presents a 52 fsrms, 89.7 dB dynamic range and 0.18 ps time-resolution at 200 MHz, 800 MHz, 1600 MHz sampling rate at the first, second and third stage, respectively, which demonstrate that the proposed third-order TDC can play an important role in applications such as ADPLLs and range finders in which accuracy and speed are vital.

Highlights

Measuring a time interval is a necessary step in various applications such as chemical sensors readout [1], biosensors [2], frequency synthesizers [3,4,5,6] and all-digital phase-locked loops (ADPLLs) [7] which is generally performed by time-todigital converters (TDCs)
These structures unable to achieve a remarkable performance due to oversampling ratio (OSR) and noise-shaping order limitation, and require calibration in most cases to compensate errors caused by disturbances such as frequency difference between stages which will consume higher power consumption and chip area on the system
In order to investigate the linearity of this work, we perform a static test to the proposed design where a ramp input are applied to the TDC

Summary

Introduction

Measuring a time interval is a necessary step in various applications such as chemical sensors readout [1], biosensors [2], frequency synthesizers [3,4,5,6] and all-digital phase-locked loops (ADPLLs) [7] which is generally performed by time-todigital converters (TDCs). Voltagedomain or time-domain ∆∑ TDCs benefiting from noiseshaping as an inherent property have become widely prevalent [15,16,17,18,19]. These structures unable to achieve a remarkable performance due to oversampling ratio (OSR) and noise-shaping order limitation, and require calibration in most cases to compensate errors caused by disturbances such as frequency difference between stages which will consume higher power consumption and chip area on the system. To enhance SNR a multirate FPGAbased second-order GSRO-TDC operating at higher sampling rates that achieves finer time-resolution has been proposed in [23]. The overall digital output of the TDC (DOUT) can be represented as: DOUT=z-1Y1 − (1 − z-1)Y2

Methods

Results

Conclusion