Oxide-trapped Charge Buildup Research Articles

Geometry Dependence of Total-Dose Effects in Bulk FinFETs

The total ionizing dose (TID) response of bulk FinFETs is investigated for various geometry variations, such as fin width, channel length, and fin pitch. The buildup of oxide-trapped charge in the shallow trench isolation turns on a parasitic transistor, leading to increased leakage current (higher IOFF.) The TID-induced degradation increases with decreasing fin width. Transistors with longer channels degrade less than those with shorter channels. Transistors with large fin pitch degrade more, compared to those with narrow fin pitch. TCAD simulations are used to analyze the buildup of trapped charge in the trench isolation oxide and its impact on the increase in leakage current. The strong influence of charge in the STI in narrow-fin transistors induces a parasitic leakage current path between the source and the drain, while in wide-fin devices, for the same amount of trapped charge in the isolation oxide, the subsurface leakage path is less effective.

Simulation of TID Effects in a High Voltage Ring Oscillator

Oscillation frequency of a high voltage ring oscillator is observed to change non-linearly with increasing dose. The change in oscillation is caused by buildup of oxide-trapped charge in both gate and isolation oxides post-radiation. A simulation methodology is described and implemented which successfully re-creates oscillator response by way of radiation-enabled simulation. Implementation of radiation-enabled simulation of ring oscillator is discussed. Simulation allows projection of oscillator response in-situ, allowing designers to anticipate changes in oscillation and implement radiation hardening as required. Alternatively, implementation of a ring oscillator as a reliability monitor in a large-scale circuit allows easily detectable observation of total dose effects on transistors.

Modeling Radiation-Induced Degradation in Top-Gated Epitaxial Graphene Field-Effect-Transistors (FETs)

This paper investigates total ionizing dose (TID) effects in top-gated epitaxial graphene field-effect-transistors (GFETs). Measurements reveal voltage shifts in the current-voltage (I-V) characteristics and degradation of carrier mobility and minimum conductivity, consistent with the buildup of oxide-trapped charges. A semi-empirical approach for modeling radiation-induced degradation in GFETs effective carrier mobility is described in the paper. The modeling approach describes Coulomb and short-range scattering based on calculations of charge and effective vertical field that incorporate radiation-induced oxide trapped charges. The transition from the dominant scattering mechanism is correctly described as a function of effective field and oxide trapped charge density. Comparison with experimental data results in good qualitative agreement when including an empirical component to account for scatterer transparency in the low field regime.

Effects of Moisture and Hydrogen Exposure on Radiation-Induced MOS Device Degradation and Its Implications for Long-Term Aging

Transistors and ICs built in several different captive and commercial facilities were exposed to moisture, irradiated, and annealed. The moisture exposures were performed using highly accelerated stress test (HAST) at 130degC and 85% relative humidity. Irradiation of n-channel transistors exposed to HAST followed by a long-term anneal resulted in some increase in interface-trap and oxide-trapped charge buildup. However, exposing p-channel transistors to HAST preirradiation resulted in extremely large and unexpected voltage shifts immediately following irradiation. They were observed for devices with either doped oxide or nitride final chip passivation. Because of this, nitride passivation may not be sufficient to prevent H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O from causing enhanced radiation-induced degradation over long time periods in some devices (e.g., commercial devices with nitride final chip passivation packaged in plastic packages). The smaller voltage shifts for the n-channel transistors may be related to the formation of phosphosilicate glass (PSG) overlying the sources and drains of the n-channel transistors impeding the diffusion of moisture to the gate oxides. It is shown that, the large radiation-induced voltage shifts for the p-channel transistors can lead to enhanced IC parametric degradation and functional failure at lower radiation levels. Large increases in radiation-induced field oxide leakage current were also observed for transistors exposed to HAST preirradiation. Transistors were also annealed (prior to irradiation) and irradiated in H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Approximately the same level of radiation-induced degradation was observed for n- and p-channel transistors suggesting that the diffusion kinetics for H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> diffusion are considerably different than for H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O diffusion. These results raise the concern that exposure of devices to moisture or hydrogen can lead to long-term radiation-induced aging effects.

Enhanced TID Susceptibility in Sub-100 nm Bulk CMOS I/O Transistors and Circuits

This paper evaluates the radiation responses of 2.5 V I/O transistors and regular-threshold MOSFETs from a 90 nm commercial bulk CMOS technology. The data obtained from Co ionizing radiation experiments indicate enhanced TID susceptibility in I/O devices and circuits, which is attributed to the p-type body doping. A quantitative model is used to analyze the effects of doping and oxide trapped charge buildup along the sidewall of the shallow trench isolation oxide. These effects are captured in the general electrostatic equation for surface potential, which can be correlated to off-state leakage current. Device simulations are used in concert with experimental measurements and the analytical model to provide physical insight into the radiation response of each device type.

Electrical stressing effects in commercial power VDMOSFETs

The effects of DC gate bias stressing on threshold voltage and channel carrier mobility in commercial power VDMOSFETs from two different manufacturers are studied. Underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. Apart from certain quantitative differences, it is shown that gate bias stressing has qualitatively the same effects and causes significant threshold voltage shift and mobility degradation in both VDMOS devices. Negative gate bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger after stressing by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon ≡Si•o defects into the oxide conduction band and subsequent hole tunnelling from the charged oxide traps ≡Sio+ to interface-trap precursors ≡Sis–H are proposed to be the main mechanisms responsible for build-up of positive oxide-trapped charge and interface traps, respectively. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects ≡Sio••Sio≡ is shown to be responsible for build-up of oxide-trapped charge, and subsequent electro-chemical reactions of interfacial precursors ≡Sis–H with charged oxide traps ≡Sio+•Sio≡ and H+ ions for that of interface traps.

Effects of electrical stressing in power VDMOSFETs☆

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon Sio defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps Sio+ to interface-trap precursors Sis–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects SioSio is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Sis–H with the charged oxide traps Sio+Sio and H+ ions are proposed to be responsible for interface trap buildup.

Effects of electrical stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon Si o defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps Si o + to interface-trap precursors Si s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects Si o Si o is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si s–H with the charged oxide traps Si o + Si o and H + ions are proposed to be responsible for interface trap buildup.

Effects of gate bias stressing in power vdmosfets

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analyzed in terms of the mechanisms responsible. In the case of positive bias stressing, electron tunneling from neutral oxide traps associated with trivalent silicon ?Sio defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunneling from the charged oxide traps ?Sio+ to interface-trap precursors ?Sis-H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunneling from the silicon valence band to oxygen vacancy defects ?Sio / Sio? is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors ?Sis?? with the charged oxide traps ?Sio+ Sio? and H+ ions are proposed to be responsible for interface trap buildup.

Effects of burn-in stressing on radiation response of power VDMOSFETs

The effects of pre-irradiation burn-in stressing on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift in stressed, and more considerable mobility reduction in unstressed devices have been observed, confirming the necessity of performing the radiation qualification testing after the reliability screening of power MOSFETs. The underlying changes of gate oxide-trapped charge and interface trap densities have been calculated and analysed in terms of the mechanisms responsible for pre-irradiation stress effects. The buildup of oxide-trapped charge appeared to be almost independent of device pre-irradiation stress, while the buildup of interface traps was somewhat less pronounced in stressed devices. Passivation of interface-trap precursors due to diffusion of hydrogen related species (originating either from package inside or gate oxide adjacent structures) from the bulk of the oxide towards the interface has been proposed as a mechanism responsible for the suppressed interface-trap buildup in pre-irradiation stressed devices.

A pseudo-two-dimensional model of an n-channel MOSFET under the influence of ionizing radiation

A pseudo-two-dimensional model has been developed for determining the radiation-induced changes in the characteristics of an n-channel metal-oxide-semiconductor-field-effect transistor (MOSFET) during exposure to ionizing radiation as well as in the post-irradiated condition. The ionizing radiation-induced excess carriers in the semiconductor as well as changes in the interface states and build-up of oxide-trapped charges at Si–SiO2 interface have been incorporated in the basic model equations for analysing the device under exposure to ionizing radiation. A model has been proposed that can examine the behaviour of the device during exposure to ionizing radiation. This model enables one to determine the ID–VD and transfer characteristics of the device by considering the field-dependent mobility of the surface channel in the unirradiated condition, during exposure to ionizing radiation as well as in post-irradiated condition. The results obtained on the basis of the model in the irradiated as well as post-irradiated condition have been compared and contrasted with available experimental and simulated results.

Effects of irradiation temperature on MOS radiation response

Effects of irradiation and annealing temperature on radiation-induced charge trapping are explored for MOS transistors. Transistors were irradiated with 10-keV x rays at temperatures from -25 to 100/spl deg/C and annealed at 100/spl deg/C for times up to 3.6/spl times/10/sup 6/ s. Transistor data were analyzed for the contributions of radiation-induced charge due to oxide traps, border traps, and interface traps. Increased irradiation temperature resulted in increased interface-trap and border-trap buildup and decreased oxide-trapped charge buildup during irradiation. Interface-trap buildup immediately following irradiation for transistors irradiated at 100/spl deg/C was equivalent to the buildup of interface traps in transistors irradiated at 27/spl deg/C and annealed for one week at 100/spl deg/C (standard rebound test). For the p-channel transistors, a one-to-one correlation was observed between the increase in interface-trap charge and the decrease in oxide-trapped charge during irradiation. This may imply a link between increased interface-trap buildup and the annealing of oxide-trapped charge in these devices. The observed data can be explained in terms of increased hydrogen ion transport rates to the Si/SiO/sub 2/ interface during elevated temperature irradiations. These results have implications on hardness assurance testing and potentially may be used to reduce costs associated with rebound qualification.

The Response of MOS Devices to Dose-Enhanced Low-Energy Radiation

A series of experiments has been performed to investigate the response of MOS structures to low-energy radiation. A 10-keV x-ray source was used to irradiate MOS capacitors through a gold/aluminum bilaminate. As expected, the device response when the gold side of the bilaminate faces the device is enhanced strongly with respect to its response when the aluminum side of the bilaminate faces the device. The degree to which the enhanced radiation affects the device response, as determined by the buildup of oxidetrapped charge, depends on the thickness of the gate insulator and the thickness of the capacitor gate in ways similar to those expected from previous work. In addition, striking dependences of the enhanced device response on the energy of the incident radiation, and on the magnitude and direction of the electric field across the gate insulator during the irradiation were observed. These results may provide new insights into the details of the interaction of low-energy radiation with MOS devices.