Build-up Layer Research Articles

Experimentally determined and Monte Carlo–calculated energy dependence of NaCl pellets read by optically stimulated luminescence for photon beams in the energy range 30 keV to 1.25 MeV

Ordinary salt, NaCl, has many properties suitable for dosimetry and has been suggested for both retrospective and prospective optically stimulated luminescence (OSL) dosimetry. Lately, the focus has been on NaCl that is compressed into solid pellets, as this improves both its handling and dosimetric properties. In this project, the energy dependence of NaCl pellets produced in-house was investigated for photon energies between 30 and 1.25 MeV. The NaCl pellets were first exposed to free-in-air conditions, and the estimated absorbed dose to the NaCl pellets was compared to the air kerma, K air, at the point of exposure. Second, a backscatter medium of polymethyl methacrylate (PMMA) was added, and NaCl pellets were exposed when positioned on a ISO slab phantom to relate the response in the NaCl to the personal dose equivalent, H p(10). The results show a significant energy dependence for exposure to low-energy photons with a peak over-response compared to K air and H p(10) of up to 18. Comparisons with Monte Carlo simulations show good agreement, even though the simulations cannot account for properties related to the intrinsic luminescence effects of the NaCl pellets or the readout and calibration process. The finite thickness of the NaCl pellet makes it an imperfect Bragg-Grey cavity, which complicates the behaviour of the energy dependence. The results presented here may serve as an important basis for further experimental and theoretical modelling of a build-up layer and filters in efforts to develop a passive personal dosemeter based on NaCl.

Influence of wire-arc additive manufacturing path planning strategy on the residual stress status in one single buildup layer

In recent years, the significant residual stress in the wire-arc additively manufactured components has been continuously one of the most concerning issues for the further development of the wire-arc additive manufacturing (WAAM) technology. Although many pre/post processing methods have been proved capable of modifying the residual stress, few works have been conducted to reduce the residual stress using appropriate path planning. In the present research, a WAAM path planning strategy is developed combining both zigzag and contour-offset methods, which aims to obtain a single WAAM deposition buildup layer with both optimal outline accuracy and residual stress status. The path planning and residual stress measurement processes have been carefully designed to acquire reasonable results. According to the residual stress results measured using X-ray diffraction method, the arc deposits finished with more contour-offset paths contain smaller tensile residual stresses, which is due to the hooping function of the outer contour deposit path to the inner deposit. Therefore, it can be concluded that the offsetting of the external contours before zigzag filling the internal dimensions is beneficial to both the residual stress distribution and shape outline accuracy of the WAAM buildup layer.

Heterogeneous System-In-Package (HSIP) Technology

Abstract A stitched test vehicle has been designed using molded wafer technology to characterize the assembly yield and reliability of a 4-layered topside Buildup (BU) and 4 layered bottom side BU package. In this design, the individual module uses 20 1mm square Si die elements, and one 10mmm square Si die and 8 through substrate vias (TSVs) arrayed on a 14mm square module size to produce a Reliability Test Vehicle (RTV) using Fan-out Wafer-Level (FOWL) technology. 17 individual RTV modules are molded on a 100mm wafer to create a reconstituted wafer. On the 1mm square Si die are two dog bone structures that allows for the design of a stitched net for each build layer with the embedded Si die. Therefore one can generate a stitched net between the first BU layer with the embedded Si die, the second BU layer with the embedded die layer, and so on. The layered stitched design feature, allows one to characterize the integrity of the individual BU layers during the sequential BU processing of the layers on both sides of the molded core. The TSVs allow for signal communication between the top 4 BU layers with the 4 backside BU layers. On top of each 4th layer is a ball grid array (BGA) pad on a 0.8mm pitch that can be used to stack this module using conventional soldering methods. This approach to embed die in a molded wafer and then BU layers on each side is referred to as Heterogeneous System-in-Package (HSIP) technology. Another feature to be included in this work is the use of Current Induced Thermal Cycle (CITC) testing. This is a fast and accurate test method developed by i3 Electronics in Endicott, NY to assess the reliability of vias in a BU package. It is widely used in the industry for circuit boards and build up organic substrates, and is now be applied to the finer via dimension (25um diameter) used for HSIP technology. As was discussed above for the RTV design, the same BU and TSV features will be tested in this CITC module design. The BU layers are exactly the same as that used in the above RTV design. For this wafer build, the die will be molded to create a reconstituted wafer. The first goal is to develop a molding process that has less than 20um die shift and produces a molded substrate with the acceptable amount of bow to accommodate the topside build up layers. For each BU layer, the assembly yield can be characterized by probing the stitched nets for the first, second, and so on BU layers for both sides. This data will provide assembly yield. The individual RTV and CITC modules can then be diced from the wafer, solder balls are attached to the topside BGA pads, and then tested using a conventional clam shell socket test fixture. The first set of reliability tests will be thermal cycling and temperature humidity. In this paper we will discuss the challenges with building HSIP modules, their yield and the first phase of reliability testing.

Hardfacing of metal-cutting tools by arc welding in vacuum

Purpose: To present a technology for hardfacing of metal-cutting tools by arc welding in vacuum. Design/methodology/approach: The experiments were carried out using an installation for arc welding in vacuum. Objects of research were metal cutting tools (lathe knives), made of high-speed steel HS6-5-2 on a base metal of structural steel C45. The structure, hardness and wear resistance after hardfacing and after a triple tempering at 560°C have been determined. The heat resistance of the obtained instruments has been examined. Findings: The microstructural analysis showed that the structure of the built-up layer consisted of martensite, retained austenite and carbides. This was confirmed by the values of measured hardness after welding which were about 63-64 HRC. The triple tempering led to an increase in hardness by 3-4 HRC. It was found that the built-up layers (cutting edges of tools) retain their hardness (HRC=63-65) up to a temperature of 615-620°C, which shows that the heat resistance of the build-up layers was similar to that of the hardened and tempered tools of the same steel. The built-up work-pieces (excluding heat treated) and the reference knife showed the same cutting qualities at cutting speeds in the range of 55 to 120 m/min. It has been found that triple tempering after hardfacing led to increased wear resistance and consequently the durability of the tool also increased due to the higher hardness. Practical implications: The practical application is related to the production of metalcutting tools. Originality/value: The proposed technological method allows to produce defects free built-up layers. The cutting properties of the built-up in vacuum layers are comparable to or better than those of new tools made of steel HS 6-5-2.

Low-Loss Impedance-Matched Sub-25-μm Vias in 3-D Millimeter-Wave Packages

This article presents, for the first time, low-loss small microvias in build-up layers for the next-generation highdensity high-performance fifth-generation (5G) millimeter-wave (mm-wave) antenna-integrated packages. As the operating frequency increases, the signal losses in antenna packages become more critical and need to be mitigated to obtain desired performance in beamforming and massive multi-input multioutput. As electrical wavelengths in mm-wave spectra are short, the signal losses caused by microvias dominate the loss budget. To minimize the signal losses and identify the required microvia diameter in build-up layers, this article first focuses on the modeling of small microvias for impedance matching. Based on the models and simulated characteristic impedance, test vehicles with daisy chains are fabricated in build-up layers on a core package substrate. Ultraviolet (UV) laser is utilized to drill microvias, and targeted microvia diameters are obtained through a semiadditive patterning process. High-frequency measurements are also performed to correlate with the models and simulated results in the 28-GHz band. The characterization results exhibit good model-to-hardware correlation and indicate that small microvias (20 μm) provide impedance closer to 50 Ω compared with the larger microvias. This matched microvia impedance lowers reflection and insertion loss, resulting in a 10% reduction in the signal losses caused by microvias in the 5G New-Radio n257 band around 28 GHz.

Depositing Al-Based Metallic Coatings onto Polymer Substrates by Cold Spray

The feasibility of depositing aluminum onto thermoplastic substrates via cold spray (CS) was investigated. Dense coatings of 7075 Al and CP Al (commercial purity) were achieved on three substrates—polyetheretherketone (PEEK), polyetherimide (PEI), and acrylonitrile butadiene styrene (ABS) using an iterative optimization process. 7075 Al deposition yielded low deposition efficiencies (DEs) and low thicknesses but high adhesive strengths, while CP Al deposition led to high DEs and thicknesses but relatively low adhesive strengths. PEEK and PEI were more suitable substrates for cold spray than ABS, which suffered from surface erosion and substrate distortion. Two key factors were identified that influenced the DE and adhesive strength of the coating. The first factor was the bond layer, the initial few particle layers that fused with the substrate to allow subsequent buildup. The bond layer was influenced by the substrate hardness, yield strength, glass transition temperature, and impact strength, as well as the differences in thermal expansion coefficients of Al and the polymer substrates. The second factor was the CS process parameters selected, as the bond layer and the build-up layers may require different process conditions in order to optimize both bonding strength and coating strength, respectively.

Experimental Study of Wear Mechanisms of Cemented Carbide in the Turning of Ti6Al4V.

Titanium and titanium alloys such as Ti-6Al-4V are generally considered as difficult-to-machine materials. This is mainly due to their high chemical reactivity, poor thermal conductivity, and high strength, which is maintained at elevated temperatures. As a result, the cutting tool is exposed to rather extreme contact conditions resulting in plastic deformation and wear. In the present work, the mechanisms behind the crater and flank wear of uncoated cemented carbide inserts in the turning of Ti6Al4V are characterized using high-resolution scanning electron microscopy (SEM), energy-dispersive X-ray spectroscopy (EDS), and high-resolution Auger electron spectroscopy (AES).The results show that, for combinations of low cutting speeds and feeds, crater and flank wear were found to be controlled by an attrition wear mechanism, while for combinations of medium to high cutting speeds and feeds, a diffusion wear mechanism was found to control the wear. For the latter combinations, high-resolution SEM and AES analysis reveal the formation of an approximately 100 nm thick carbon-depleted tungsten carbide (WC)-layer at the cemented carbide/Ti6Al4V interface due to the diffusion of carbon into the adhered build-up layers of work material on the rake and flank surfaces.

Modeling the primary source intensity distribution: reconstruction and inter-comparison of six Varian TrueBeam sources

The primary source size is one of the most important beam model parameters in small photon fields. In this work we apply a recently suggested reconstruction technique to characterize the primary source of 6 Varian TrueBeam (TB) linacs. A series of photon fluence profile measurements were performed on 6 Varian TB linacs in the crossplane and inplane orientation using radiochromic film in air and a 2 mm Pb foil as a build-up layer. An image reconstruction algorithm was then applied, based on the maximum likelihood expectation-maximization (MLEM) algorithm, to estimate the source distribution. The method iteratively ray-traces photons from the source plane to the measurement plane to extract source profile corrections. The technique was first benchmarked using a Monte Carlo (MC) model of a Varian TrueBeam with known input Gaussian source sizes. The robustness of the suggested technique was also tested by randomly sampling different combinations of source and field size values and repeating the reconstruction. At the MC benchmarking stage the MLEM reconstruction algorithm was capable of reproducing the Gaussian shape with a RMSE less than 4.0%, while the reconstructed source size (FWHM) and field size were determined with an accuracy level of 0.14 mm and 0.10 mm respectively. Experimentally, the reconstructed TB sources presented FWHM values between 1.02–1.5 mm (–0.18 mm) and 1.08–1.42 mm (–0.13 mm) in the crossplane and inplane orientations respectively. All TB sources studied in this work can be considered symmetric within uncertainties with the exception of one. The source distribution presented systematic deviations from a Gaussian distribution mostly in the lower tail region. Multi-parameter functional forms, such as Pearson VII or double Gaussian presented improvements in modeling the source in this region, but increase the model complexity. The reconstructed sources measured in this work can serve as reference values for commissioning beam models in small fields and set upper and lower thresholds values of the expected source size for a TB linac.

Characteristics of Alloying and Structure Formation of Wear-Resistant Coatings Carboborite

Modern hardfacing methods for machine parts using alloying systems Cr-Mn, Cr-B, Cr-Ni, Cr-W-V based on iron have pushed their functionality to the limit and cannot satisfy the increasing demands of modern machinery, because alloys based on these systems form build-up layers with restricted content of alloying elements: chromium 30-40%; titanium 4-5%; tungsten 18-25%; manganese up to 15%. Cladding materials with such content of alloying elements do not exert due effect for details experiencing severe abrasion working in aggressive media, under high temperatures. During alloying the best effect is obtained when not one but several alloying elements influencing the properties are added, they form an advantageous structure. The authors have developed new cladding compositions with refractory components TiC, (Ti,Cr)B2, B4C, FeV. Laboratory testing of their mechanical properties have proved high efficiency of the studied cladding materials. High resistance to wear is reasoned by a favourable combination of strong cementing austenitic- martensitic matrix and formation of complex carboborides strongly fixed in that matrix. The base of the strengthening phase is a strong and wear-resisting carboboride ((TiB2Fc,Cr,Ti)23(C,B)6); plastic borides CrB2 and TiB2 are present in the structure of the build-up layer, too. Thus, the peculiarities and laws of build-up layers formation suggest that due to high properties and quality refractory compositions are an intense source for creation of new highly efficient classing materials with unique physical and technical properties.

Processing Through Glass Via (TGV) Interposers

For the next generation of 3D-IC applications, glass offers many desirable properties that make it an ideal interposer. In order to realize these applications, it becomes necessary to be able to deposit a Cu layer on both surfaces as well as in the glass via. In this paper we will present results of interposers that have fine line circuitry on both sides of the glass and have through glass vias (TGVs). One major challenge is how to create a TGV using either electrically conductive adhesives (ECAs) or Cu plating methods to achieve a high conductivity and reliable via connection. Most work to date uses ECA materials to fill the TGV, however, many of these ECA materials have limitations in that they cannot withstand temperatures in excess of 400°C, are not hermetic and do not have the electrical properties of bulk Cu. In the first phase of our work, we have evaluated different commercially available ECA materials to fill the glass vias. A major challenge in using these materials is how to effectively fill the vias. Our test vehicle has a TGV with dimensions of 50um diameter and a 300um thickness on 2″ × 2″ glass substrate. A positive pressure screen printing process was used to fill the vias. These ECA materials exhibited a very high viscosity, due to the high Cu metal filler content, which made them very difficult to fill. Different pressures, squeegee speeds, and standoff conditions were evaluated to arrive at an optimized process to effectively fill the glass vias. A tilted X-ray inspection approach was used to characterize the yield for ECA hole fill. A DOE of different sintering conditions was conducted to determine how to maximize the electrically conductivity of the paste. From this work we will show the impact of sintering conditions on electrical conductivity and hermeticity. In parallel, we have developed a process to Cu plate a TGV. In this approach, a dry deposition process was used to produce a conductive seed layer in the via having a diameter of 100um and a total substrate thickness of 300um. We proceeded to use a Cu electroplating process to plate up a conformal Cu layer in the glass via. In this work we have pattern plated circuitry on both surfaces along with the via to produce a glass interposer. In addition, we were able to deposit a very thin layer of Si3N4 between two thick Cu metal layers on the topside of a glass interposer to produce a capacitor. The success of plating a TGV also enables the formation of inductors in a glass substrate. An organic dielectric layer using an Ajinomoto Buildup Film (ABF) was used to create a single buildup layer on the glass interposer. The combination of these individual technologies allows the capability to manufacture a glass interposer for advanced packaging applications. A discussion of the challenges associated in building glass interposers will be presented, which will include examples of recent builds of a double-sided Cu circuitry glass interposer and a diplexer module having Cu MIM (metal-insulator-metal) capacitors and inductors for RF applications.

First Demonstration of Compact, Ultra-Thin Low-Pass and Bandpass Filters for 5G Small-Cell Applications

Package-integrated and ultra-thin low-pass filter (LPF) and bandpass filter (BPF) with footprint smaller than $0.5\lambda _{0}\times 0.5\lambda _{0}\times 0.025\lambda _{0}$ at the operating frequencies of 28- and 39-GHz bands are presented for 5G and mm-wave small-cell application. Such package integration of 5G filters with ultrashort 3-D interconnects allows for low interconnect losses that are similar to that of on-chip filters, but low component insertion loss of off-chip discrete filters. These thin-film filters exhibit a cross-sectional height of $188.5~\mu \text{m}$ and can be utilized either as embedded components or integrated passive devices in module packages. Three topologies of LPF and BPF in total are modeled, designed, and fabricated on precision thin-film buildup layers on glass substrate as a core. Large-area panel-compatible semiadditive patterning (SAP) process is utilized to form high-precision topologies to aid the low-cost fabrication of ultraminiaturized filters. SAP also enables the realization of ultra-thin traces to precisely model high-impedance inductive lines compared to conventional subtractive etching and printing techniques. This results in filters with low insertion loss, low VSWR, and high selectivity. The simulated and measured results of filters show an excellent correlation.

Mechanical Properties of Build-Up Layers on Failed Ceramic Roller

The paper describes degradation process of ceramic rollers. Rollers behavior under mechanical and thermal load was evaluated using available methods like XRD, instrumented hardness measurement and compressive strength. The influence of residual stresses was also discussed. The first phase during the degradation crystalize from amorphous silica tridymite, cristobalite and quartz, then due to the contact and pressure of the steel strip to the surface roller iron diffuses and forms fayalite. Measured values of compression strength of roller of 55-61 MPa agree with producer documentation declared minimal values. Hardness and Young´s modulus of buildup phases identified from surface into depth were determined. Wüstite was present up to 100 mm, with hardness 6±1 GPa, Young´s modulus 75±6 GPa, fayalite, cristobalite, up to 500 mm, with hardness 5.4±0.6 GPa, Young´s modulus 51±2 GPa, tridymite over 500 mm, with the hardness 7±4 GPa and Young´s modulus 58±25 GPa.

Non-destructive DRIFT spectroscopy measurement of the degree of curing of industrial epoxy/silica composite buildup layers

The degree of curing of epoxy composites and coatings is one key parameter to control the reliability of manufacturing processes, particularly in printed circuit board (PCB) manufacturing where epoxy buildup composites are partially cured before processing. We show that the reaction of curing of an industrially relevant buildup composite (epoxy-phenol reinforced with silica fillers) can be monitored by diffuse reflectance infrared Fourier transform (DRIFT) in the near-infrared range. The accuracy of DRIFT measurements is confirmed by comparison with measurements in transmission mode on reference composite samples. DRIFT is demonstrated to offer an easy and reliable measurement of the epoxy degree of curing on PCB coupons.

IBM POWER9 package technology and design

The first-level package that contains the IBM POWER9 processor chip is designed to achieve the high computational performance needed for cognitive systems in a cost-effective design. The throughput data bandwidth of the POWER9 package for high-end scale-up systems is more than 1 TB/s, which is double the data bandwidth of the previous generation. This increase in bandwidth is achieved by introducing a dielectric with a loss tangent of 40% of the predecessor material, a C4 density increase of 15%, higher number of stacked vias to reduce jogging, and improved via pattern and placement to increase the frequency and density of signals. The cloud platform scale-out POWER9 package leverages the high-end and cognitive platform package attributes to maintain signal frequency while introducing novel chip-package-system co-design techniques. These design techniques were used to produce a well-balanced two-socket entry-level package with four build-up layers above and below the core, instead of six, resulting in a significant cost reduction from the previous generation while supporting the signal frequencies of POWER9. POWER9 systems are the first to offer 16-Gb/s PCIe Gen4 and 25.8-Gb/s open coherent accelerator processor interface that interconnect the processor to the I/O, networking, and accelerators required for systems in the cognitive computing era. In this paper, we present the material and wiring technology needed to achieve the signal performance up to 25.8 Gb/s per channel, the package physical attributes, and the chip-package-system co-design methodology to achieve the increased signal density, minimize the crosstalk, and maximize the frequency while reusing the package form factors of the previous generation, IBM POWER8.

Miniaturized and high-performance RF packages with ultra-thin glass substrates

Advanced RF packages are demonstrate with active (low-noise amplifier, RF switch) and passive integration in ultra-thin 3D glass packages with miniaturization and enhanced performance. The novelty of this RF packages is three-fold: 1) Ultra-thin 100 μm glass, 2) Double-side thinfilm RF circuits interconnected with Through-Package Vias (TPVs), and 3) Direct assembly of the glass-core package to the board with Land Grid Array (LGA) connections. An innovative double-via process, starting from prefabricated vias in bare glass, polymer filling and via drilling, is utilized for a robust and high-yield substrate fabrication process. Scalable and low-cost panel laminate processes are utilized to form the RF circuits on the build-up layers. The performance benefits are demonstrated through interconnect loss, impedance match, electrical gain and noise figure measurements. Compared to existing RF substrates, the glass substrates show 2.5X miniaturization in substrate thickness with extensibility to thinner substrates.

Frictional and wear performance of TiAlN/TiN coated tool against high-strength steel

The sliding friction and high-speed turning experiments were carried out in dry conditions to reveal the anti-friction characteristics and wear mechanisms of the TiAlN/TiN coated tool against high-strength steel. The friction coefficient was collected and wear rate was calculated in the sliding tests, while the value of flank wear width was measured in the turning tests. The microstructure and composition of the worn surfaces were observed by an ESEM and an EDX, respectively. During the sliding wear process, the friction coefficient showed an upward trend with the increase of applied load, while it showed a downward trend with the increase of sliding speed. With the changes of the sliding speed and applied load, the wear volume and wear rate of the coating showed the opposite trend. The combined action of the peeling off, chipping, adhesion, mechanical scratch, element diffusion and oxidation was the dominate wear mechanisms of the TiAlN/TiN coated tool in sliding and turning process. Furthermore, the build-up layer and oxide films formed on the worn surface can prevent the direct contact of the friction pair, which played a positive role in lubrication and anti-friction.

Analysis of the dynamic chip formation process in turning

Any surface orthogonal indentation into a metal structure with friction leads to a deformation in the interface between indenter and material. Transferring this observation to turning and taking the cutting velocities vc and vchip into account results in a stagnation point in the chip formation process. The friction behaviour depends on the velocities vc and vchip and under standard conditions leads to a build-up edge (BUE), build-up layer (BUL) and a self-blockading effect. Any variation of velocities vc and vchip changes the position of the aforementioned stagnation point and consequently the position of the BUE. This is demonstrated regarding a non-steady cutting process during the first revolution of the workpiece, where no chip formation occurs. Based on this, the external and internal friction during the chip formation process is analysed. A very good correspondence between analytical and experimental results, as well as between the existing external friction between tool and material and the internal friction, are observed. Furthermore, this result helps to create a new dynamic model based on mathematical–physical relations involving strain hardening, dynamic body forces, and deformation as a result of plastic strain rate with internal and external friction. For the case of turning C45 steel (material number 1.0503) at vc=5 m/min, not only the movement of particle flow producing flank and crater wear is shown, but also the dynamic movement of the BUE with the corresponding frequency and strain hardening with decreasing strain rate is developed and mathematically described by a regression function. In addition, as a result of strain rate and friction, the temperature in the chip formation zone is estimated. Finally, the self-blockading effect of the cutting process is demonstrated considering internal friction, metal deformation, dynamic body forces, and temperatures. Experiments show a high degree of conformity between analytical and experimental results.

Sensitivity of Liquation Cracking to Deposition Parameters and Residual Stresses in Laser Deposited IN718 Alloy

The laser deposited IN718 alloys were fabricated with laser cladding system under different conditions to estimate the sensitivity of weld metal liquation cracking. The microstructure and the crack characterization of the laser deposited IN718 alloy were investigated, and the effect of metallurgical factors and residual stress on the crack sensitivity was analyzed. The results showed that the continuous dendritic Laves was precipitated and formed a Lave–austenite interface with ambiguous nanohardness distribution. The weld metal liquation cracking was propagated along the laser scanning direction and the buildup direction in the laser deposited IN718 alloy simultaneously, and the Nb-/Mo-riched fine granular clusters were formed in the crack surface. The precipitation amount of the coarse eutectic phases, presented as dendrite or network, was increased in the laser deposited alloy fabricated with IN718/C-Fe-Cr composite powder and slow cooling rate. The total crack length and the maximum crack length were decreased by increasing cooling rate, and the transverse residual stress was increased with increasing buildup layer number. The crack sensitivity of the laser deposited IN718 alloy was increased by the crack initiation provided by the metallurgical defects and the eutectic phases with low melting temperatures, and then, crack propagated along the continuous phase under the transverse residual stress.

Miniaturized Bandpass Filters as Ultrathin 3-D IPDs and Embedded Thinfilms in 3-D Glass Modules

This paper presents the modeling, design, fabrication, and characterization of an innovative and miniaturized thin-film bandpass filter with coupled spiral structures in ultrathin glass substrates (30– $100~\mu \text{m}$ ). This filter is demonstrated for two applications: 3-D integrated passive devices and embedded thinfilm filters in RF modules. A compact filter design was achieved through an integrated resonant structure that effectively utilizes the inductive and capacitive coupling between metal layers on either side of an ultrathin glass substrate or organic build-up layer. The designed filters (layout area $150~\mu \text{m}$ device thickness) were fabricated on a 30- $\mu \text{m}$ -thin glass substrate using a panel-based low-cost approach with double-side thin-film wiring processes. The effect of process variations on the performance of the proposed structures was also studied. Furthermore, an improved WLAN filter is designed and demonstrated by employing specific structural modifications. The measured frequency response of the filters shows good model-to-hardware correlation, with very low insertion loss (0.6 dB) in the passband, and high adjacent-band rejection (>25 dB).

Ultraminiaturized Three-Dimensional IPAC Packages With 100 μm Thick Glass Substrates for Radio Frequency Front-End Modules

This paper presents innovative compact three-dimensional integrated passive and active components (3D IPAC) packages with ultrathin glass substrates for radio frequency (RF) long-term evolution (LTE) front-end modules (FEMs). High component density was achieved through double-side integration of substrate-embedded passives for impedance matching networks and three-dimensional (3D) double-side assembly of filters onto glass substrates. Glass with 100 μm thickness formed the core of the package, while four build-up layers with 15 μm thickness each were used to embed passives and form redistribution layers (RDLs). Advanced panel-scale double-side assembly processes were developed with low-cost mass reflow. Board-level assembly was realized with paste-printed solder balls and reflow on printed circuit board (PCB) with no intermediate substrates. Electrical performance of filters with substrate-embedded impedance matching networks was characterized and compared to simulations.