Bufferless Routing Research Articles

Retraction notice: Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA

Retraction notice: Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA

Approximate Priority Hybrid 3DNoC Buffered-Bufferless Router

This paper introduces a novel 3D NoC router that combines buffered and bufferless routing with approximate priority comparison when deflecting flits. Our proposal is a modification of an asymmetrical router that is buffered in the z dimension ports and bufferless in the x and y dimension ports. Flits that request output ports in the x and y dimensions are granted or deflected based on approximate, instead of accurate, priority comparison. Experimental results show that the proposed router, in addition to effectively combining the advantages of both buffered and bufferless routers, achieves additional performance and area gains due to the reduced logic required for approximate priority comparison in flit deflections. Experimental results using synthetic and realistic traffic show that the proposed router begins to saturate at a significantly higher injection rate than a bufferless router, but at a slightly lower injection rate than when using accurate priority comparison. Furthermore, the proposed router achieves higher clock frequencies and a reduced area compared to bufferles routers due to the simpler permutation network. The increased routing efficiency is shown to also translate to energy gains.

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA

PurposeThe small area network for data communication within routers is suffering from storage of packet, throughput, latency and power consumption. There are a lot of solutions to increase speed of commutation and optimization of power consumption; one among them is Network-on-chip (NoC). In the literature, there are several NoCs which can reconfigurable dynamically and can easily test and validate the results on FPGA. But still, NoCs have limitations which are regarding chip area, reconfigurable time and throughput.Design/methodology/approachTo address these limitations, this research proposes the dynamically buffered and bufferless reconfigurable NoC (DB2R NoC) using X-Y algorithm for routing, Torus for switching and Flexible Direction Order (FDOR) for direction finding between source and destination nodes. Thus, the 3 × 3 and 4 × 4 DB2R NoCs are made free from deadlock, low power and latency and high throughput. To prove the applicability and performance analysis of DB2R NoC for 3 × 3 and 4 × 4 routers on FPGA, the 22 bits for buffered and 19 bit for bufferless designs have been successfully synthesized using Verilog HDL and implemented on Artix-7 FPGA development bond. The virtual input/output chips cope pro tool has been incorporated in the design to verify and debug the complete design on Artix-7 FPGA.FindingsIn the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.Originality/valueIn the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.

Design and implementation of asynchronous NOC architecture with buffer-less router

In present days, development in chip technology enables us to incorporate heterogonous cores on one chip. Synchronization and communication between such diverse cores is a major issue. Current Synchronous NOC architecture with buffered router consumes a substantial chip area and Power (clock distribution & I/O buffers). Hence in recent times Buffer-less routers based on Deflective routing are projected as a possible solution, but they suffers from issues like sequential port allocation and slow critical path and also increases the Latency. In this paper we propose 2D 4x4 Asynchronous Mesh NOC architecture with a novel router design using XY routing algorithm. In the proposed router design, we have eliminated the conventional input and output buffers and crossbar switch. We integrated priority encoder and FSM based Arbiter which efficiently solves long critical path issues of conventional Buffer less router by dynamically changing the port priority and hence solves the starvation and Live/Dead lock issue and improves the Area Consumption (i.e., reduced by ≈ 43%). We have used parallel transmission which enables us to improve Speed (by ≈73%) and elimination of I/O buffers reduces the power consumption (≈ 0.56w).

Evaluation of Bufferless Network-On-Chip with Parallel Port Allocator

Multicore network-on-chip when scales upto hundred of nodes, energy consumption, design complexity and cost increases multifold owing to structure of interconnect. Many researches are being conducted to design novel architecture to build efficient networks-on-chips. Our paper proposes efficient bufferless design with deflection containment technique to eliminate buffers and latency. The high cost of buffers motivate us to go for bufferless design, however with increasing network loads, it become notorious with multiple deflection and flit loss between nodes. To overcome this, we have designed a bufferless architecture with local bypass ring within nodes to reduce deflection and packet loss. Deflection Containment with the use of local bypass ring shortens critical path and improves performance. Architecture of our designed bufferless NoC is analysed and RTL implementation of its components is done with Xillinx ISE design suite and its working is analysed in Modelsim SE. Our evaluation proves that bufferless routing with deflection containment technique reduces power dissipation without compromising on its performance.

Ant Lion Optimized Bufferless Routing in the Design of Low Power Application Specific Network on Chip

Network on chip is widely restricted with power utilization and area occupation due to the usage of buffers. Hence, the design of bufferless architecture entirely eliminates such kind of limitations. However, conventional methodologies will not provide low-power design with enhanced features by means of operational frequency and area. This work introduces an optimization algorithm along with bufferless routing in chip design. Ant lion optimized (ALO) routing topology in bufferless router achieves very less power. Power dissipation of ALO-bufferless technique is evaluated with conventional topologies, such as spin, octagon and cliche. Xilinx ISE design suite 14.5 is used for the purpose of design and validation of the planned work, and it is compared with fault-tolerant deflection routing and hierarchical FTDR in terms of throughput and fault rate. ALO-based bufferless routing achieves operational frequency of 780.153 MHz with 0.413 mW power consumption; while ant lion optimized buffered routing achieves operational frequency of 426.995 MHz and 0.750 mW for speed and power, respectively.

An Approximate Bufferless Network-on-Chip

Bufferless network-on-chip (NoC) designs have drawn research attention in massively parallel multicore systems via their significant benefits in power and area savings. However, it shows poor throughput and low bandwidth in current bufferless designs due to complex bufferless routing and arbitration. Especially in the NACK-based bufferless network, the network performance will be affected significantly as the network conflicts increased caused by packet retransmissions. To this end, we proposed a novel approximate bufferless network, ABNoC. ABNoC lessens network conflicts and packet retransmissions via an approximate allocation mechanism (AAM) and a packet approximation method. We show that, compared with SCARAB, ABNoC improved the bandwidth up to 1.92 times and achieved 1.2 times faster in runtime. Besides, ABNoC accomplished 83.6% retransmission reduction and 46.7% latency reduction, while maintaining low application error.

Energy‐efficient fault tolerant technique for deflection routers in two‐dimensional mesh Network‐on‐Chips

New generation multi-processor system-on-chips integrate hundreds of processing elements in a single chip which communicate with each other through on-chip communication networks, commonly known as network-on-chip (NoC). Routers are the most critical NoC components and deflection routing is a technique used in buffer-less routers for better energy efficiency. Massive integration of devices along with fabrication at deep sub-micron level feature sizes increases the possibility of wear out and damage to various components resulting in unreliable operation of the chip. Hence NoC fabric in general and routers, in particular, should be equipped with built-in fault tolerance mechanisms to ensure the reliability of the chip in the presence of faults. The authors propose an energy-efficient routing technique that can tolerate permanent faults in NoC links by introducing a simple logic unit placed next to the output port allocation stage of the deflection router pipeline. This technique incurs minimum wiring overheads and promises a stable network throughput for high fault rates. Evaluation of the proposed method on 8 × 8 mesh NoC for various fault rates reports reduced flit deflection rate and hop power which brings about a significant reduction in dynamic power consumption at the inter-router links compared to state-of-the-art fault tolerance techniques.

GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC

Recently, there has been enormous attention given to the network on chip (NoC) because it is scalable compared to the communication bus. Three dimensional (3D) NoC is getting more popular due to the reduction of wire length with that off two dimensional NoC. The router in the NoC is provides communication between the different computational units. In this paper, a two-phase bundled-data handshake latch is used with an asynchronous router. The Mousetrap latch controller forms the basis of this asynchronous router. The major part of the arbiter is to schedule the packet, then deliver to its destination without any loss of the packet. This paper proposes a novel asynchronous 3D lottery routing algorithm which is based on arbitral mechanism. The Lottery routing algorithm distinguishes the different priorities of the input port and makes sure that it responses to the higher priority port. The proposed hardware is implemented using Cadence 180 nm technology. The result shows that the power reduction is about 17% and a slight increase in area and delay of about 2% with respect to synchronous 3D NoC.

Randomly prioritized buffer-less routing architecture for 3D Network on Chip

Recently, 3D NoC has become more important than 2D NoC due its new geometrical arrangement and also reduces the wire length from global interconnect to local interconnect. One of the main components to implement 3D NoC is the router. The components of the router are crossbar, FIFO, and arbiter. The scheduling algorithm is the main part of the arbiter which schedules and delivers all packets to the destination nodes without any loss of packets. Packets that have the highest priority are served first,the remaning highest priority packets ares queued in the priority register and non-priority packets are served after all priority packets are served. Round Robin routing algorithm is commonly used as the scheduling algorithm in most of the routers. This paper proposes a novel 3D lottery routing algorithm which is based on arbitral mechanism like randomly prioritized buffer. Communication among the IPs in NoC can be customized by users through the lottery router. The lottery routing algorithm distinguishes the different priorities of the input port and makes sure that it responses to the higher priority port. The efficient hardware implementation of 3D NoC is proposed using Xilinx Spartan 3E FPGA, the result shows that the proposed architecture consumes 1644 slices out of 4656 slices and operates at the maximum frequency of about 103.602MHz. The 3D NoC is modeled and implemented with a Cadence Electronic Design Automation tool and the results show that the power consumption of 3D NoC is reduced by 9% compared to a single layer.

Impact of deflection history based priority on adaptive deflection router for mesh NoCs

Network on chip (NoC) has been proposed over bus to address the communicational prerequisite of highly dense multi-core systems. NoCs with buffer-less routers gain popularity due to simplicity in the router design, low power consumption and less chip area. The state of the art of deflection router DeBAR employs side buffers instead of input port buffers, that can accommodate one among the deflected flit per router per cycle. In this paper we propose deflection history as a priority metrics for flit selection. We, modify the primitive DeBAR design, and propose priority based deflection based adaptive router (PBDeBAR) that make use of a cost effective priority scheme to choose a flit that has to be moved to the side buffer. Experimental results shows that PBDeBAR reduces latency, deflection rate, buffer occupancy and link usage with respect to the existing minimally buffered deflection routers.

Impact of Deflection History based Priority on Adaptive Deflection Router for Mesh NoCs

Network on chip (NoC) has been proposed over bus to address the communicational prerequisite of highly dense multi-core systems. NoCs with buffer-less routers gain popularity due to simplicity in the router design, low power consumption and less chip area. The state of the art of deflection router DeBAR employs side buffers instead of input port buffers, that can accommodate one among the deflected flit per router per cycle. In this paper we propose deflection history as a priority metrics for flit selection. We, modify the primitive DeBAR design, and propose priority based deflection based adaptive router (PBDeBAR) that make use of a cost effective priority scheme to choose a flit that has to be moved to the side buffer. Experimental results shows that PBDeBAR reduces latency, deflection rate, buffer occupancy and link usage with respect to the existing minimally buffered deflection routers.

A load balancing bufferless deflection router for network-on-chip**Project supported by the National Natural Science Foundation of China (Nos. 61474087, 61322405, 61376039).

The bufferless router emerges as an interesting option for cost-efficient in network-on-chip (NoC) design. However, the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases. In this paper, we propose a load balancing bufferless deflection router (LBBDR) for NoC that relieves the effect of deflection in bufferless NoC. The proposed LBBDR employs a balance toggle identifier in the source router to control the initial routing direction of X or Y for a flit in the network. Based on this mechanism, the flit is routed according to XY or YX routing in the network afterward. When two or more flits contend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention. Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate, average packet latency and throughput by up to 13%, 10% and 6% respectively. The layout area and power consumption compared with the reported schemes are 12% and 7% less respectively.

DualBLESS: Bufferless Router with Dual Ejection Ports for 2D and 3D NoC

In this paper, the authors proposed a 1-cycle bufferless router with dual ejection ports (which is also called DualBLESS) for 2D and 3D Network-on-Chip. The router uses a simple route computer module, a MUX module instead of the Flit Ejector module and a MUX module in a baseline bufferless router to achieve high performance. Simulation results under six synthetic workloads illustrate that the two proposed DualBLESS routers achieve less average packet latency and higher throughput than the baseline 2D and 3D bufferless routers.

Exploring Heterogeneous NoC Design Space in Heterogeneous GPU-CPU Architectures

Computer architecture is transiting from the multicore era into the heterogeneous era in which heterogeneous architectures use on-chip networks to access shared resources and how a network is configured will likely have a significant impact on overall performance and power consumption. Recently, heterogeneous network on chip (NoC) has been proposed not only to achieve performance comparable to that of the NoCs with buffered routers but also to reduce buffer cost and energy consumption. However, heterogeneous NoC design for heterogeneous GPU-CPU architectures has not been studied in depth. This paper first evaluates the performance and power consumption of a variety of static hot-potato based heterogeneous NoCs with different buffered and bufferless router placements, which is helpful to explore the design space for heterogeneous GPU-CPU interconnection. Then it proposes Unidirectional Flow Control (UFC), a simple credit-based flow control mechanism for heterogeneous NoC in GPU-CPU architectures to control network congestion. UFC can guarantee that there are always unoccupied entries in buffered routers to receive flits coming from adjacent bufferless routers. Our evaluations show that when compared to hot-potato routing, UFC improves performance by an average of 14.1% with energy increased by an average of 5.3% only.

Express Ring: a multi-layer and non-blocking NoC architecture

As the Network-on-Chip (NoC) induces significant hardware overheads, it becomes the performance and scalability bottleneck of System-on-Chip (SoC) design. To address this challenge, we propose a multi-layer, non-blocking ring NoC architecture. Multi-layer links with different bandwidth achieve high link utilization and avoid protocol-level deadlock. The non-blocking architecture leverages bufferless router to reduce hardware overheads and simplifies router pipeline to reduce zero-load latency. We also propose a scalable global signal control mechanism to eliminate the starvation and avoid the loss of packets. Compared with the conventional ring network composed of dateline routers (DRing) and Intel Nehalem-EX ring network (NRing), our design achieves 69.4% and 12.3% performance improvements, respectively. Compared with DRing, it also reduces hardware overheads.

Bufferless Routing in Optical Gaussian Macrochip Interconnect

The ever increasing intra-chip and inter-chip traffic load in computing systems has been pushing traditional electronic interconnects to their limit in communication bandwidth, latency, and energy consumption. In order to achieve the high bandwidth and low latency required by intra-chip and inter-chip communications and mitigate the high interconnect power dissipation, optical interconnects have been considered as a promising candidate for intra-chip and inter-chip interconnections in next generation computing systems. In addition, packet switching is an efficient switching paradigm to fully utilize the communication bandwidth. However, due to lack of random access optical memory, it is challenging to implement all-optical packet switching in optical interconnects. In this paper, we exploit bufferless routing, a special type of packet-switching, to overcome the problem of lack of random access optical buffer. More specifically, we study bufferless routing in a novel optical multichip system, called Gaussian macrochip, where embedded chips are interconnected by an optical Gaussian network. By taking advantage of the underlying Hamiltonian cycles in the Gaussian network, we design a bufferless routing algorithm for the Gaussian macrochip, which routes packets along the shortest path in the absence of deflection, and guarantees that deflected packets reach their destinations within ${{N}}$ hops. Our extensive simulation results demonstrate that by adopting the proposed routing algorithm, Gaussian macrochip can support much higher inter-chip communication bandwidth, has much shorter average packet delay, and is more power efficient than the previously proposed architectures for optical multichip systems.

A survey on energy-efficient methodologies and architectures of network-on-chip

Integration of large number of electronic components on a single chip has resulted in complete and complex systems on a single chip. The energy efficiency in the System-on-Chip (SoC) and its communication subset, the Network-on-Chip (NoC), is a key challenge, due to the fact that these systems are typically battery-powered. We present a survey that provides a broad picture of the state-of-the-art energy-efficient NoC architectures and techniques, such as the routing algorithms, buffered and bufferless router architectures, fault tolerance, switching techniques, voltage islands, and voltage-frequency scaling. The objective of the survey is to educate the readers with the latest design-improvements that are carried out in reducing the power consumption in the NoCs.

LDBR: Low-deflection bufferless router for cost-sensitive network-on-chip design

In network-on-chip (NoC) designs, the bufferless router is more energy-efficient than the conventional router with buffers. However, in the bufferless network, deflections cause great performance loss. In this paper, three deflection models are firstly constructed for analyzing the causes of deflections. Then, we propose a low-deflection bufferless router (LDBR), in which a multi-channel network interface and a novel deflection routing based on turn model are designed for reducing the deflections during packet transmissions. Finally, LDBR is evaluated against the latest bufferless routers using synthetic and real-world traffic patterns. The experimental results exhibit that the deflection rate of LDBR network is reduced by 41% compared to other bufferless networks, and LDBR also shows superiority in cost and power consumption across all workloads.