Required Buffer Size Research Articles

DEVELOPMENT OF A MODIFIED METHOD OF NETWORK TRAFFIC FORMING

Based on the analysis of the statistical characteristics of heterogeneous network traffic of "Quadruple Play" mobile subscribers, it is shown that it cannot be represented by Poisson or Erlang distributions. It is shown that for such similar traffic, the rate of growth of the required buffer volume increases as the Hurst parameter increases. A method of adaptive traffic formation using the control of the length of intervals of the intensity of the arrival of data packets has been developed. Congestion management is carried out by changing the frequency of the marker generator (GM) on the basis of the results of forecasting the required bandwidth of the system and the required buffer size. The shaper adapts to changes in the length and instantaneous intensity of packet input in real-time.

Novel Mode Selection Schemes for Buffer-Aided Cooperative NOMA System

This paper investigates a cooperative non-orthogonal multiple access (C-NOMA) system, where the NOMA and buffer-aided cooperative transmission modes between the users are integrated. Two novel mode selection schemes are proposed, which adaptively select the NOMA and cooperative modes according to different buffer states and communication environments. These two proposed schemes are termed single-core state (SCS) and dual-core state (DCS) schemes since they correspond to single and dual-core buffer states. These core states are carefully chosen, which ensure not only a sufficient amount of available transmission modes or links but also a small number of stored packets at each buffer. The closed-form expressions of the outage probabilities and average delays of the proposed schemes are derived and verified by simulation results. Asymptotic performance analysis is also performed, revealing that both proposed schemes achieve the full diversity within the minimum required buffer size of two. Analytical and simulation results show that the proposed SCS and DCS schemes ensure favourable outage performance and the lowest delay, respectively.

Fuzzy-Based Relay Node Selection with the Buffer Cleaning Technique for Delay-Tolerant Networks

Delay-tolerant networks allow communication using store-carry-forward technique between source and destination nodes where no end-to-end connectivity exists. In case of network disconnection, messages get stored in a node and wait till the connection is restored, which could be forwarded to another node. To explore the possibility of improvement, many researchers have applied protocol based on fuzzy in DTN, but none of them proposed any solution for the situation where the node density is very low. This situation may result in low buffer availability. Hence, the nodes become unavailable for forwarding messages due to low buffer availability. In general, the remote area does not have a dense network thus, required buffer size might not be available at all the nodes for enabling communication. In this paper, we proposed a solution for the scenario where nodes cannot accept any message due to the unavailability of storage. To make communication possible, we formulated a methodology to search for the best node available in the communication range for relaying the message. The selected node is tested for buffer availability. As per negative result, it is subjected to buffer cleaning and then used for sending a message to that node. If the result is positive, the message will be sent directly to the relay node. A Fuzzy logic system is used for relay node selection and buffer cleaning process. ONE simulator has been adopted for simulating the environment and the simulation results indicate that the proposed technique enhanced the network's performance.

Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric

The development of the space–air–ground integration has put higher demands on satellite network. It needs to support high-bandwidth, large-capacity and various quality of service guarantees. However, the satellite onboard switching is facing the problem of resource constraints and special requirements of hardware complexity and scheduling efficiency. For this, this paper proposes a novel memory architecture for high-bandwidth onboard switching fabric. To reduce hardware complexity, multiplexer is used in the input side to merge k input ports into one internal bus, while the output demultiplexer splits an internal bus into k output links. Shared memory architecture is adopted in the input module to improve the memory efficiency, and a buffered crossbar is used to interconnect the input modules to the output modules. A discrete-time queuing model is formulated, and an iterative approach is used to quantitatively analyze the performance of the proposed architecture. The throughput and delay are calculated under different switch size, input load, and buffer capacity. The numerical results can serve as a guidance on deciding the required buffer size and appropriate speedup ratio. This work is validated by both simulations and FPGA implementations. Synthesize result show that using the state-of-the-art Xilinx VU13P FPGA, a switching fabric with 48 ports can be implemented and the peak throughput of the proposed architecture can reach 480 Gbps. Compared with existing combined input-crosspoint queuing, the proposed architecture can significantly reduce the packet delay and the memory resource cost.

Efficient Processing of Sparse Tensor Decomposition via Unified Abstraction and PE-Interactive Architecture

We propose a novel architecture to efficiently perform sparse tensor decomposition/completion. As the generalization of vectors and matrices, tensors are widely used to process high-dimensional data. Sparse tensor decomposition (SpTD) is not only an emerging tensor analysis technique but also an effective tool to reduce the storage and computation costs of tensors. However, conventional general-purpose processors are inefficient to perform SpTD, mainly due to: i) variable sparsity degree and flexible buffer size requirement; ii) difficulties of fusing multiple execution kernels to pursue better performance. For domain-specific accelerator designers on the other hand, the diversity of decomposition algorithms is also an important problem that must be considered. To solve these challenges, we propose a unified abstraction for SpTD algorithms and design a specialized accelerator. First, we formulate two types of core kernels (SpLrMM and LrSampling) that serve as a standard form to fit a broad range of SpTD algorithms. Second, we design a sparse tensor engine (STE) to efficiently perform SpTD. STE uses a processing element (PE)-interactive architecture where PEs can be flexibly grouped together via Network-on-Chip (NoC) to share the buffer capacity, bandwidth, and compute resources. We evaluate our accelerator with extensive experiments, and it can achieve an average speedup of 45× over CPU and 29× over GPU.

BS-HTIS: Buffer Sizing for Heterogeneous Traffic and Integrated System

Buffer sizing for switching and routing devices is of significance for guaranteeing the Quality of Service (QoS) of critical services on the Internet of Things (IoT), continuously evolving scheduling mechanisms and complex traffic characteristics pose new challenges for the traditional method of static buffer sizing based on rule-of-thumb. In this paper, the scope of buffer sizing is extended from a basic scheduling system under homogeneous arrival traffic input to an integrated scheduling system under heterogeneous arrival traffic input which is more ubiquitous. In this context, Voices, videos and other heterogeneous data in the IoT are categorized into short-range-dependent (SRD) and long-range-dependent (LRD) traffic, and the integrated scheduling system is decomposed into single-server-single-queue (SSSQ) systems by not only decoupling the complex dependencies among heterogeneous traffic inputs but also taking the impact of SRD and LRD traffic burstiness on the buffer sizing into account. On this basis, expressions for the relation between the minimum buffer size and the maximum overflow probability are presented. The numerical analysis results and simulation analysis results reveal that the average arrival rate, traffic burst level and scheduling priority are positively correlated with the required buffer size, and once the overflow probability is set, the minimum buffer size can be determined correspondingly. The achievements of this paper will provide theoretical guidance for IoT manufacturers and technicians to set buffers more reasonably and use resources more efficiently.

Presynaptic Spike-Driven Spike Timing-Dependent Plasticity With Address Event Representation for Large-Scale Neuromorphic Systems

Learning plays an important role in the brain to make it adaptive to dynamical environments. This paper presents a presynaptic spike-driven spike timing-dependent plasticity (STDP) learning rule in the address domain for a neuromorphic architecture using a synaptic connectivity table in an external memory at a local routing node. We contribute two aspects to the implementation of the learning rule for extended large-scale neuromorphic systems. First, we reduced buffer sizes required for tracing a spike train which is required to pair all presynaptic and postsynaptic spike for an STDP time window. This method implements an exponential decay STDP function with two parameters: the latest timestamp and the synaptic modification rate at the latest timestamp. It reduces the required buffer size compared to previous works. Second, we resolve a lack of reverse lookup table issue with the presynaptic spike-driven algorithm. The proposed algorithm holds causal updates at postsynaptic spikes until a next presynaptic spike arrival. This approach removes the need of a reverse lookup table required at a postsynaptic spike. We show the implementation of the proposed algorithm in an FPGA device and validate it with a spiking neural network configuration. The experiment results show the proposed algorithm is comparable qualitatively with a conventional STDP learning rule.

Recycling Cellular Energy for Self-Sustainable IoT Networks: A Spatiotemporal Study

This paper investigates the self-sustainability of an overlay Internet of Things (IoT) network that relies on harvesting energy from a downlink cellular network. Using stochastic geometry and queueing theory, we develop a spatiotemporal model to derive the steady state distribution of the number of packets in the buffers and energy levels in the batteries of IoT devices given that the IoT and cellular communications are allocated disjoint spectrum. Particularly, each IoT device is modelled via a two-dimensional discrete-time Markov Chain (DTMC) that jointly tracks the evolution of the data buffer and energy battery. In this context, stochastic geometry is used to derive the energy generation at the batteries and the packet transmission success probability from buffers taking into account the mutual interference from other active IoT devices. To this end, we show the Pareto-Frontiers of the sustainability region, which define the network parameters that ensure stable network operation and finite packet delay. Furthermore, the spatially averaged network performance, in terms of transmission success probability, average queueing delay, and average queue size are investigated. For self-sustainable networks, the results quantify the required buffer size and packet delay, which are crucial for the design of IoT devices and time critical IoT applications.

Implementing lean paradigm in an Indian foundry facility: a case study

This article seeks to establish the effectiveness of lean manufacturing in eliminating the hidden wastes, maintaining better inventory control and reducing the total production time. A large Indian foundry facility is utilised to illustrate the adopted approach. Firstly, current state mapping is prepared to have the knowledge of the existing procedure followed in the production of castings. In addition, relevant data such as, cycle time, changeover time, percentage of defects, percentage downtime and inventory in between the processes are collected for each process. Further, the future state map is created, after amending the entire process, by adopting the methodology proposed by Rother and Shook (1999). Additionally, the required buffer size (number of Kanbans) at each stage and the sequence of production are also estimated by adopting the method advocated by the Smalley (2004). Finally, improvement is accounted in terms of reduced lead time of the process.

Buffer Size Evaluation of OpenFlow Systems in Software-Defined Networks

In this paper, we address the problem of minimum buffer size evaluation of an OpenFlow system in software-defined networks (SDNs), while ensuring optimum packet waiting time. The problem is important, as OpenFlow is one of the popular southbound application programing interfaces, which enables controller–switch interaction. The related existing literature addresses schemes on enhancement and packet flow in an OpenFlow system. However, there is a need to analyze the optimum buffer size of an OpenFlow switch, for ensuring the quality-of-service of SDNs. In this paper, we propose an analytical scheme for buffer bound evaluation of an OpenFlow system, named OPUS. Additionally, we propose a queuing scheme for an OpenFlow system—C-M/M/1/K/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\infty$</tex-math></inline-formula> queuing model—based on the OpenFlow specification version 1.5.0. Further, we calculate the minimum buffer size requirement of an OpenFlow switch, theoretically. Simulation-based analysis exhibits that with two times increase in packet processing rate, the packet arrival rate can be increased by 26.15– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{30.4}\%$</tex-math></inline-formula> . We infer that for an OpenFlow system, the minimum buffer size is 0.75 million packets with the maximum packet arrival and the minimum processing rate of 0.20–0.25 million packets per second (mpps) and 0.03–0.35 mpps, respectively, and the maximum packet waiting time is 0.173–0.249 s.

Low-Complexity Energy-Efficient Power Allocation With Buffer Constraint in HSR Communications

In this paper, we investigate the energy-efficient power allocation for downlink distributed antenna system (DAS) with buffer size constraint in high-speed railway (HSR) scenarios. We design the power allocation at different times for HSR communications, utilizing the characteristics of fixed moving path of trains. A key issue we discuss is the matching problem between the data arrival process and instantaneous wireless transmission process under the buffer size constraint. We formulate the energy-efficient power allocation problem with the requirement of buffer size as a non-convex optimization problem. By a parameterized transformation and an iterative algorithm, we derive the optimal solution at different time phases. Then, to reduce complexity of the multiple iterations, we present a low-complexity algorithm by analyzing the feasible region of the optimal solution. Simulation results demonstrate that the proposed power allocation schemes can achieve the optimal energy efficiency (EE) and avoid data overflow. Moreover, with a smaller number of iterations, the low-complexity algorithm can achieve the same EE performance as the optimal algorithm based on the bisection method.

Mobile Data Gathering With Bounded Relay in Wireless Sensor Networks

Sensing data gathering is an important and fundamental issue in the Internet of Things. However, for battery-powered sensors, energy depletion is unavoidable. Using mobile sinks to collect sensing data by one-hop transmission is an effective way to prolong the lifetime of wireless sensor networks but will inevitably cause an excessive long delay time of data gathering. In order to reduce the delay time of mobile data gathering, it is necessary to incorporate multihop transmission into mobile data gathering. In this paper, a new mobile data gathering algorithm with multihop transmission is proposed to reduce the delay time of data gathering. The proposed algorithm is called the bounded relay combine-TSP-reduce (BR-CTR). The BR-CTR algorithm visits the convergence area of sensors’ communication ranges to reduce the number of visiting points. The BR-CTR algorithm is integrated with a path adjustment mechanism, which can further shorten the planned traveling path effectively. In performance evaluation, we compare the BR-CTR algorithm not only with the existing mobile data gathering algorithms with one-hop transmission but also with the existing mobile data gathering algorithms with multihop transmission in terms of the length of traveling path, delay time, network lifetime, and buffer size requirement. Experimental results indicate that the proposed algorithm has high performance on all the above-mentioned indices.

The influence of spare parts provisioning on buffer size in a production system

ABSTRACTWe consider a discrete-part production line consisting of two machines with random processing and failure times. One option that can mitigate the effect of these uncertainties is the installation of a buffer between the two machines to avoid starving and blocking of the machines. In this article, we additionally allow the keeping of spare parts in stock to enable a fast repair and reduce machine downtime. We introduce a new model to support the optimization of the buffer size and the spare parts inventory level simultaneously. The model is based on a continuous-time Markov chain and our aim is to minimize the average costs, which are composed of costs for work in process and the stock-keeping of spare parts, subject to a minimum target throughput. Our numerical analysis reveals that the availability of spare parts can increase throughput enormously or reduce the required buffer size for a given target throughput. Using our approach, as opposed to a sequential approach, we can quantify the cost savings, which can be obtained by a joint optimization of the buffer size and the inventory level. Large cost savings can be obtained by the application of our new approach.

Designing a lean storage allocation policy for non-uniform unit loads in a forward-reserve model

PurposeThe contemporary e-tailing marketplace insists that distribution centers are playing the roles of both wholesalers and retailers which require different storage-handling load sizes due to different product variants. To fulfill piecewise retail orders, a separate small size-fast pick area is design called “forward buffer” wherein pallets are allocated from reserve area. Due to non-uniform pallets, the static allocation policy diminishes forward space utilization and also, more than practically required buffer size has been identified as wastage. Thus, dynamic storage allocation policy is required to design for reducing storage wastage and improving throughput considering non-uniform unit load sizes. The purpose of this paper is to model such policy and develop an e-decision support system assisting enterprise practitioners with real-time decision making.Design/methodology/approachThe research method is developed as a dynamic storage allocation policy and mathematical modeled as knapsack-based heuristics. The execution procedure of policy is explained as an example and tested with case-specific data. The developed model is implemented as a web-based support system and tested with rational data instances, as well as overcoming prejudices against single case findings.FindingsThe provided model considers variable size storage-handling unit loads and recommends number of pallets allocations in forward area reducing storage wastes. The algorithm searches and suggests the “just-right” amount of allocations for each product balancing existing forward capacity. It also helps to determine “lean buffer” size for forward area ensuring desired throughput. Sensitivity and buffer performance analysis is carried out for Poisson distributed data sets followed by research synthesis.Practical implicationsWarehouse practitioners can use this model ensuring a desired throughput level with least forward storage wastages. The model driven e-decision support system (DSS) helps for effective real-time decision making under complicated business scenarios wherein products are having different physical dimensions. It assists the researchers who would like to explore the emerging field of “lean” adoption in enterprise information and retail-distribution management.Originality/valueThe paper provides an inventive approach endorsing lean thinking in storage allocation policy design for a forward-reserve model. Also, the developed methodology incorporating features of e-DSS along with quantitative modeling is an inimitable research contribution justifying rational data support.

Relay Selection for Cooperative Relaying Networks With Small Buffers

Buffer-aided relaying, which combines relay selection and packet buffering, has recently been studied to mitigate throughput and multiplexing gain loss of two-hop relaying protocols. However, existing buffer-aided relaying schemes require large buffers and a long initialization process for minimizing the outage probability. In this paper, a new buffer-aided relaying scheme is proposed that considers both instantaneous buffer status and channel state information (CSI) for making the relay selection decision. Theoretical analysis is performed to get some insights into the proposed scheme. We present numerical results to validate the analysis accuracy and demonstrate the improvement of the proposed scheme in terms of outage probability, buffer size requirement, and average delay, compared with existing buffer-aided relaying schemes.

Localized paging in proxy mobile IPv6 networks

In Proxy Mobile IPv6 (PMIPv6) networks, proxy registrations are performed even for idle mobile nodes (MNs), resulting in unnecessary signaling traffic and protocol cost. Although there have been many paging techniques aimed at reducing the unnecessary location updates, those are mainly focused on telecommunication systems and how to adopt IP paging schemes in PMIPv6 is not yet well studied. In this paper, we introduce a new paging scheme that optimizes paging performance in a localized manner. The proposed localized paging scheme pages the idle MN through a mobility access gateway (MAG) while the operation is transparent to a local mobility anchor (LMA) in a PMIPv6 network domain. In this way, a bottleneck risk at the LMA can be avoided, without a huge requirement of buffer size and paging singling cost. We develop a thorough analytical model for evaluating the performance of the proposed scheme, compared with a LMA-based paging scheme in terms of the buffer size requirement and signaling cost. Analytical results demonstrate that the proposed paging scheme can significantly reduce the signaling cost for PMIPv6, achieving a less buffer size requirement and of course shorter paging delay, compared with those of the LMA-based paging scheme.

Analyzing the impact of buffer capacity on crosspoint-queued switch performance

We use both theoretical analysis and simulations to study the impact of crosspoint-queued (CQ) buffer size on CQ switch throughput and delay performance under different traffic models, input loads, and scheduling algorithms. In this paper, we present the following. 1) We prove the stability of CQ switch using any work-conserving scheduling algorithm. 2) We present an exact closed-form formula for the CQ switch throughput and a nonclosed- form but convergent formula for its delay using static nonwork- conserving random scheduling algorithms with any given buffer size under independent Bernoulli traffic. 3) We show that the above results can serve as a conservative guide on deciding the required buffer size in pure CQ switches using work-conserving algorithms such as the random scheduling, under independent Bernoulli traffic. 4) Furthermore, our simulation results under real-trace traffic show that simple round-robin and random workconserving algorithms can achieve quite good throughput and delay performance with a feasible crosspoint buffer size. Our work reveals the impact of buffer size on the CQ switch performance and provides a theoretical guide on designing the buffer size in pure CQ switch, which is an important step toward building ultra-highspeed switch fabrics.

Routing Based on Information about the Routes of Fixed-Route Traveling Nodes and on Destination Areas Aimed at Reducing the Load on the DTN

In recent years, the interest in delay/disruption tolerant networking (DTN) is growing as a means of communication in times of disaster. To ensure that a DTN works well in an emergency, it is desirable to promote general use of the DTN, so that it will also be used in normal times. Since the DTN uses mobile terminals and vehicles, which are not dedicated network devices, as relay nodes, the routing method should be such that it does not impose a large processing load on relay nodes. This paper considers use of a DTN for a day-to-day service of delivering content to a specific area and proposes a new routing method that is based on information about the routes of fixed-route traveling nodes, such as public transportation vehicles. The destination of a bundle is specified not by a terminal identifier, but by an area, which is identified by its location information. This paper presents an outbound-type bundle protocol, which is used by relay nodes when they have received a forwarding-bundle request from a sending terminal and try to determine whether the bundle can reach its destination area. Using simulation, the superiority of the proposed routing was confirmed by comparing it to existing routing methods in terms of the bundle arrival rate and factors that affect the network load, such as the number of bundle copies, the number of hops and the maximum required buffer size.

Design and test of a pulse-width modulator and driver for space-borne GaN switch mode power amplifiers in P-band

In this paper, the design and test of a single-chip RF pulse-width modulator and driver (PWMD) aimed at exciting a high-power class-E GaN high-power stage at 435 MHz is described. For the required buffer size, avoiding potential ringing of the pulses within the buffer structure presents a major challenge in the design process. Therefore, a smaller test chip capable of driving capacitive loads of up to 5 pF was initially designed, fabricated, and tested. An approach based on three-dimensional electromagnetic simulations was used to validate the test results and offers excellent simulation accuracy. Based on the results obtained for test chip an enlarged PWMD chip capable of driving a 40 W high-power stage has been designed and tested on passive loads representing the targeted final stage.

Analysis of the System with Vacations under Poissonian Input Stream and Constant Service Times

In the paper approximate formulas for the mean waiting times and the buffer dimensioning in the system with vacations fed by the stream of Poissonian type with constant service times is shown. Furthermore, in the considered system the time intervals of the availability/notavailability of the service are constant and are run alternately according to the assumed cycle. More precisely, presented approach begin with derivation of the mean waiting times and, on the basis of this, the required buffer size for guaranteeing the losses less than predefined value is estimated. The accuracy of the presented analytical formulas is on a satisfactory level. The formulas were used for the System IIP dimensioning.