Buffer Hit Ratio Research Articles

Firefly Optimization-Based Buffer Replacement Algorithm to Improve Nand Flash Memory Performance

Because of its shock tolerance, nonvolatility, low power consumption, and fast I/O speed, flash memory is often used for storage in consumer applications and, more recently, in the business computer environment. State drives SSDs to have not-in-place updates and asymmetric I/O latency, with write/erase operations being substantially slower than read operations. In this paper, we propose a buffer replacement technique FBRA that uses the firefly algorithm (FA) to precisely predict whether the pages residing in the buffer is hot or cold. The firefly optimization estimates hot fitness value of each page in the buffer in order to accurately classify them as hot or cold by characterizing precisely the temporal and spatial locality. To increase the hit ratio and SSD buffer use, the frequently used pages should stay longer in buffer compared to other pages. The proposed approach outperforms the existing SSD buffer management strategies regarding buffer hit ratio, write count, and runtime. Trace-driven simulation is done using FlashDB Simulator to support the performance of our approach surpasses various traditional buffer replacement policies.

Firefly Optimization-Based Buffer Replacement Algorithm to Improve Nand Flash Memory Performance

Because of its shock tolerance, nonvolatility, low power consumption, and fast I/O speed, flash memory is often used for storage in consumer applications and, more recently, in the business computer environment. State drives SSDs to have not-in-place updates and asymmetric I/O latency, with write/erase operations being substantially slower than read operations. In this paper, we propose a buffer replacement technique FBRA that uses the firefly algorithm (FA) to precisely predict whether the pages residing in the buffer is hot or cold. The firefly optimization estimates hot fitness value of each page in the buffer in order to accurately classify them as hot or cold by characterizing precisely the temporal and spatial locality. To increase the hit ratio and SSD buffer use, the frequently used pages should stay longer in buffer compared to other pages. The proposed approach outperforms the existing SSD buffer management strategies regarding buffer hit ratio, write count, and runtime. Trace-driven simulation is done using FlashDB Simulator to support the performance of our approach surpasses various traditional buffer replacement policies.

Improving Fairness for SSD Devices through DRAM Over-Provisioning Cache Management

Modern NVMe SSDs have been widely deployed in multi-tenant cloud computing environments or multi-programming systems. When multiple applications concurrently access one SSD hardware, unfairness within the shared SSD will slow down the application significantly and lead to a violation of service level objectives. However, traditional data cache management within SSDs mainly focuses on improving cache hit ratio, which causes data cache contention and sacrifices fairness among multiple applications. In this paper, we propose a DRAM-based Over-Provisioning (OP) cache management mechanism, named Justitia, to reduce data cache contention and improve fairness for modern SSDs. Justitia consists of two stages including <i>Static-OP</i> stage and <i>Dynamic-OP</i> stage. Through the novel OP mechanism in the two stages, Justitia reduces the max slowdown by <inline-formula><tex-math notation="LaTeX">$4.5\times$</tex-math></inline-formula> on average. At the same time, Justitia increases fairness by <inline-formula><tex-math notation="LaTeX">$20.6\times$</tex-math></inline-formula> and buffer hit ratio by <inline-formula><tex-math notation="LaTeX">$19.6\%$</tex-math></inline-formula> averagely, compared with the traditional shared mechanism.

Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

Buffer Management With Append-Only Data Isolation for Improving SSD Performance

The number of applications that can access a storage device simultaneously has increased as a result of the increase in storage capacity and the emergence of hyperscale environments. In multi-application environments, the request for append-only data to storage from applications such as log-structured merge-tree-based key-value (LSMKV) stores can negatively affect the storage-internal buffer hit ratio of other applications. This is because frequently re-accessed data can be evicted from the buffer via the intensive requests of append-only data that are rarely re-accessed. This degradation in the buffer hit ratio increases the storage access latency of applications. Herein, we propose a buffer management method to increase the buffer hit ratio of non-append-only data (or applications) in multi-application environments. The proposed method (1) defines large-sequential writes (that are not overwritten) and all reads on them as append-only input/output (I/O), (2) detects I/O, matching the access pattern of append-only data of LSMKVs, (3) allocates the append-only read/write requests into separate small buffer spaces, and (4) evicts the append-only data from the buffer when free buffer space is required. Because the proposed method stores append-only data of an LSMKV in buffer spaces with a limited size, it can increase the buffer hit ratio of applications that frequently re-access its data. Experimental results show that the proposed method can increase the buffer hit ratio of hot-data-intensive applications and the total buffer hit ratio by 70% and 46.8%, on average, respectively, in comparison to the existing buffer management techniques.

A Group-Based Buffer Management for SSD

Random writes limit the application of SSDs significantly because of their poor latency and high garbage collection overhead. Traditional page-based and block-based buffer management algorithms cannot achieve both high buffer hit ratio and good destage sequentiality at the same time. In this paper, we propose a hybrid scheme called the group-based buffer management (GBBM). To improve buffer hit ratio and decrease write/erase counts, GBBM divides buffer space into Page Region and Group Region. The frequently accessed data pages are placed at the Page Region, while infrequently accessed random written data are grouped in the Group Region. GBBM has been evaluated extensively through simulations. The write counts of GBBM show an average decrease of 12.7% compared with page-level buffer scheme. Compared with hybrid buffer management such as CBM, GBBM decreases the average write/erase count by 14.3%/12.1%. The write hit ratio of GBBM shows a 4.5% improvement as compared with PAB. The proposed GBBM can significantly reduce the number of write operations while maintaining a relatively high buffer hit ratio.

VBBMS: A Novel Buffer Management Strategy for NAND Flash Storage Devices

NAND flash storage devices are gaining popularity in consumer electronic devices, such as digital cameras, tablet PCs, and smartphones, due to their attractive features. However, write operations significantly limit the performance of the flash storage in consumer electronics devices due to their long latency and heavy overhead of garbage collection. Hence, NAND flash storage devices generally use RAM memory as a buffer to improve their write performance and to extend their lifetime. This paper proposes a novel buffer management algorithm (BMA), called as virtual-block-based buffer management scheme (VBBMS), which can make full use of both temporal and spatial localities at virtual-block level. The main difference with the existing BMAs is that the management granularity of VBBMS is a virtual block, while the management granularity of existing BMAs is a page or a block. In addition, VBBMS divides RAM into random request service region (RRSR), which is responsible for handling random requests, and sequential request service region (SRSR), which is responsible for handling sequential requests. When replacement happens, VBBMS selects victim virtual-block according to LRU policy in RRSR and first-in first-out (FIFO) policy in SRSR. VBBMS has been extensively evaluated under various realistic workloads, and our benchmark results show that VBBMS can improve buffer hit ratio, reduce response time, and erase times, compared to five existing BMAs.

An Advanced Adaptive Least Recently Used Buffer Management Algorithm for SSD

The traditional solid-state drive buffer management algorithm generally adopts fixed structures and parameters, leading to their poor adaptability. For example, after the underlying flash translation layer (FTL) or the upper workload is changed, the traditional algorithm’s performance fluctuates significantly. Focusing on this problem, based on the cross-layer aware method, we propose an Advanced Adaptive Least Recently Used buffer management algorithm (AALRU). The core idea of the AALRU is that by sensing the characteristics of the upper workload and the status of the underlying FTL, the AALRU adaptively adjusts its structure, parameters, and write-back strategy to optimize the buffer’s performance. First, the AALRU divides the buffer into two parts: read buffer and write buffer, and their proportion is adjusted by sensing the read-write characteristics of the workload and the underlying read-write latency. Second, the AALRU employs different granularities to manage the buffer. On one hand, for data loading and migrating, the AALRU adopts page-level granularity, which can avoid the problem of hot and cold data page entanglement in block management, and thus improve the buffer hit ratio. On the other hand, for data writing back to the FTL, the AALRU adopts block-level granularity, which can enhance the continuity of write requests and thus reduce the underlying FTL’s garbage collection overhead. Finally, when the clustered data are written back, by sensing the underlying FTL’s garbage collection status, the AALRU adaptively adjusts the page-padding trigger threshold to reconstruct the continuity of the write-back data, which can mitigate the underlying FTL’s garbage collection overhead. The experimental results show that the AALRU has the best adaptability to different FTLs and test workloads, and it can achieve optimal or near-optimal results.

SUPA

To design the write buffer and flash translation layer (FTL) for a solid-state drive (SSD), previous studies have tried to increase overall SSD performance by parallel I/O and garbage collection overhead reduction. Recent works have proposed pattern-based managements, which uses the request size and read- or write-intensiveness to apply different policies to each type of data. In our observation, the locations of read and write requests are closely related, and the pattern of each type of data can be changed. In this work, we propose SUPA, a single unified read-write buffer and pattern-change-aware FTL on multi-channel SSD architecture. To increase both read and write hit ratios on the buffer based on locality, we use a single unified read-write buffer for both clean and dirty blocks. With proposed buffer, we can increase buffer hit ratio up to 8.0% and reduce 33.6% and 7.5% of read and write latencies, respectively. To handle pattern-changed blocks, we add a pattern handler between the buffer and the FTL, which monitors channel status and handles data by applying one of the two different policies according to the pattern changes. With pattern change handling process, we can reduce 1.0% and 15.4% of read and write latencies, respectively. In total, our evaluations show that SUPA can get up to 2.0 and 3.9 times less read and write latency, respectively, without loss of lifetime in comparison to previous works.

이중 쓰기 버퍼를 활용한 SSD의 성능 향상 및 수명 연장 기법

In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.

F-LRU: An efficient buffer replacement algorithm for NAND flash-based databases

In this paper, an efficient buffer replacement algorithm called F-LRU is proposed for NAND flash-based databases. The proposed F-LRU algorithm maintains two Least Recently Used (LRU) page lists, which are a mixed page list and a dirty page list. The proposed F-LRU algorithm improves the buffer hit ratio by first evicting cold clean pages and reduces the number of write operations by giving dirty pages a second chance to stay in the buffer. The proposed F-LRU algorithm can dynamically adjust the lengths of the mixed page list and the dirty page list to adapt to different kinds of NAND flash memory with different cost ratios of write operation to read operation. A series of trace-driven simulations have been conducted on two kinds of NAND flash memory with cost ratios 118:1 and 2:1. Experimental results show that the proposed F-LRU algorithm performs better than the state-of-the-art buffer replacement algorithms in terms of the buffer hit ratio, the number of write operations, and the runtime.

Energy-aware buffer management scheme for NAND and flash-based consumer electronics

Because NAND flash memory shows a number of remarkable advantages such as non-volatility, high access performance, low power consumption, shock resistance, and small size, it has become the dominant data storage device for consumer electronics. However, NAND flash memory exhibits very different physical characteristics from hard disks so that existing buffer management schemes designed for hard disks perform badly when they are deployed on NAND flash-based consumer electronics directly. In this paper, an energy-aware buffer management scheme is proposed for NAND flash-based consumer electronics. The proposed scheme introduces a Low Cost First strategy for selecting a victim page and a clustering algorithm for grouping dirty data. Experimental results show that the proposed scheme performs better than existing buffer management schemes in terms of the buffer hit ratio, the number of write operations, and the energy consumption.

Page replacement algorithm based on counting bloom filter for NAND flash memory

In this paper, a page replacement algorithm based on counting bloom filter for NAND flash memory is proposed. This algorithm mainly consists of two schemes: the data separation scheme based on counting bloom filter and the free block management scheme. The former is used for classifying the dirty subpages within the victim pages as hot or cold and the latter is used for classifying the free blocks within the free block list into young or old. Moreover, in order to improve the performance of NAND flash memory, the hot dirty subpages are written back to the young free block, and the cold subpages are distributed to the old free block. Experimental results show that the proposed algorithm performs better than the existing page replacement algorithms in terms of the number of write operations, the total runtime, the buffer hit ratio and the degree of wear leveling.

A Popularity-Aware Buffer Management to Improve Buffer Hit Ratio and Write Sequentiality for Solid-State Drive

Random writes significantly limit the application of flash memory in enterprise environment due to its poor latency, shorten lifetime and high garbage collection overhead. Solid-state drive (SSD) uses a small part of memory as buffer to reduce random write and extend lifetime. Existing block-based buffer management schemes exploit spatial locality to improve the write sequentiality at a cost of low buffer hit ratio. In this paper, we propose a novel buffer management scheme referred to as PAB, which adopts both buffer hit ratio and write sequentiality as design objectives. Leveraging block popularity, PAB makes full use of both temporal and spatial localities at block level. When replacement happens, PAB selects victim block based on block popularity, page counter and block dirty flag. As universal buffer, PAB serves both read and write requests to increase the possibility to form sequential write. PAB has been extensively evaluated under real enterprise workloads. Our benchmark results conclusively demonstrate that PAB can achieve up to 72% performance improvement and 308% block erasure reduction compared to existing buffer management schemes.

AD-LRU: An efficient buffer replacement algorithm for flash-based databases

Flash memory has characteristics of out-of-place update and asymmetric I/O latencies for read, write, and erase operations. Thus, the buffering policy for flash-based databases has to consider those properties to improve the overall performance. This article introduces a new approach to buffer management for flash-based databases, called AD-LRU (Adaptive Double LRU), which focuses on improving the overall runtime efficiency by reducing the number of write/erase operations and by retaining a high buffer hit ratio. We conduct trace-driven experiments both in a simulation environment and in a real DBMS, using a real OLTP trace and four kinds of synthetic traces: random, read-most, write-most, and Zipf. We make detailed comparisons between our algorithm and the best-known competitor methods. The experimental results show that AD-LRU is superior to its competitors in most cases.

멀티미디어 파일 시스템을 위한 효율적 버퍼 관리

멀티미디어 데이터는 연속적이고 대용량이며 실시간 특성을 가지고 있으므로 주문형 비디오(VOD)를 서비스하는 멀티미디어 서버에서는 잦은 디스크 입출력 및 프로세서와 디스크 사이의 속도 차이로 인한 시스템 성능 저하가 발생한다. 따라서 멀티미디어 데이터에 대한 디스크 접근을 줄이는 효율적인 버퍼 관리가 필요하다. 본 논문에서는 멀티미디어 서버에서 연속적이고 실시간 특성이 있는 비디오 데이터를 대상으로 버퍼의 적중률을 높여 디스크 접근을 줄이고, 동시에 서비스 받는 사용자수를 늘리며 시스템 전반에 걸친 버퍼 이용도를 높이는 버퍼 관리 방법에 대하여 연구한다. 이를 위해 여러 가지 자원 관리 알고리즘 및 정책변화에 대한 시뮬레이션을 통하여 다양한 환경하에서의 각 알고리즘의 성능을 비교 분석한다. The multimedia data for video-on-demand(VOD) service has large, continuous and real time characteristics. The frequent disk I/O operations takes much time and decrease the system performance in multimedia services. Therefore the efficient buffer management is needed in order to reduce the disk accesses to multimedia data. This paper addresses how to increase the buffer hit ratio and the number of users in a multimedia service like VOD by increasing the utility of buffer. This paper also simulated various resource management algorithms and strategies and evaluated, compared and analyzed their performances.

Managing Frequent Updates in R-Trees for Update-Intensive Applications

Managing frequent updates is greatly important in many update-intensive applications, such as location-aware services, sensor networks, and stream databases. In this paper, we present an R-tree-based index structure (called Rsb-tree, R-tree with semibulk loading) for efficiently managing frequent updates from massive moving objects. The concept of semibulk loading is exploiting a small in-memory buffer to defer, buffer, and group the incoming updates and bulk-insert these updates simultaneously. With a reasonable memory overhead (typically only 1 percent of the whole data set), the proposed approach far outperforms the previous works in terms of update and query performance as well in a realistic environment. In order to further increase buffer hit ratio for the proposed approach, a new page-replacement policy that exploits the level of buffered node is proposed. Furthermore, we introduce the concept of deferring threshold ratio (dtr) that simply enables deferring CPU- and I/O-intensive operations such as node splits and removals. Extensive experimental evaluation reveals that the proposed approach is far more efficient than previous approaches for managing frequent updates under various settings.

LRU-WSR: integration of LRU and writes sequence reordering for flash memory

Most mobile devices are equipped with a NAND flash memory even if it has characteristics of not-in-place update and asymmetric I/O latencies among read, write, and erase operations: write/erase operations are much slower than a read operation in a flash memory. For the overall performance of a flash memory system, the buffer replacement policy should consider the above severely asymmetric I/O latencies. However, existing LRU buffer replacement algorithm cannot deal with the above problem. This paper proposes the LRU-WSR buffer replacement algorithm that enhances LRU by reordering writes of not-cold dirty pages from the buffer cache to flash storage. The enhanced LRU-WSR algorithm focuses on reducing the number of write/erase operations as well as preventing serious degradation of buffer hit ratio. The experimental results show that the LRU-WSR outperforms other algorithms including LRU, CF-LRU, and FAB1.

Dynamic Affinity Cluster Allocation in a Shared Disks Cluster

A shared disks (SD) cluster couples multiple computing nodes for high performance transaction processing, and all nodes share a common database at the disk level. In the SD cluster, a front-end router selects a node for an incoming transaction to be executed. An affinity-based routing can increase the buffer hit ratio of each node by clustering transactions referencing similar data to be executed on the same node. However, the affinity-based routing is non-adaptive to the changes of the system load. This means that a specific node would be overloaded if corresponding transactions rush into the system. In this paper, we propose a new transaction routing algorithm, named Dynamic Affinity Cluster Allocation (DACA). DACA can make an optimal balance between the affinity-based routing and indiscriminate sharing of load in the SD cluster. As a result, DACA can increase the buffer hit ratio and reduce the frequency of inter-node buffer invalidations while achieving the dynamic load balancing.

Managing Multiuser Database Buffers Using Data Mining Techniques

In this paper, we propose a data-mining-based approach to public buffer management for a multiuser database system, where database buffers are organized into two areas – public and private. While the private buffer areas contain pages to be updated by particular users, the public buffer area contains pages shared among different users. Unlike traditional buffer management strategies where limited knowledge of user access patterns is used, the proposed approach discovers knowledge from page access sequences of user transactions and uses it to guide public buffer placement and replacement. A prefetch strategy is exploited based on the discovered page access knowledge. In practice, to make such a data-mining-based buffer management approach tractable, we present a soft variation to approximate our absolute best buffer replacement solution. The knowledge to be discovered and the discovery methods are discussed in the paper. The effectiveness of the proposed approach was investigated through a simulation study. The results indicate that with the help of the discovered knowledge, the public buffer hit ratio can be improved significantly, while the added computational complexity, compared to the achievement in buffer hit ratio, is less. In some situations, the time cost of the data-mining-based buffer management policy is even lower than that of the simplest buffer management policy.